Unit 5: Registers and Counters

Registers

A stage in a shift register consists of:

A latch
A flip-flop
A byte of storage
Four bits of storage

To serially shift a byte of data into a shift register, there must be:

One clock pulse

One load pulse
Eight clock pulses
One clock pulse for each 1 in the data

To parallel load a byte of data into a shift register with a synchronous load, there must be

One clock pulse

One clock pulse for each 1 in the data
Eight clock pulses
One clock pulse for each on in the data

A group of bits (10110101) is serially shifted (right-most bit first) into an 8-bit parallel output shift
register with an initial state of 11100100. After two clock pulses, the register contains:

01011110
10110101
01111001
00101101

With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in:

80 μs
8 μs
80 ms
10 μs

With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register:

In 8 μs
In the propagation delay time of eight flip-flops
In 1 μs
In the propagation delay time of one flip-flop

To serially shift a byte of data into a shift register, there must be:

One clock pulse

One load pulse
Eight clock pulses
One clock pulse for each 1 in the data

To parallel load a byte of data into a shift register with a synchronous load, there must be:
One clock pulse
One clock pulse for each 1 in the data
Eight clock pulses
One clock pulse for each on in the data

A group of bits (10110101) is serially shifted (right-most bit first) into an 8-bit parallel output shift
register with an initial state of 11100100. After two clock pulses, the register contains:

01011110
10110101
01111001
00101101

With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in:

80 μs
8 μs
80 ms
10 μs

When an 8-bit serial in/serial out shift register is used for a 24 μs time delay, the clock frequency
must be:

41.67 kHz
333 kHz
125 kHz
8 MHz

In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses,
the data outputs are ________

1110
0001
1100
1000
 Counters

Asynchronous counters are known as

Ripple counters
Multiple clock counters
Decade counters
Modulus counter

An asynchronous counter differs from a synchronous counter in:

The number of states in its sequence

The method of clocking
The type of flip-flops used
The value of the modulus

The modulus of a counter is:

The number of flip-flops

The actual number of states in its sequence
The number of times it recycles in a second
The maximum possible number of states

A 3-bit binary counter has a maximum modulus of:

3
6
8
16

A 4-bit binary counter has a maximum modulus of:

16
32
8
4

A modulus-12 counter must have:

12 flip-flops
3 flip-flops
4 flip-flops
Synchronous Clocking

Which one of the following is an example of a counter with a truncated modulus?

Modulus 8
Modulus 14
Modulus 16
Modulus 32

A BCD counter is an example of:

A full-modulus counter
A Decade Counter
A truncated-modulus counter
Both B and C

Which of the following is an invalid state in an 8421 BCD counter?

1100
0010
0101
1000

Three cascaded modulus -10 counters have an overall modulus of:

30
100
1000
10000

A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5 counter, a

modulud-8 counter, and two modulud-10 counters. The lowest output frequency possible is:

10 kHz
2.5 kHz
5 kHz
25 kHz

A 4-bit up/down counter is in the binary state of zero. The next state in the DOWN node is:

0001
1111
1000
1110

The terminal count of a modulud-13 binary counter is:

0000
1111
1101
1100

A modulus-10 Johnson counter requires:

10 flip-flops
4 flip-flops
5 flip-flops
12 flip-flops

A modulus-10 Ring counter requires a minimum of:

10 flip-flops
5 flip-flops
4 flip-flops
12 flip-flops

When an 8-bit serial in/serial out shift register is used for a 24 μs time delay, the clock frequency
must be:
41.67 kHz
333 kHz
125 kHz
8 MHz

Three cascaded modulus -10 counters have an overall modulus of:

30
100
1000
10000

A 4-bit up/down counter is in the binary state of zero. The next state in the DOWN mode is:

0001
1111
1000
1110

A counter circuit is usually constructed of ____________

A number of latches connected in cascade form

A number of flip-flops connected in cascade
A number of NAND gates connected in cascade form
A number of NOR gates connected in cascade form

Internal propagation delay of asynchronous counter is removed by ____________

Ripple counter
Ring counter
Modulus counter
Synchronous counter

A 3-bit binary counter has a maximum modulus of

8
6
3
16

UP Counter is ____________

It counts in upward manner

It count in down ward manner
It counts in both the direction
Toggles between Up and Down count

An asynchronous counter differs from a synchronous counter in:

The number of states in its sequence

The method of clocking
The type of flip-flops used
The value of the modulus
The modulus of a counter is:

The number of flip-flops

The actual number of states in its sequence
The number of times it recycles in a second
The maximum possible number of states

A 4-bit up/down counter is in the binary state of zero. The next state in the DOWN node is:

0001
1111
1000
1110

With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in:

80 μs
8 μs
80 ms
10 μs

With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register:

In 8 μs
In the propagation delay time of eight flip-flops
In 1 μs
In the propagation delay time of one flip-flop

For the circuit shown in figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is
assumed to be zero.

If the clock (Clk) frequency is 1 GHz, then the counter behaves as a:

Mod-5 counter
Mod-6 counter
Mod-7 counter
Mod-8 Counter
A mod-n counter using a synchronous binary up-counter with synchronous clear input is shown in
figure. The value of n is ________

Mod-2 counter
Mod-4 counter
Mod-5 counter
Mod-6 counter

The circuit shown consists of J-K flip-flops, each with an active low asynchronous reset (Rd’ input). The
counter corresponding to this circuit is:

A modulo-5 binary up counter

A modulo-6 binary down counter
A modulo-5 binary down counter
A modulo-6 binary up counter

A three bit pseudo random number generator is shown. Initially the value of output Y = Y2Y1Y0 is set to
111. The value of output Y after three clock cycles is:

000
001
010
100
When the output Y in the circuit below is "1", it implies that data has

changed from "0" to "1"

changed from "1" to "0"
changed in either direction
not changed

Two D flip-flops are connected as a synchronous counter that goes through the following Q BQA
sequence 00 -- 11 -- 01 -- 10 -- 00 --

The combinations to the inputs DA and DB are:

Ans: D

Assuming that flip-flops are n reset condition initially, the count sequence observed at Q A in the
circuit shown is:

0010111…
0001011…
0101111
0110100

What are the counting stages (Q1, Q2) for the counter shown in the figure below?
 11, 10, 00, 11, 10…
01, 10, 11, 00, 01…
00, 11, 01, 10, 00…
01, 10, 00, 01, 10…

For the circuit shown, the counter state (Q1Q0) follows the sequence:

00, 01, 10, 11, 00…

00, 01, 10, 00, 01…
00, 01, 11, 00, 01…
00, 10, 11, 00, 10…

A switch-tail ring counter is made by using a single D flip-flop. The resulting circuit is a:

SR flip-flop
JK flip-flop
D flip-flop
T flip-flop

In a JK flip-flop, we have J = Q’ and K = 1. Assume the flip-flop was initially cleared and then clocked for 6
pulses, the sequence at the Q output will be:
010000
011001
010010
010101

A 4-bit shift register circuit configured for right-shift operation, i.e. Din  A, A  B, B C, C  D, is
shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to
reach the state ABCD = 1111 is ______________.

Answer: 10.0 to 10.0

The minimum number of flip-flops needed to construct a BCD decade counter is:

4
3
10
None of these

A shift counter comprising five flip-flops with an inverse feedback from the output of the MSB flip-flop
to the input of the LSB flip-flop is a:

Divide - by- 32 counter

Divide-by-10 counter
Divide-by-5 counter
Five-bit shift register

A four-bit binary UP/DOWN counter is initially reset to 0000. The UP/DOWN mode select terminal
designated as U’/D on the pin connection diagram of the IC is tied to logic HIGH level. What would be
the counter’s output state at the end of the first clock pulse?

0001
1000
1111
0000

A counter that has a modulus of 64 should use a minimum of:

6 flip-flops
6 J-K type flip-flops
6 D flip-flops
64 flip-flops

A MOD-32 binary synchronous counter would require:

6 flip-flops and 3 AND gates

5 flip-flops
5 flip-flops and 3 AND gates
None of these

Mark the false statement:

Ring counter is a synchronous counter

Johnson counter is a synchronous counter
The output of a ring counter is always a square wave
The decoding circuitary for a Johnson counter is simpler than that of a binary counter

In what type of shift register do we have access to only the leftmost and rightmost flip-flops?

SISO Register
SIPO Register
PISO Register
PIPO Register
An octal D flip-flop IC can be used to construct a:

MOD-8 ring counter

MOD-16 ring counter
MOD-32 Johnson counter
MOD-16 Johnson counter
Both (a) and (d)

The minimum number of flip-flops required to construct a MOD-10 Johnson counter and a MOD-5 ring
counter, respectively, are:

10, 05
05, 10
05, 05
10, 10

In any synchronous counter,

All filp-flops change state at the same time

Only D flip-flops are used
The counter responds to negative going clock edges
Each flip-flop output serves as clock input to the next flip-flop

A five-bit counter:

Has a modulus of 5
Has a modulus of 2
Cannot have a modulus that is greater than 32
Both (c) and (d) are true

All BCD counters:

Are decade counters because all decade counters are BCD counters
Are not decade counters
Have a modulus of 10
Are constructed with only presettable D flip-flops
Both (C) and (D) are correct.

The decoding glitches are far more likely to occur in the case of :

Ripple Counters
Parallel Counters
Johnson Counters
Ring Counters

The problem of decoding glitches can be:

Ripple counters
Parallel counters
Johnson counters
Ring counters

A five-bit Johnson counter in cascade with a five - bit ring counter produces a frequency divider of:

25
10
50
15

A cascade arrangement of four stages of BCD counters can be used to count a maximum of:

1111 pulses
1111111111111111 pulses
1001100110011001 pulses
9999 pulses

A four-bit pre-settable down counter initially loaded with 0101 will divide the input clock frequency
by:

16
5
11
10

In digital logic, a counter is a device which ____________

Counts the number of outputs

Stores the number of times a particular event or process has occurred
Stores the number of times a clock pulse rises and falls
Counts the number of inputs

What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’
number of flip-flops?

a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2(n+1/2)

How many types of the counter are there?

2
3
4
5

Explanation: Counters are of 3 types, namely, (i) asynchronous/synchronous, (ii) single and multi-mode &
(iii) modulus counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter,
Up/Down Counter and such like.

A decimal counter has ______ states.

5
10
15
20
Ripple counters are also called ____________

SSI counters
Asynchronous counters
Synchronous counters
VLSI counters

Three decade counter would have ____________

2 BCD counters
3 BCD counters
4 BCD counters
5 BCD counters

Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD
counters. Thus, a three decade counter will count from 0 to 29.

BCD counter is also known as ____________

Parallel counter
Decade counter
Synchronous counter
VLSI counter

The parallel outputs of a counter circuit represent the _____________

Parallel data word

Clock frequency
Counter modulus
Clock count

How many natural states will there be in a 4-bit ripple counter?

4
8
16
32

A ripple counter’s speed is limited by the propagation delay of _____________

Each flip-flop
All flip-flops and gates
The flip-flops only with gates
Only circuit gates

One of the major drawbacks to the use of asynchronous counters is that ____________

Low-frequency applications are limited because of internal propagation delays

High-frequency applications are limited because of internal propagation delays
Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency
counting applications
Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications

What happens to the parallel output word in an asynchronous binary down counter whenever a clock
pulse occurs?
The output increases by 1
The output decreases by 1
The output word increases by 2
The output word decreases by 2

How many flip-flops are required to construct a decade counter?

4
8
5
10

The terminal count of a typical modulus-10 binary counter is ____________

0000
1010
1001
1111

Explanation: A binary counter counts or produces the equivalent binary number depending on the cycles of
the clock input. Modulus-10 means count from 0 to 9. So, the terminal count is 9 (1001).

How many different states does a 3-bit asynchronous counter have?

2
4
8
16

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay.
The total propagation delay (tp(total)) is ____________

12 ms
24 ns
48 ns
60 ns

An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional
states are required?

1
2
8
15

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q
output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________

15 ns
30 ns
45 ns
60 ns

Three cascaded decade counters will divide the input frequency by ____________
10
20
100
1000

Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e. 10*10*10=1000 states.

A 4-bit counter has a maximum modulus of ____________

3
6
8
16

Which of the following statements are true?

Asynchronous events does not occur at the same time

Asynchronous events are controlled by a clock
Synchronous events does not need a clock to control them
Only asynchronous events need a control clock

A down counter using n-flip-flops count ______________

Downward from a maximum count

Upward from a minimum count
Downward from a minimum to maximum count
Toggles between Up and Down count

UP Counter is ____________

It counts in upward manner

It count in down ward manner
It counts in both the direction
Toggles between Up and Down count

DOWN counter is ____________

It counts in upward manner

It count in downward manner
It counts in both the direction
Toggles between Up and Down count

How many different states does a 3-bit asynchronous down counter have?

2
4
6
8

In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop
goes from HIGH to LOW.

MSB flip-flop
LSB flip-flop
Master slave flip-flop
Latch

In a 3-bit asynchronous down counter, the initial content is ____________

000
111
010
101

In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content
becomes ____________

000
111
101
010

In order to check the CLR function of a counter ____________

Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset
state
Ground the CLR input and check to be sure that all of the Q outputs are LOW
Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q
outputs are toggling

Modulus refers to ____________

A method used to fabricate decade counter units

The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
An input on a counter that is used to set the counter state, such as UP/DOWN
The maximum number of states in a counter sequence

A sequential circuit design is used to ____________

Count up
Count down
Decode an end count
Count in a random order
In general, when using a scope to troubleshoot digital systems, the instrument should be triggered by
____________

The A channel or channel 1

The vertical input mode, when using more than one channel
The system clock
Line sync, in order to observe troublesome power line glitches

Which counters are often used whenever pulses are to be counted and the results displayed in
decimal?

Synchronous
Bean
Decade
BCD
The minimum number of flip-flops that can be used to construct a modulus-5 counter is ____________

3
8
5
10

Normally, the synchronous counter is designed using ____________

S-R flip-flops
J-K flip-flops
D flip-flops
T flip-flops

Explanation: Since J-K flip-flops have options of recovery from toggle condition and by using less number of J-
K flip-flops a synchronous counter can be designed. So, it is more preferred. Also, because JK-flip-flops
resolves the problem of Forbidden States.

MOD-16 counter requires ________ no. of states.

8
4
16
32

What is a state diagram?

It provides the graphical representation of states

It provides exactly the same information as the state table
It is same as the truth table
It is similar to the characteristic equation

High speed counter is ____________

Ring counter
Ripple counter
Synchronous counter
Asynchronous counter

Program counter in a digital computer ____________

Counts the number of programs run in the machine

Counts the number of times a subroutine
Counts the number of time the loops are executed
Points the memory address of the current or the next instruction

What is the difference between a 7490 and a 7493?

7490 is a MOD-10, 7493 is a MOD-16

7490 is a MOD-16, 7493 is a MOD-10
7490 is a MOD-12, 7493 is a MOD-16
7490 is a MOD-10, 7493 is a MOD-12

How many different states does a 2-bit asynchronous counter have?

1
4
2
8

A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a

modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________

10 kHz
20 kHz
30 kHz
60 kHz

Which one is a 4-bit binary ripple counter?

IC 7493
IC 7490
IC 7491
IC 7492

IC 7493 consist of ____________

4 S-R flip-flop
4 J-K flip-flop
4 master-slave flip-flop
4 D flip-flop

A reset input is used in IC 7493, why?

For increment of bit by 1

For decrement of bit by 1
For reset the counter
For setting the counter

In a 4-bit binary ripple counter, four master-slave flip-flops are internally connected to provide a
________ bit counter.

Divide-by-2 & divide-by-6

Divide-by-6 & divide-by-8
Divide-by-2 & divide-by-8
Divide-by-4 & divide-by-8

Which of the following is a decade counter?

IC 7493
IC 7490
IC 7491
IC 7492

In a 4-bit decade counter, four master-slave flip-flops are internally connected to provide a ________ bit
counter.

Divide-by-2 & divide-by-6

Divide-by-6 & divide-by-8
Divide-by-2 & divide-by-5
Divide-by-4 & divide-by-8

Reset inputs are used in IC 7490, why?

For increment of bit by 1

For decrement of bit by 1
For reset the counter
For setting the counter

The set inputs are used in a decade counter, why?

To set the counter to 0011

To set the counter to 1000
To set the counter to 1001
To set the counter to 0001

List which pins need to be connected together on a 7493 to make a MOD-12 counter.

12 to 1, 11 to 3, 9 to 2
12 to 1, 11 to 3, 12 to 2
12 to 1, 11 to 3, 8 to 2
12 to 1, 11 to 3, 1 to 2

Explanation: IC-7493 is a MOD-16 counter. So maximum, it can have 16 states. A MOD-12 counter will have
12-states. Thus, it is clear from the diagram shown below: 12 & 1 are clear pins, 11 & 3 are clock pins, 8 & 2
are input for 7493 FF.

Ripple counter IC has _____________

10 pins
11 pins
12 pins
14 pins

Integrated-circuit counter chips are used in numerous applications including ____________

Timing operations, counting operations, sequencing, and frequency multiplication

Timing operations, counting operations, sequencing, and frequency division
Timing operations, decoding operations, sequencing, and frequency multiplication
Data generation, counting operations, sequencing, and frequency multiplication

Explanation: There are no integrated circuit counter chips employed for frequency multiplication. In the rest
of the options, frequency multiplication is mentioned which is not related to counters in anyway. So, they are
not the correct answers. Thus, counters are used for timing operations, counting operations, sequencing and
frequency division.

What is the difference between 7490 and a 7492?

7490 is a MOD-12, 7492 is a MOD-10

7490 is a MOD-12, 7492 is a MOD-16
7490 is a MOD-16, 7492 is a MOD-10
7490 is a MOD-10, 7492 is a MOD-12

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay.
The total propagation delay (tp(tot)) is ________
12 ms
24 ns
48 ns
60 ns

What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each
flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?

15 ns
22 ns
60 ns
88 ns

The main drawback of a ripple counter is that __________

It has a cumulative settling time

It has a distributive settling time
It has a productive settling time
It has an associative settling time
A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec,
the maximum clock frequency that can be used is equal to __________

20 MHz
10 MHz
5 MHz
4 MHz

As the number of flip flops are increased, the total propagation delay of __________

Ripple counter increases but that of synchronous counter remains the same
Both ripple and synchronous counters increase
Both ripple and synchronous counters remain the same
Ripple counter remains the same but that of synchronous counter increases

Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and
fourth stages will __________

Continue to count with correct outputs

Continue to count but have incorrect outputs
Stop counting
Turn into molten silicon

UP-DOWN counter is a combination of ____________

Latches
Flip-flops
UP counter
Up counter & down counter

UP-DOWN counter is also known as ___________

Dual counter
Multi counter
Multimode counter
Two Counter

In an UP-counter, each flip-flop is triggered by ___________

The output of the next flip-flop

The normal output of the preceding flip-flop
The clock pulse of the previous flip-flop
The inverted output of the preceding flip-flop

In DOWN-counter, each flip-flop is triggered by ___________

The output of the next flip-flop

The normal output of the preceding flip-flop
The clock pulse of the previous flip-flop
The inverted output of the preceding flip-flop

Once an up-/down-counter begins its count sequence, it ___________

Starts counting
Can be reversed
Can’t be reversed
Can be altered

In 4-bit up-down counter, how many flip-flops are required?

2
3
4
5

A modulus-10 counter must have ________

10 flip-flops
4 Flip-flops
2 flip-flops
Synchronous clocking

Which is not an example of a truncated modulus?

8
9
11
15

An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be
changed to a down counter by ________

Taking the output on the other side of the flip-flops (instead of Q)

Clocking of each succeeding flip-flop from the other side (instead of Q)
Changing the flip-flops to trailing edge triggering
All of the Mentioned
A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most
significant bit is ________

1.25 kHz
2.50 kHz
160 kHz
320 kHz

Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB changes on 8th
stage; Hence, f = 10/8 = 1.25 kHz.

A register is defined as ___________

The group of latches for storing one bit of information

The group of latches for storing n-bit of information
The group of flip-flops suitable for storing one bit of information
The group of flip-flops suitable for storing binary information

Explanation: A register is defined as the group of flip-flops suitable for storing binary information. Each flip-
flop is a binary cell capable of storing one bit of information. The data in a register can be transferred from
one flip-flop to another.

The register is a type of ___________

Sequential circuit
Combinational circuit
CPU
Latches

How many types of registers are?

2
3
4
5

The main difference between a register and a counter is ___________

A register has no specific sequence of states

A counter has no specific sequence of states
A register has capability to store one bit of information but counter has n-bit
A register counts data

Registers capable of shifting in one direction is ___________

Universal shift register

Unidirectional shift register
Unipolar shift register
Unique shift register

A register that is used to store binary information is called ___________

Data register
Binary register
Shift register
D – Register

A shift register is defined as ___________

The register capable of shifting information to another register

The register capable of shifting information either to the right or to the left
The register capable of shifting information to the right only
The register capable of shifting information to the left only

How many methods of shifting of data are available?

2
3
4
5

In serial shifting method, data shifting occurs ____________

One bit at a time

Simultaneously
Two bit at a time
Four bit at a time

Based on how binary information is entered or shifted out, shift registers are classified into _______
categories.

2
3
4
5

Explanation: The registers in which data can be shifted serially or parallelly are known as shift registers.
Based on how binary information is entered or shifted out, shift registers are classified into 4 categories, viz.,
Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-
Out (PIPO).

The full form of SIPO is ___________

Serial-in Parallel-out
Parallel-in Serial-out
Serial-in Serial-out
Serial-In Peripheral-Out

A shift register that will accept a parallel input or a bidirectional serial load and internal shift features
is called as?

Tristate
End around
Universal
Conversion

How can parallel data be taken out of a shift register simultaneously?

Use the Q output of the first FF

Use the Q output of the last FF
Tie all of the Q outputs together
Use the Q output of each FF

What is meant by the parallel load of a shift register?

All FFs are preset with data

Each FF is loaded with data, one at a time
Parallel shifting of data
All FFs are set with data

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift
register with an initial state 01110. After three clock pulses, the register contains ________

01110
00001
00101
00110

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble
1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)

1100
0011
0000
1111

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to
enter. After four clock pulses, the register contains ________

0000
1111
0111
1000

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________

4 μs
40 μs
400 μs
40 ms

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time
delay (td) of ________

16 us
8 us
4 us
2 us

A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is
waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing
________
1101
0111
0001
1110

To operate correctly, starting a ring shift counter requires __________

Clearing all the flip-flops

Presetting one flip-flop and clearing all others
Clearing one flip-flop and presetting all others
Presetting all the flip-flops

A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for
each clock pulse.

Right, one
Right, two
Left, one
Left, three

How many clock pulses will be required to completely load serially a 5-bit shift register?

2
3
4
5

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time
delay between the serial input and the Q3 output?

1.67 s
26.67 s
26.7 ms
267 ms

What is the difference between a ring shift counter and a Johnson shift counter?

There is no difference
A ring is faster
The feedback is reversed
The Johnson is faster

A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing
________

1110
0111
1000
1001

In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses,
the data outputs are ________

1110
0001
1100
1000

The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift
register with an initial state 11110000. After two clock pulses, the register contains ______________

10111000
10110111
11110000
11111100

By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a ________ and
________ out register.

Parallel-in, serial, parallel

Serial-in, parallel, serial
Series-parallel-in, series, parallel
Bidirectional in, parallel, series

What type of register would have a complete binary number shifted in one bit at a time and have all
the stored bits shifted out one at a time?

Parallel-in Parallel-out
Parallel-in Serial-out
Serial-in Serial-out
Serial-in Parallel-out

In a 4-bit Johnson counter sequence, there are a total of how many states or bit patterns?

1
3
4
8

If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?

1101000000
0011010000
1100000000
0000000000

How much storage capacity does each stage in a shift register represent?

One bit
Two bits
Four bits
Eight bits

Ring shift and Johnson counters are ____________

Synchronous counters
Asynchronous counters
True binary counters
Synchronous and true binary counters
What is the difference between a shift-right register and a shift-left register?

There is no difference
The direction of the shift
Propagation delay
The clock input

What is the function of a buffer circuit?

To provide an output that is inverted from that on the input

To provide an output that is equal to its input
To clean up the input
To clean up the output

Explanation: The function of a buffer circuit is to provide an output that is equal to its input. A transceiver
circuit is a buffer that can operate in both directions right as well as left.

Which is not characteristic of a shift register?

Serial in/parallel in
Serial in/parallel out
Parallel in/serial out
Parallel in/parallel out