PLATFORM-BASED BEHAVIOR-LEVEL AND

SYSTEM-LEVEL SYNTHESIS
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
University of California, Los Angeles
Email: {cong, fanyp, leohgl, wjiang, zhiruz}@cs.ucla.edu

Abstract— With the rapid increase of complexity in System- been widely identified as the next productivity boost for the
on-a-Chip (SoC) design, the electronic design automation (EDA) semiconductor industry. However, despite some recent success
community is moving from RTL (Register Transfer Level) in ESL simulation, the transition to ESL design will not be
synthesis to behavioral-level and system-level synthesis. The
needs of system-level verification and software/hardware co- as well accepted as the transition to RTL without robust and
design also prefer behavior-level executable specifications, such efficient behavior-level and system-level synthesis technolo-
as C or SystemC. In this paper we present the platform-based gies that automatically synthesize high-level functional de-
synthesis system, named xPilot, being developed at UCLA. The scriptions into optimized software/hardware implementations.
first objective of xPilot is to provide novel behavioral synthesis We believe that behavior-level and system-level synthesis and
capability for automatically generating efficient RTL code from
a C or SystemC description for a given system platform and optimizations are becoming imperative steps in EDA design
optimizing the logic, interconnects, performance, and power flows. They provide the following combined advantages:
simultaneously. The second objective of xPilot is to provide a Better complexity management: Design abstraction is one
platform-based system-level synthesis capability, including both of the most effective methods for controlling rising complexity
synthesis for application-specific configurable processors and and improving design productivity. For example, a recent
heterogeneous multi-core systems. Preliminary experiments on
FPGAs demonstrate the efficacy of our approach on a wide range study from NEC [8] shows that the code density (in terms
of applications and its value in exploring various design tradeoffs. of line counts) can be improved by nearly 10X when moved
to the behavior level. In addition, behavior-level and system-
I. M OTIVATION level synthesis have the added value of allowing efficient
The relentless tracking of Moore’s curve by the entire reuse of soft functional/behavioral IPs, which are technology-
semiconductor industry has showcased the exponential scaling independent and can be synthesized for different requirements.
of the transistor feature size by a factor of 0.7 reduction every Shorter verification/simulation cycle: System-level syn-
three years. This leads to exponentially increasing transistor thesis and optimizations allow the designers to start with a
counts and results in an explosive growth in functionality and specification in a high-level programming language (HPL)
the amount of computing power available on a single chip. such as C or SystemC that is directly executable and simulat-
Today it is perfectly feasible to design a System-on-a-Chip able with high speed (up to 1000X faster than RT-level simula-
(SoC) with one billion transistors [7], and it is generally tion according to [8]). More importantly, behavioral synthesis
believed that industry will continue to overcome technical automatically compiles the input descriptions into RTL code
hurdles to sustain this trend for another decade. However, through a series of formal constructive transformations. This
the cost of developing these chips and providing production avoids the slow and error-prone manual process and simplifies
facilities is also growing at a very fast pace. For instance, the design verification and debugging effort.
the total development cost of a single complex, high-density Rapid system exploration: With the coexistence of micro-
SoC at today’s 90-nm technology can easily be in the $20 processors, DSPs, memories and custom logic on a single
to $30 million range. The ITRS 2005 edition [7] has also chip, more software elements are involved in the process of
emphasized that the cost of design remains the greatest threat designing a modern embedded system. One of the fundamental
to continuation of the semiconductor roadmap. challenges of system-level design is the hardware/software
Unfortunately, the progress of design technologies lags partitioning, a task that is too complex to be feasible at the RT
behind that of process manufacturing technologies. The con- level. HPL-based design methodologies (especially C-based
stantly improving CAD tools can help to mitigate the problem designs) offer a promising solution to this problem. With
by delivering faster simulation, higher capacity formal ver- the aid of behavior-level synthesis, the software programming
ification, and better logic synthesis coupled with place-and- languages can also be used to specify functionality in hard-
route. However, these improvements fail to close the design ware. In this flow, designers can quickly experiment with
productivity gap, i.e., the number of available transistors grows different hardware/software boundaries by co-simulating the
faster than the ability to meaningfully design them. HPL descriptions and the automatically synthesized HDLs.
It is commonly acknowledged that the ultimate solution Higher quality of results: VLSI designs in current semi-
is to move to the next level of abstraction beyond RTL, conductor technologies are limited by interconnect in both
and Electronic system-level (ESL) design automation has delay and power. However, since the interconnects are deter-
 Platform Description &
SystemC/C
Constraints each process uses a control data flow graph (CDFG) to cap-
ture its behavior. Each process interacts with other processes
xPilot xPilot front end through ports and channels. Each channel implements one or
Profiling more interfaces to capture certain communication protocols.
SSDM
Analysis
Altogether, an SSDM defines a process network to model
(System Synthesis the concurrent behavior of a complex system. On top of this
Data Model) Mapping powerful data model, various analysis, simulation and profiling
passes can be performed.
Processor &
Architecture Interface Behavioral We currently rely on the designers to manually partition
Synthesis Synthesis Synthesis
the application into software and hardware based on the
Processor Cores Drivers + Glue Logic
performance analysis. Once the hardware/software partitioning
+ Executables Custom Logic
is available, we invoke the xPilot behavioral synthesis engine
SoC
to compile the hardware portion of the design to the custom
logics. Specifically, xPilot performs platform-based synthesis
Fig. 1. xPilot system-level synthesis framework. and optimizations during scheduling and resource binding;
these construct an optimized state transition diagram (STG)
and an associated datapath model. At the back end, xPilot
mined by downstream physical design tools, it is very difficult generates RT-level VHDL together with the associated con-
for designers to make accurate estimation at the RT level. To straint files (e.g., multicycle path constraints, physical location
achieve timing and power closure, designers have to adjust constraints, etc.) to leverage the existing logic synthesis and
the initial RTL in an ad hoc manner and iterate over the time- physical design toolset. Additionally, xPilot also generates
consuming synthesis and layout process. We believe that by RT-level SystemC code for fast co-simulation with other
integrating automatic high-level optimizations together with software/hardware modules specified in SystemC.
physical planning, we can optimize the logic and interconnects Since the original design specification is written in a C-
simultaneously and achieve higher quality of results (QoR). based language, it is relatively straightforward to generate the
In this paper we present the xPilot synthesis system being software code for embedded processors. During the software
developed at UCLA. The goal of xPilot is to provide novel code generation step, we also generate the application-specific
platform-based synthesis technologies to simultaneously opti- instruction set for the extensible microprocessors. A pattern
mize the logic, interconnects, performance, and power (which generation, selection, and covering algorithm has been devel-
becomes much more difficult for human designers), so that we oped [3] to automatically identify and generate the custom in-
can improve both design productivity and quality of results. structions. We are also developing an microprocessor-network
The reminder of this paper is organized as follows: Sec- synthesis and mapping algorithm for homogeneous and/or
tion II presents an overview of the xPilot infrastructure and the heterogeneous multiprocessor systems to exploit task-level
main features of current xPilot implementation. Section III and parallelism and further speed up the software implementation.
Section IV briefly discuss the system front end and highlight In order to integrate the microprocessors and custom logics
the behavioral synthesis engine, respectively. The preliminary together, an interface synthesis module is being developed to
experimental results are reported in Section V. generate the software drivers and glue logics.

II. X P ILOT S YSTEM OVERVIEW III. X P ILOT F RONT E ND

The overall design flow of the xPilot system is shown in xPilot accepts synthesizable C or SystemC as input. C
Figure 1. xPilot accepts synthesizable C or SystemC as input. language is effective for describing sequential behavior within
The behavioral description is first parsed and optimized by one single process of the entire system. SystemC, on the
our front end complier. Currently, we use the UIUC LLVM other hand, provides the capability to capture many hardware-
compiler [6] to parse in C/SystemC code. LLVM consists of specific features such as process-level parallelism and the
a GCC-based C/C++ front end, a virtual instruction set, a communication/synchronization among concurrent modules.
link-time optimization framework, and various back ends for Our front end compiler translates design descriptions written
common target machines. We leverage the GCC-based com- in C or SystemC into SSDM—the internal data model of
piler front end to obtain an LLVM intermediate representation xPilot. Currently, we use the UIUC LLVM compiler [6] to
(IR). On top of this IR, we first recover certain high-level pro- parse in C/SystemC code. On top of the LLVM intermediate
gramming constructs from the low-level virtual instruction set. representation, we first recover certain high-level programming
We then perform elaboration to extract the processes, ports, constructs from the low-level virtual instruction set, then
channels and their interconnection topologies, and construct perform elaboration to extract the processes, ports, channels
our system-level synthesis data model (SSDM)—the internal and their interconnection topologies, and construct our SSDM
data model of xPilot. accordingly based on this information.
The basic building blocks in SSDM are processes and Several analysis and optimization passes will be performed
channels. A process describes the behavior of one module, and during this stage, including traditional compilation techniques
such as dead code elimination, and hardware-specific passes when compared to the scheduler of SPARK [5], a state-of-
such as bitwidth analysis. We observe that the bitwidth the-art academic high-level synthesis system. The technical
analysis can be very beneficial for many designs, since the details of our scheduling algorithm are discussed in [4].
operations and variables can use the function units and the
registers with the minimal widths. B. Resource Binding
Another major task at the front end is platform characteri- In the resource binding stage, we focus on the optimization
zation. Specifically, we characterize the delay, area, and power of interconnects and multiplexors to improve the quality of
for each type of available resource (e.g., functional units, results using a distributed register-file microarchitecture.
memories, steering logic, etc.) under different input/output At the RT level, large number of discrete registers may
operand count and bitwidth configurations. We also capture result in wide multiplexors and a complicated interconnect
the layout information of the target platform to facilitate structure. To address this problem, register files can be used,
our physical-aware synthesis. The heterogeneous resources which replace the multiplexors with the dedicated decoding
distribution map and the interconnect delay/power lookup logic. However, due to the limited number of read and write
tables are also collected. ports, a centralized register file may not provide sufficient
bandwidth for the applications with multiple concurrent data
IV. B EHAVIORAL S YNTHESIS E NGINE reads and writes. Distributed register files are required for such
applications. The usage of distributed register files is further
In this section we will highlight the xPilot behavioral
encouraged for modern FPGA and Structured ASIC platforms,
synthesis engine, including scheduling and resource binding.
which have rich on-chip distributed memory IP blocks.
We propose a distributed register-file microarchitecture
A. Scheduling
(DRFM), which consists of multiple islands. Each island
Scheduling, which exploits parallelism in the behavior-level contains a local register file, a functional unit pool, and data-
design and determines the time at which different computa- routing logic. In DRFM, each register file allows a variable
tions and communications are performed, is recognized as one number of read ports but only a fixed number (typically
of the most important problems in behavioral synthesis. How- one) of write ports. The DRFM-based resource binding tries
ever, the existing scheduling techniques either have limited to minimize the inter-island connections. This will simplify
efficiency in a specific class of application or lack general the data-routing logic in each island and reduce the overall
support of various design constraints. To address the above complexity of the resulting datapath. Our heuristic approach
deficiencies, We have developed a new scheduling algorithm, uses a weighted bipartite matching algorithm to gradually bind
which consists of three main steps. operation set to the target DRFM. Each binding step handles
First, we convert a rich set of scheduling constraints into a a set of compatible operations and binds them onto different
system of difference constraints. In particular, for dependency islands, with the objective to minimize the amount of newly
constraints, we can exactly model data dependencies and introduced inter-island connections.
control dependencies. For timing constraints, we can precisely Our DRFM study on the Virtex-II FPGAs shows more than
transform the frequency constraint, relative I/O timing con- 2X logic area reduction when compared to the traditional
straints, and latency constraints. Since resource-constrained discrete-register-based approach [5], with a faster clock period
scheduling problem is intractable in general, we heuristically (27% improvement on average). The technical details of our
convert the resource constraints into difference constraints. Us- resource binding algorithm are available in [2].
ing this formulation, the consistency of the constraint system
can be checked efficiently by solving a single-source shortest V. E XPERIMENTAL RESULTS
path problem. The xPilot system is implemented in a C++/Linux environ-
Second, we express the scheduling objective as a linear ment. In this paper we report the results of targeting the field-
function so that the global optimization can be performed by programmable SoC platforms (e.g., Altera and Xilinx FPGAs).
linear programming. In addition, the matrix formed by the con-
straint equations has a special property that guarantees integral A. Test Examples
solution. Under this unified mathematical framework, we can We tested xPilot hardware synthesis through several real-
apply a variety of powerful optimizations by reformulating the life behavioral designs from different application domains. As
objective function. Specifically, we can generalize As-Soon- listed in Table I, PR and MCM are two DSP kernels with pure
As-Possible and As-Late-As-Possible schedules, and optimize additions/subtractions and multiplications. CACHE is a cache
the worst-case longest-path latency, the expected average-case controller implementation which is a pure control-intensive
latency, and the overall slack distribution. design with cycle-accurate I/O operations. MOT ION performs
Third, after we obtain the integer results by the LP solver, the motion compensation algorithm for the MPEG-1 decoder.
we can directly translate this solution into an actual schedule This design has multiple branches and a modest amount of
in STG representation. computations. IDCT implements the inverse discrete cosine
Experiments on a set of real-life behavioral designs show transform algorithm used in the JPEG standard, and DW T
that our scheduler achieves 15% shorter latency on average implements the discrete wavelet transform algorithm adopted
in the JPEG2000 standard. These two benchmarks contain on the RTL VHDL generated by xPilot using the same input
a large amount of computations and memory accesses. The stimulus takes about 2300 seconds.
EDGELOOP design is extracted from the H.264 decoder. It E. Advantage of xPilot Synthesis: Faster Design Exploration
features a mix of computation, control branches, loops and As one case study on system-level design, we have imple-
memory accesses. mented a Motion-JPEG encoder on a Xilinx XUP Virtex-II Pro
development board. The original C design is obtained from the
TABLE I
UC Berkeley Metropolis group [1].
C VS . RTL VHDL CODE SIZES
In this experiment we evaluated the performance of two
Design C lines VHDL lines LE Fmax(MHz) alternative design implementations. The first model uses five
PR 90 600 1349 178.7 MicroBlaze soft-core processors to implement the five major
MCM 161 1260 2402 152.6 modules of Motion-JPEG encoder, i.e., preprocessing, DCT,
CACHE 295 1277 371 161.6
MOTION 130 1200 888 161.2 quantization, Huffman encoding, and table modification. These
IDCT 236 7388 9351 162.9 MicroBlazes communicate through FIFOs and execute on the
DWT 180 1371 1862 147.3 incoming image blocks in a pipelined fashion. In the second
EDGELOOP 329 7296 7440 100.1
model, we use xPilot to synthesize the software DCT in C into
hardware VHDLs and replace the corresponding MicroBlaze
with our own custom hardware DCT block. After the hardware
B. Advantage of xPilot Synthesis: Code Size Reduction
synthesis process, which only takes a few seconds, we are
In Table I the second and third columns report the compar- able to obtain a 38% faster implementation using the second
ison on code sizes before and after behavioral synthesis for model. In fact, the hardware DCT module itself is at least 6X
the seven test cases. In this experiment we target the Altera faster than the software counterpart, but the overall speedup
Stratix FPGAs using Quartus II v4.2 as the downstream RTL is limited by the I/O bandwidth.
synthesis and physical design tool.
On average, the code size of the synthesized RTL designs F. Advantage of xPilot Synthesis: Better QoR
is about one order of magnitude larger than the corresponding We made comparisons with SPARK [5] on our benchmark
C code. If we assume design complexity is proportional to the suite targeting Xilinx Virtex-II FPGAs. After scheduling and
code line count, we can expect more than a 10× reduction resource binding, xPilot achieves nearly 40% better perfor-
in design effort by rising to the behavioral level and applying mance (in final latency) with 2× area reduction on average.
our behavioral synthesis tool. The full consideration and detailed characterization of the tar-
get platform partly contribute to the significant improvement.
C. Advantage of xPilot Synthesis: Design Tradeoffs
ACKNOWLEDGMENTS
TABLE II This research is partially supported by the Semiconductor Research
D ESIGN TRADEOFF IN X P ILOT Corporation, the Gigascale Silicon Research Center, the National
Science Foundation, and grants from Altera Corporation, Magma
Target State Fmax Cycle Latency LE Design Automation, Inc., and Xilinx, Inc. under the California
Cycle time MHz (ns)
MICRO program.
9ns 34 123.56 4830 39.1 1777
7ns 36 147.28 5211 35.4 1862 R EFERENCES
5.5ns 51 183.62 6926 37.8 1926
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