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Assignment 8 System Design Through VERILOG - Unit 9 - Week 8 - Case Studies

The document is an assessment submitted for an online NPTEL course on system design through Verilog. It consists of 8 multiple choice questions testing concepts about Baugh-Wooley multipliers, 2's complement representations, fixed point numbers, and Verilog primitives. The assessment is due on September 21, 2023 at 11:59pm IST.

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309 views3 pages

Assignment 8 System Design Through VERILOG - Unit 9 - Week 8 - Case Studies

The document is an assessment submitted for an online NPTEL course on system design through Verilog. It consists of 8 multiple choice questions testing concepts about Baugh-Wooley multipliers, 2's complement representations, fixed point numbers, and Verilog primitives. The assessment is due on September 21, 2023 at 11:59pm IST.

Uploaded by

vijaymtech
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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System Design Through VERILOG (course)


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exam
(https://examform.nptel.ac.in/2022_04/exam_form/dashboard)
Thank you for taking the Assignment 8.

Course outline Assignment 8


Your last recorded submission was on 2022-09-21, 12:18 IST Due date: 2022-09-21, 23:59 IST.
How does an NPTEL
1) Which of the following
statement is TRUE with respect to Baugh-Wooley Multiplier (BWM) 1 point
online course work? ()

BWM implementation
requires minimum 7 half adders and 7 full adders  
Week 1: Introduction to

BWM implementation requires minimum 7 half adders and 8 full adders
Verilog ()


BWM implementation
requires minimum 8 half adders and 7 full adders 
Week 2 : Gate level
BWM implementation
requires minimum 8 half adders and 8 full adders
modeling-I ()
2) If A=2’d99; B=2’d88; and C=2’d77;
before the execution of $display
keyword. After the execution of $display
(“%b  %o  %h”, A, B, C); 1 point
the values of A, B, and C
displayed are respectively
Week 3: Gate level
modeling-II ()

1100011, 130, 4d

110011, 120, 3c
Week 4: Switch level
modeling ()
110001,110,3e

1110011,131,3f
Week 5: Dataflow and
3) The 8-bit signed 2’s complement
representation of -16 is 1 point
behavioral modeling ()

00001111
Week 6: Behavioral

11100111
modeling of sequential
circuits ()
11101111

11110000
Assessment
Weeksubmitted.
7: Test benches ()
X 4) The range of 8-bit fixed point
normalized signed 2’s complement numbers is 1 point
Week 8: Case studies ()

-1 to +127/128
Lec 25: FIR filter
-1 to +128/127
implementation (unit?

-1 to +255/256
unit=61&lesson=62)

-1 to +256/255
Lec 26: Baugh-Wooley
signed multiplier 5) If 4-bit fixed point normalized
signed 2’s complement representation of A is a3.a2a1a0 , then A 2-2 would be 1 point
architecture (unit?
unit=61&lesson=63)
 a3.a3a3a2     

 a3.a3a2a1
Lec 27: IIR filter
implementation (unit?
 a3.a3a3a0
unit=61&lesson=64)
 a3.a3a3a3
Quiz: Assignment 8 6) If 4-bit fixed point normalized
signed 2’s complement representation of A is a3 a2 a1 a0  , then a¯3 . a¯2 a¯1 a¯0 + 0.001  would be 1 point
(assessment?name=92)

 -A 20  
Week 8: Feedback form
(unit?unit=61&lesson=65)
-A 2-1

-A 2-2
Download ()

-A 2-3

Live Session () 7) Which of the following


statement(s) is FALSE? 1 point

Problem Solving
Braun multiplier is unsigned
multiplier
Session ()
Baugh-Wooley multiplier is signed multiplier

The conventional parallel multiplier handles sign bit in an
efficient manner
Books ()

All of the above

Transcripts () 8) The Verilog primitive $time displays 1 point

 
Current simulation time

One-time value of variables or
strings

Variables whenever a value
changes during a simulation run

None of the above

You may submit any number of times before the due date. The final submission will be considered for grading.
Submit Answers
Assessment submitted.
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