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System Design Through VERILOG (course)

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Assignment 7
(https://examform.nptel.ac.in/2022_04/exam_form/dashboard)

Assignment not submitted Due date: 2022-09-14, 23:59 IST.

For Q. 1-4. Consider the following Verilog modules for 2 × 1 multiplexer and its corresponding test bench:
Course outline

module   mux_2 × 1 (y,a,b,s);

How does an NPTEL

output y;
online course work? ()
input  a,b,s;

assign  y = (s)?b:a;
Week 1: Introduction to
endmodule

Verilog ()

module   mux_2 × 1_tb;

Week 2 : Gate level
reg  A,B,S;
modeling-I ()

wire  Y;

parameter  stop_time=50;
Week 3: Gate level

# Instantiate circuit to be tested #

modeling-II ()

mux_2 × 1 M1 (.y(Y),.a(A),.b(B),.s(S));

initial #stop_time $finish;
Week 4: Switch level

initial begin
modeling ()

S=1; A=0; B=1;

#10 A=1; B=0;

Week 5: Dataflow and

#10 S=0;
behavioral modeling ()

 #10 A=0; B=1;

Week 6: Behavioral end
modeling of sequential

endmodule
circuits ()
1) At t = 0, the values of S, A, B,
and Y are respectively 1 point
Lec 18: Verilog modeling of
counters (unit?
0,0,1 and 0
unit=48&lesson=49)
0,0,1 and 1
Lec 19: Verilog modeling of
1,0,1 and 0
sequence detector (unit?

1,0,1 and 1
unit=48&lesson=50)
2) At t = 5, the values of S, A, B, and Y are
respectively 1 point
Lec 20: Verilog modeling
FSMs and shift registers

0,1,0 and 0
(unit?unit=48&lesson=51)

1,1,0 and 1
Quiz: Assignment 6

0,0,1 and 1
(assessment?name=90)

1,0,1 and 1
Week 6: Feedback form
(unit?unit=48&lesson=52) 3) At t = 15, the values of S, A, B, and Y are respectively 1 point

Solution: Assignment 6
0,1,0 and 0
(unit?unit=48&lesson=53)

1,1,0 and 0
Week 7: Test benches ()
0,0,1 and 1

1,0,1 and 0
Lec 21: Combinational
circuit examples (unit? 4) At t = 25, the values of S, A, B and Y are respectively 1 point
unit=54&lesson=55)

0,0,1 and 1
Lec 22: Sequential circuit
examples (unit?

1,0,1 and 0
unit=54&lesson=56)
0,1,0 and 1

Lec 23: Arithmetic and

1,1,0 and 1
Logic Unit (ALU) (unit?
For Q. 5-8. Consider the following Verilog
modules for D flip-flop and its corresponding test bench:
unit=54&lesson=57)

Lec 24: Static RAM and module   DFF (Q,

Qbar, D,Clk, Reset);

Braun Multiplier (unit? output

reg Q, Qbar;
unit=54&lesson=58)

input  D,Clk,Reset;

Quiz: Assignment 7
always
@(negedge  Clk)

(assessment?name=91) if
(Reset)

Q
= 1’b0;
Week 7: Feedback form

else
(unit?unit=54&lesson=59)

Q
<= D;

 Solution: Assignment 7 endmodule

(unit?unit=54&lesson=60)

`timescale 1ns /
1ps
Week 8: Case studies ()

module DFF_tb;

// Inputs
Download () reg D;

reg Clk;

Live Session () reg Reset;

// Outputs

Problem Solving wire Q;

Session ()

wire Qbar;

// Instantiate
the Design Under Test (DUT)
Transcripts ()

DFF dut (.Q(Q),.Qbar(Qbar),.D(D),.Clk(Clk),.Reset(Reset));

initial begin
 

// Initialize
Inputs
Clk = 1'b0;

forever #10
Clk = ~Clk; 
end

initial begin

D=0; Reset = 1;

#13 Reset=0;

#18 D=1;

#37 Reset=1;

end

endmodule

5) The values of Reset and Q at t = 18ns are respectively  1 point

0,0

0,1

1,0

1,1

6) The values of Reset and Q at t = 35ns are respectively 1 point

0,0

0,1

1,0

1,1

7) The values of Reset and Q at t = 60ns are respectively 1 point


0,0

0,1

1,0

1,1

8) The values of Reset and Q at t = 68ns are respectively 1 point

0,0

0,1

1,0

1,1

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