DIGITAL ELECTRONICS LAB

LAB MANUAL

IV SEMESTER
 DIGITAL ELECTRONICS LAB ( )

LIST OF EXPERIMENTS:-

1. Study of TTL gates – AND; OR; NOT; NAND; NOR; EX-OR; EX-NOR
2. Verify the NAND and NOR gates as universal logic gates.
3. Design and verification of the truth tables of Half and Full adder circuits.
4. Design and verification of the truth tables of Half and Full subtractor circuits.
5. To verify the truth tables of S-R; J-K; T and D type flip flops
6. Design, and Verify the 4-Bit Asynchronous Counter.
7.To verify the operation of bi-directional shift register
8. Operate the counters 7490, 7493
9. Implementation of 4x1 multiplexer using Logic Gates.
10.Verification of the truth table of the De-Multiplexer 74154.

.
 INDEX

Sr. No. Exp. No. Experiments Pages Date Remark

1 1 Study of TTL gates – AND; OR;
NOT; NAND; NOR; EX-OR;
EX-NOR

2 2
Verify the NAND and NOR gates
as universal logic gates.

3 3 Design and verification of the

truth tables of Half and Full
adder circuits.

4 4 Design and verification of the

truth tables of Half and Full
subtractor circuits.
5 5
To verify the truth tables of S-R;
J-K; T and D type flip flops

6 6 . Design, and Verify the 4-Bit

Asynchronous Counter
7 7
To verify the operation of bi-
directional shift register
8 8 Operate the counters 7490,
7493

9 9 Implementation of 4x1
multiplexer using Logic
Gates.
10 10
Verification of the truth table of
the De-Multiplexer 74154.
 EXPERIMENT NO: 1
AIM: - Study of TTL gates – AND; OR; NOT; NAND; NOR; EX-OR; EX-NOR
APPARATUS REQUIRED: Power Supply, Digital Trainer Kit., Connecting Leads, IC’s (7400,
7402, 7404, 7408, 7432, and 7486)

BRIEF THEORY:

AND Gate: The AND operation is defined as the output as (1) one if and only if all the inputs are (1)
one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals &Y is the Output terminal.
Y = A.B
OR Gate: The OR operation is defined as the output as (1) one if one or more than 0 inputs are (1) one.
7432 is the two Input OR gate IC. A&B are the input terminals & Y is the Output terminal.
Y=A+B
NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output (Y). IC No.
is 7404. Its logical equation is,
Y = A NOT B, Y = A’
NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known as NAND
operation. If all inputs are 1 then output produced is 0. NAND gate is inverted AND gate.
Y = (A. B)’
NOR GATE: The NOR gate has two or more input signals but only one output signal. IC 7402 is two
I/P IC. The NOT- OR operation is known as NOR operation. If all the inputs are 0 then the O/P is 1.
NOR gate is inverted OR gate.

Y = (A+B)’
EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output. 7486 is two
inputs IC. EX-OR gate is not a basic operation & can be performed using basic gates.
Y=A B
LOGIC SYMBOL:
. Logic Symbol of Gates
PIN CONFIGURATION:
7400(NAND) 7402(NOR)

7404(NOT) 7408(AND)

7486 (EX-OR) 7432 (OR)

 PROCEDURE:
(a) Fix the IC’s on breadboard & give the supply.
(b) Connect the +ve terminal of supply to pin 14 & -ve to pin 7.
(c) Give input at pin 1, 2 & take output from pin 3. It is same for all except
NOT & NOR IC.
(d) For NOR, pin 1 is output & pin 2&3 are inputs.
(e) For NOT, pin 1 is input & p in 2 is output.
(f) Note the values of output for different combination of inputs
& draw the TRUTH TABLE.

OBSERVATIO N TABLE:

INP UTS OUTP UTS

A’ A+B (A+B)’ (A *B) (A*B )’ (A B)
A B NOT OR NOR A ND NAND Ex-OR
0 0 1 0 1 0 1 0
0 1 1 1 0 0 1 1
1 0 0 1 0 0 1 1
1 1 0 1 0 1 0 0

RESULT: We have learnt all the gates ICs according to the IC p in diagram.

PRECAUTIONS:

1. Make the connection s according to the IC pin diagram.

2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Define gates ?

Ans. Gates are the digital circuits, which perform a specific type of logical operation.

Define IC?
Ans. IC means integrated circuit. It is the integration of no. of components on a common
substrate.
Give example of Demorgan’s theorem.
Ans. (AB)’=A’+B’
(A+B)’=A’.B’
(A+A) A =?
Ans. A.
Q5. Define Universal gates.
Ans. Universal gates are those gates by using which we can design any type of logical expression.
Q6.Write the logical equation for AND gate.
Ans. Y=A.B
Q7 How many no. of input variables can a NOT Gate have?
Ans. One
Q8.Under what conditions the output of a two input AND gate is one?
Ans. Both the inputs are one.
Q9.1+0 =?
Ans. 1
Q10.When will the output of a NAND Gate be 0?
Ans. When all the inputs are 1.
 EXPERIMENT NO: 2
Aim:- Verify the NAND and NOR gates as universal logic gates

To implement the logic functions i.e. AND, OR, NOT, Ex-OR, Ex- NOR and a logical expression
with the help of NAND and NOR universal gates respectively

Theory:

Introduction:

Logic gates are electronic circuits which perform logical functions on one or more inputs to
produce one output. There are seven logic gates. When all the input combinations of a logic gate
are written in a series and their corresponding outputs written along them, then this input/
output combination is called Truth Table.

1) Nand gate as Universal gate:

NAND gate is actually a combination of two logic gates i.e. AND gate followed by NOT
gate. So its output is complement of the output of an AND gate. This gate can have minimum two
inputs. By using only NAND gates, we can realize all logic functions: AND, OR, NOT, Ex-OR,
Ex-NOR, NOR. So this gate is also called as universal gate.

NAND gates as OR gate

From DeMorgan’s theorems:
(A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.

Figure-1:NAND gates as OR gate

 Figure-2:Truth table of OR

NAND gates as AND gate:

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted,
overall output will be that of an AND gate.

Y = ((A.B)’)’
Y = (A.B)

Figure-3:NAND gates as AND gate

Figure-4:Truth table of AND

NAND gates as Ex-OR gate:

The output of a two input Ex-OR gate is shown by: Y = A’B + AB’. This can be achieved
with the logic diagram shown in the left side.

Figure-5:NAND gate as Ex-OR gate

 Figure-6:Truth table of Ex-OR

NAND gates as Ex-NOR gate:

Ex-NOR gate is actually Ex-OR gate followed by NOT gate. So give the output of Ex-OR
gate to a NOT gate, overall output is that of an Ex-NOR gate.

Y = AB+ A’B’

Figure-7:NAND gates as Ex-NOR gate

Figure-8:Truth table of Ex-NOR

Implementing the simplified function with NAND gates only

We can now start constructing the circuit. First note that the entire expression is inverted and we
have three terms ANDed. This means that we must use a 3-input NAND gate. Each of the three
terms is, itself, a NAND expression. Finally, negated single terms can be generates with a 2-input
NAND gate acting as an inverted. Figure 8 illustrates a circuit using NAND gates only.

F=((C'.B.A)'(D'.C.A)'(C.B'.A)')'
 Figure-9:Implementing the simplified function with NAND gates only

2) Nor gate as Universal Gate

NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. So its
output is complement of the output of an OR gate.This gate can have minimum two inputs, output
is always one. By using only NOR gates, we can realize all logic functions: AND, OR, NOT, Ex-
OR, Ex-NOR, NAND. So this gate is also called universal gate.

NOR gates as OR gate

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall
output will be that of an OR gate.

Y = ((A+B)’)’
Y = (A+B)

Figure-10:NOR gates as OR gate

Figure-11:Truth table of OR
NOR gates as AND gate:
From DeMorgan’s theorems:
(A+B)’ = A’B’
(A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.
 Figure-12:NOR gates as AND gate

Figure-13:Truth table of AND

2.4)NOR gates as Ex-OR gate:

Ex-OR gate is actually Ex-NOR gate followed by NOT gate. So give the output of Ex-NOR
gate to a NOT gate, overall output is that of an Ex-OR gate.
Y = A’B+ AB’

Figure-14:NOR gates as Ex-OR gate

Figure-15:Truth table of Ex-OR

2.3)NOR gates as Ex-NOR gate:

The output of a two input Ex-NOR gate is shown by: Y = AB + A’B’. This can be achieved
with the logic diagram shown in the left side.
 Figure-16:NOR gates as Ex-NOR gate

Figure-17:Truth table of Ex-NOR

2.5)Constructing a circuit with NOR gates only:

Designing a circuit with NOR gates only uses the same basic techniques as designing a
circuit with NAND gates; that is, the application of deMorgan’s theorem. The only difference
between NOR gate design and NAND gate design is that the former must eliminate product
terms and the later must eliminate sum
terms.

F=(((C.B'.A)+(D.C'.A)+(C.B'.A))')'

Figure-18:Implementing the simplified function with NOR gates only

 EXPERIMENT NO: 3
Aim:- Design and verification of the truth tables of Half and Full adder circuits.

To verify the truth table of half adder and full adder by using XOR and NAND gates respectively
and analyse the working of half adder and full adder circuit with the help of LEDs in simulator 1
and verify the truth table only of half adder and full adder in simulator 2.

Theory

Introduction

Adders are digital circuits that carry out addition of numbers. Adders are a key component of
arithmetic logic unit. Adders can be constructed for most of the numerical representations
like Binary Coded Decimal (BCD), Excess – 3, Gray code, Binary etc. out of these, binary
addition is the most frequently performed task by most common adders. Apart from addition,
adders are also used in certain digital applications like table index calculation, address decoding
etc.

Binary addition is similar to that of decimal addition. Some basic binary additions are shown
below.

Figure 1. Schematic representation of half adder

1) Half Adder
Half adder is a combinational circuit that performs simple addition of two binary numbers. If we
assume A and B as the two bits whose addition is to be performed,the block diagram and a truth
table for half adder with A, B as inputs and Sum, Carry as outputs can be tabulated as follows.
`

Figure 2. Block diagram and truth table of half adder

The sum output of the binary addition carried out above is similar to that of an Ex-OR operation
while the carry output is similar to that of an AND operation. The same can be verified with
help of Karnaugh Map. The truth table and K
Map simplification and logic diagram for sum output is shown below.

Figure 3. Truth table, K Map simplification and Logic diagram for sum output of half adder

Sum = A B' + A' B

The truth table and K Map simplification and logic diagram for carry is shown below.

Figure 4. Truth table, K Map simplification and Logic diagram for sum output of half adder

Carry = AB
If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex
– OR of A and B and logic function to calculate carry C is AND of A and B. Combining
these two, the logical circuit to implement the combinational circuit of half adder is shown below.

Figure 5. Half Adder Logic Diagram

As we know that NAND and NOR are called universal gates as any logic system can be
implemented using these two, the half adder circuit can also be implemented using them. We
know that a half adder circuit has one Ex – OR gate and one AND gate.
Half Adder using NAND gates:
Five NAND gates are required in order to design a half adder. The circuit to realize half adder
using NAND gates is shown below.

Figure 6. Realization of half adder using NAND gates

Half Adder using NOR gates

Five NOR gates are required in order to design a half adder. The circuit to realize half adder using
NOR gates is shown below.

Figure 7. Realization of half adder using NOR Gates

2) Full Adder
Full adder is a digital circuit used to calculate the sum of three binary bits. Full adders are
complex and difficult to implement when compared to half adders. Two of the three bits are same
as before which are A, the augend bit and B, the addend bit. The additional third bit is carry bit
from the previous stage and is called 'Carry' – in generally represented by CIN. It calculates the
sum of three bits along with the carry. The output carry is called Carry – out and is represented
by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S, Carry OUT as outputs is
shown below.
 Figure 8. Full Adder Block Diagram and Truth Table

Figure 9. Full Adder Logic Diagram

Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be
derived using K – Map.

Figure 10. The K-Map simplified equation for sum is S = A'B'Cin + A'BCin' + ABCin

Figure 11. The K-Map simplified equation for COUT is COUT = AB + ACIN + BCIN
In order to implement a combinational circuit for full adder, it is clear from the equations
derived above, that we need four 3-input AND gates and one 4-input OR gates for Sum and three
2-input AND gates and one 3-input OR gate for Carry – out.

Full Adder using NAND gates:

As mentioned earlier, a NAND gate is one of the universal gates and can be used to implement
any logic design. The circuit of full adder using only NAND gates is shown below.

Figure 12. Full Adder using NAND gates

Full Adder using NOR gates:

As mentioned earlier, a NOR gate is one of the universal gates and can be used to implement any
logic design. The circuit of full adder using only NOR gates is shown below.

Figure 13. Full Adder using NOR

 EXPERIMENT NO : 4
Aim: Design and verification of the truth tables of Half and Full subtractor circuits.

To verify the truth table of half subtractor by using the ICs of XOR, NOT and AND gates and of
full subtractor by using the ICs of XOR, AND, NOT and OR gates respectively and
analyse the working of half subtractor and full subtractor circuit with the help of LEDs in
simulator 1 and verify the truth table only of half subtractor and full subtractor in simulator 2.

Theory

Introduction

Subtractor circuits take two binary numbers as input and subtract one binary number input
from the other binary number input. Similar to adders, it gives out two outputs, difference and
borrow (carry-in the case of Adder). There are two types of subtractors.
1) Half Subtractor
2) Full Subtractor

1) Half Subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs Difference and Borrow.
The logic symbol and truth table are shown below.

Figure-1:Logic Symbol of Half subtractor

Figure-2:Truth Table of Half subtractor

 Figure-3:Circuit Diagram of Half subtractor

From the above truth table we can find the boolean expression.

Difference = A ⊕
B Borrow = A' B
From the equation we can draw the half-subtractor circuit as shown in the figure 3.

2) Full Subtractor

A full subtractor is a combinational circuit that performs subtraction involving three bits, namely
A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B
(subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout
(borrow out). The logic symbol and truth table are shown below.

Figure-4:Logic Symbol of Full subtractor

Figure-5:Truth Table of Full subtractor

From the above truth table we can find the boolean expression.

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin
From the equation we can draw the Full-subtractor circuit as shown in the figure 6.

Figure-6:Circuit Diagram of Full subtractor

 EXPERIMENT NO: 5
Aim: To verify the truth tables of S-R; J-K; T and D type flip flops

APPARATUS REQUIRED: IC’S 7400, 7402 & 7476 Digital Trainer & Connecting leads.

BRIEF THEORY:

• RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When I/Ps R = 0 and S
= 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the flip-flop is switches to the stable
state where O/P is 1 i.e. SET. The I/P condition
is R = 1 and S = 0 the flip-flop is switched to the stable state where O/P is 0 i.e. RESET. The
I/P condition is R = 1 and S = 1 the flip-flop is switched to the stable state where O/P is
forbidden.

• JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal

element to use. The variable J and K are called control I/Ps because they determine what the
flip- flop does when a positive edge arrives. When J and K are both 0s, both AND gates are
disabled and Q retains its last value.

• D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q output
until clock pulses occur. When the clock is low, both AND gates are disabled D can change
value without affecting the value of Q. On the other hand, when the clock is high, both
AND gates are enabled. In this case, Q is forced to equal the value of D. When the clock
again goes low, Q retains or stores the last value of D. a D flip flop is a bistable circuit
whose D input is transferred to the output after a clock pulse is received.

• T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock

edge, giving an output which is half the frequency of the signal to the T input. It is useful
for constructing binary counters, frequency dividers, and general binary addition devices. It
can be made from a J-K flip-flop by tying both of its inputs high.

CIRCUIT DIAGRAM:
SR Flip Flop

D Flip Flop
 JK Flip Flop

T Flip Flop
PROCEDURE:
1. Connect the circuit as shown in fi gure.
2. Apply Vc c & ground signal to every IC.
3. Observe the input & output according to the truth table.

TRUTH TABL E:
SR F LIP FLOP:
Q
CLOCK S R n +1
1 0 0 NO CH ANGE
1 0 1 0
1 1 0 1
1 1 1 ?

D FL IPFLOP:

INPUT OU TPUT
0 0
1 1

JK FLIPFLOP
Q
CLOCK S R n +1
1 0 0 NO CH ANGE
1 0 1 0
1 1 0 1
1 1 1 Qn ’
 T FLIP FLOP

Q
CLOCK S R n +1
1 0 1 NO CH ANGE
1 1 0 Qn ’

RESULT: Truth table is verified on digital trainer.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

Q 1.Flip flop is Astable or Bistable?

Ans. Bistable.
Q2.What are the I/Ps of JK flip–flop where this race round condition occurs?
Ans. Both the inputs are 1.
Q3.When RS flip-flop is said to be in a SET state?
Ans. When the output is 1.
Q4.When RS flip-flop is said to be in a RESET state?
Ans. When the output is 0.
Q5.What is the truth table of JK flip-flop?
Q
J K n+1
0 0 Qn
0 1 0
1 0 1
1 1 ’
Qn,
Q6.What is the function of clock signal in flip-flop?
Ans. To get the output at known time.
Q7.What is the advantage of JK flip-flop over RS flip-flop?
Ans. In RS flip-flop when both the inputs are 1 output is undetermined.
Q8.In D flip-flop I/P = 0 what is O/P?
Ans.0
Q9.In D flip-flop I/P = 1 what is O/P?
Ans.1
Q10.In T flip-flop I/P = 1 what is O/P?
Ans. Qn
 EXPERIMENT NO: 6
Aim: – Design, and Verify the 4-Bit Asynchronous Counter.

APPARATUS REQUIRED: Digital trainer kit and 4 JK flip flop each IC 7476 (i.e dual JK flip flop)
and two AND gates IC 7408.

BRIEF THEORY: Counter is a circuit which cycle through state sequence. Two types of counter,
Synchronous counter (e.g. parallel) and Asynchronous counter (e.g. ripple). In Ripple counter same
flip- flop output to be used as clock signal source for other flip-flop. Synchronous counter use the
same clock signal for all flip-flop.

PIN CONFIGURATION:

Pin diagram of JK M/S Flip Flop

LOGIC DIAGRAM:
4- Bit Asynchronous counter

Pin Number Description

 1 Clock 1 Input
2 Preset 1 Input
3 Clear 1 Input
4 J1 Input
5 Vcc
6 Clock 2 Input
7 Preset 2 Input
8 Clear 2 Input
9 J2 Input
10 Complement Q2 Output
11 Q2 Output
12 K2 Input
13 Ground
14 Complement Q1 Output
15 Q1 Output
16 K1 Input
PROCEDURE:
a) Make the connections as per the logic diagram.
b) Connect +5v and ground according to pin configuration.
c) Apply diff combinations of inputs to the i/p terminals.
d) Note o/p for summation.
e) Verify the truth table.

RESULT: 4-bit asynchronous counter studied and verified.

PRECAUTIONS:
1. Make the connections according to the IC pin diagram.
2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

Quiz Questions with answer.

How many flip-flops are required to make a MOD-32 binary

counter? Ans. 5.
The terminal count of a modulus-11 binary counter is .
Ans.1010.
Synchronous counters eliminate the delay problems encountered with
asynchronous counters because the:
Ans. Input clock pulses are applied simultaneously to each stage.
Q4. Synchronous construction reduces the delay time of a counter to the delay of:

Ans. a single flip-flop and a gate.

Q5. What is the difference between a 7490 and a 7492?

Ans.7490 is a MOD-10, 7492 is a MOD-12.

Q6. When two counters are cascaded, the overall MOD number is equal to the
of their individual MOD numbers.
Ans. Product.
Q7. A BCD counter is a .
Ans. decade counter.
Q8. What decimal value is required to produce an output at "X" ?

Ans.5.

Q9. How many AND gates would be required to completely decode ALL the states of a MOD-64
counter, and how many inputs must each AND gate have?

Ans. 64 gates, 6 inputs to each gate.

Q.10 A ring counter consisting of five Flip-Flops will have
Ans. 5 states.
 EXPERIMENT NO - 7

Aim – To verify the operation of bi-directional shift register.

Apparatus Required: -– Digital trainer kit, IC 7495,Connecting wires etc.

Brief Theory:-
A bidirectional shift register is one in which the data can beshifted either left or right. It can be
implemented by using gatelogic that enables the transfer of a data bit from one stage to thenext
stage to the right or to the left, depending on the level of acontrol line. A 4-bit bidirectional shift
register is shown inFigure below. A HIGH on the RIGHT / LEFT control input allows databits
inside the register to be shifted to the right, and a LOWenables data bits inside the register to be
shifted to theleft.

Procedure:-

Serial In Parallel Out(SIPO):-

1. Connections are made as per circuit diagram.

2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift
to QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into
the shift register.
Serial In Serial Out(SISO):-

1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at
QD. Thus the data applied serially at the input comes out serially at QD
Parallel In Serial Out (PISO):-

1. Connections are made as per circuit diagram.

2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied
at A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the
Data coming out serially at QD

Parallel In Parallel Out (PIPO):-

1. Connections are made as per circuit diagram.

2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD
respectively.

PIN CONFIGURATION–
RESULT- 4-bit bidirectional shift register is studied and verified.
 EXPERIMENT NO - 8

AIM: - Operate the counters 7490, 7493.

APPARATUS REQUIRED:-
Logic trainer kit, Counter ICs- 7490, IC - 7493 wires.

THEORY:

Asynchronous 74LS90 Decade Counter

Digital counters count upwards from zero to some pre-determined count value on the application
of a clock signal. Once the count value is reached, resetting them returns the counter back to zero
to start again.
A decade counter counts in a sequence of ten and then returns back to zero after the count of nine.
Obviously to count up to a binary value of nine, the counter must have at least four flip-flops
within its chain to represent each decimal digit as shown.

The 74LS90 BCD Counter

The 74LS90 integrated circuit is basically a MOD-10 decade counter that produces a BCD output
code. The 74LS90 consists of four master-slave JK flip-flops internally connected to provide a
MOD-2 (count-to-2) counter and a MOD-5 (count-to-5) counter. The 74LS90 has one
independent toggle JK flip-flop driven by the CLK A input and three toggle JK flip-flops that
form an asynchronous counter driven by the CLK B input as shown.

The counters four outputs are designated by the letter symbol Q with a numeric subscript equal to
the binary weight of the corresponding bit in the BCD counter circuits code. So for example, QA,
QB, QC and QD. The 74LS90 counting sequence is triggered on the negative going edge of the
clock signal, that is when the clock signal CLK goes from logic 1 (HIGH) to logic 0 (LOW).
The additional input pins R 1 and R2 are counter “reset” pins while inputs S 1 and S2 are “set” pins.
When connected to logic 1, the Reset inputs R 1 and R2 reset the counter back to zero, 0 (0000), and
when the Set inputs S1 and S2 are connected to logic 1, they Set the counter to maximum, or 9
(1001) regardless of the actual count number or position.
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the Counters were designed and their truth table is verified.

PRECATIONS:

 All connections should be made neat and tight.

 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.
 EXPERI MENT NO :9
Aim:- Implementation of 4x1 multiplexer using Logic Gates
APPARATUS REQUIRED: -
logic trainer kit, IC- 74150, wires.
THEORY:

A Multiplexer (or a data selector) is a logic circuit that accepts several data inputs and allows only
one of them at a time to get through to the output. The selection of the desired data input is
controlled by the SELECT (or ADDRESS) INPUTS. Multiplexer means transmitting a large number
of information units over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many input lines and directs it to a
single output line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine which input
is selected. Figure below shows the block diagram of a Multiplexer.

In this diagram the inputs and outputs are indicated by means of broad arrows to indicate that there
may be one or more lines. Depending upon the digital code applied at the SELECT inputs, one out of
the data sources is selected and transmitted to the single output channel. The Multiplexer becomes
enabled when the strobe signal is active LOW. The pin out of a 8:1 multiplexer IC 74150 is shown
above. The output of this circuit is the inverted input. This is a 16-pin DIP.
Function Table
INPUT OUTPUT
S1 S0 Y
0 0 D0 = D0 S1’ S0’
0 1 D1 = D1 S1’ S0
1 0 D2 = D2 S1 S0’
`1 1 D3 = D3 S1 S0
Y = D0 S1’ S0’ +D1 S1’ S0 +D2 S1 S0’ +D3 S1 S0
PIN DIAGRAM: CIRCUIT DIAGRAM FOR MULTIPLEXER:

Truth Table
INPUT OUTPUT
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

PROCEDURE: -

1) Assemble the circuit on bread board, as per above diagram.

2) Give the logical inputs and check for the proper output, as per the truth table.

CONCLUSION:

Hence verified the Multiplexer (8:1) operation using IC-74150

PRECAUTIONS:

 All connections should be made neat and tight.

 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.
 EXPERIMENT – 10
AIM: -
Verification of the truth table of the De-Multiplexer 74154.

APPARATUS REQUIRED :-
Logic trainer kit, IC- 74154, wires.

THEORY:

A Demultiplexer performs the reverse operation of a Multiplexer. It accepts a single input and
distributes it over several outputs. The SELECT input code determines to which output the data input
will be transmitted. The Demultiplexer becomes enabled when the strobe signal is active LOW.
This circuit can also be used as binary-to-decimal decoder with binary inputs applied at the select
input lines and the output will be obtained on the corresponding line. These devices are available as
2-line-to-4-line decoder, 3-line-to- 8-line decoder, 4-line-to-16-line decoder. The output of these

devices is active LOW. Also there is an active low enable/data input terminal available. Figure below
shows the block diagram of a Demultiplexer.
PIN CONFIGURATION:
FUNCTION TABLE:
S1 S0 INPUT
0 0 D0 = X S1’ S0
0 1 D1 = X S1’ S0
1 0 D2 = X S1 S0’
1 1 D3 = X S1 S0
Y = X S1’ S0 + X S1’ S0 + X S1 S0’ + X S1 S0
In this diagram the inputs and outputs are indicated by means of broad arrows to indicate that there
may be one or more lines. Depending upon the digital code applied at the SELECT inputs, one data
is transmitted to the single output channel out of many. The pin out of a 16:1 Demultiplexer IC
74154 is shown above. The output of this circuit is active low. This is a 24-pin DIP.
 PIN DIAGRAM: CIRCUIT DIAGRAM:

TRUTH TABLE
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PROCEDURE: -

1) Assemble the circuit on bread board, as per above Pin diagram.

2) Give the logical inputs and check for the proper output, as per the truth table.

CONCLUSION:

Hence verified the Demultiplexer (16:1) operation using IC-74154.

PRECAUTIONS:

 All connections should be made neat and tight.

 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.