Vlsi Document
Vlsi Document
PROJECT REPORT
on
In
VLSI DESIGN
by
KOTHURI . SRAVANI
2019 -2022
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
2019 -2022
CERTIFICATE
This is to certify that the project entitled “Design of low area low power combinational circuits
using CNTFET’s” being submitted by K. SRAVANI (19JD1D7210), in view of academic
curriculum, Degree of Bachelor of Technology in Electronic and Communication Engineering during
2019 – 2022 and is a bonfide work carried out by them under my guidance and supervision.
EXTERNAL EXAMINER
ACKNOWLEDGEMENT
In the beginning I want to elucidate that this project would have been a distant dream
without the grace of Almighty God who has blessed us with a drop of knowledge from his
mighty ocean.
I am very grateful to my project guide M.PRIYANKA M.Tech for his inspiration, adroit
guidance, constant supervision and constructive criticism in successful completion of this
project. he provided organization, supported enthusiastic discussions, in depth reviews and
valuable references.
I am very grateful to the head of the ECE Department Dr.B.RAJARAO Ph.D Professor
for his valuable guidance, motivation and endless supply of new ideas and technical
support for this project.
I am thankful to our Principal Dr. P. BALAKRISHNA PRASAD Ph.D for permitting
and encouraging me in doing this project.
I extend my sincere thanks to Sri V. Raghavendra Rao, Chairman of our college for
providing sufficient infrastructure and good environment in the college to complete my
course.
Great acknowledgement is expressed to Coordinator, Teaching and Non- Teaching Staff
Members whose guidance cannot be ignored in completing this project in time
KOTHURI.SRAVANI
(19JD1D7210)
DECLARATION
I here by declaring that the project work entitled “Design of low area low power
combinational circuits using CNTFET’s” submitted to JNTU Kakinada, is a record of
original work done by me.
This project work is submitted in the partial fulfillment for the degree of Master of
Technology in Very large scale integration Circuit Design.
The results embedded in this thesis have not been submitted to any other University
or Institute for the award of any degree or Diploma.
KOTHURI.SRAVANI
(19JD1D7210)
INDEX
TABLE OF CONTENT`
CHAPTER 6 CONCLUSON 46
6.1 Advantages 47
6.2 Applications 47
6.3 Future Scope 47
REFERENCES 48
APPENDIX 51
A1: ABOUT SIMULATION TOOL 51
A2: JOURNAL PUBLICATION
LIST OF FIGURES
Fig No. Figure Name Page No.
i
5.3.1 Voltage variations 43
5.3.2 Temperature variations 44
5.4.1 Noise signal 45
ii
LIST OF TABLES
19
3.1.1 Truth table of multiplexer
3.3.1 Truth table of ternary half adder 21
iii
LIST OF ACRONYMS
ACRONYM DESCRIPTION
Nm Nano Meter
TG Transmission Gate
iv
ABSTRACT
Embedded systems, Internet of Things (IoT) gadgets, and portable
electronic devices have all become highly popular in recent years. The majority of
them run on batteries. The major goal of this project is to reduce battery usage
while also providing an energy-efficient solution for low-power portable
electronics and embedded systems.
Using 32nm CNFET’s, the project proposes ternary combinational circuits.
This study employs a power supply that provides two voltage supplies (Vdd and
Vdd/2) and so reduces the overall energy consumption in the circuit to reduce
energy consumption by exploiting the unary operator of ternary systems. This
proposed design show the improvements in the 25% in transistor count and 98% in
energy consumption reduction’s.
v
DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S
CHAPTER-1
INTRODUCTION
1. INTRODUCTION
Now a days, in our day to day life every electronic gadget is compressed of
the combinational circuits in which FET’S plays a vital role. In microprocessors
these adders requires high power and where delay will also be high. so, in order
to reduce that a high speed and low power combinational circuit’s is designed
through very largescale integrated circuits.
1.1 VLSI
1.4APPLICATIONS OF VLSI:
Electronic systems now perform a wide variety of tasks in daily life.
Electronic systems in some cases have replaced mechanisms that operated
mechanically, hydraulically, or by other means; electronics are usually smaller,
more flexible, and easier to service. In other cases electronic systems have
created totally new applications. Electronic systems perform a variety of tasks,
some of them visible, some more hidden:
2. Electronic systems in cars operate stereo systems and displays; they also
control fuel injection systems, adjust suspensions to varying terrain, and perform the
control functions required for antilock braking (ABS) systems.
Carbon nano tube with multiple diameter is placed between source and drain
terminals, Due to the applied voltage to the gate terminal integrates the current
flow in CNT which helps in easy flow of current from source to drain. Threshold
voltage depends on the diameter of the carbon nano tube, Switching depends on
the diameter of the carbon nano tube. Ternary half adders and Ternary
multipliers can be designed by using CNTFET’s
The point here is that this is merely an issue of the encoding of logic values
and, as the following circuit examples indicate, the use of MVL concepts in the
design stage often leads to circuits that exhibit better characteristics than would
be obtained if only binary-valued logic were utilized.
There are two kinds of MVL circuits based on MOS technology, namely the
current-mode MVL circuits and the voltage mode MVL circuits. Voltage-mode
MVL circuits have been achieved in multi threshold CMOS design. The carbon
nanotube (CNT) FET (CNTFET) is a promising alternative to the bulk silicon
transistor for low-power and high-performance design due to its ballistic
transport and low OFF-current properties.
A multi threshold CMOS design relies on body effects using different bias
voltages to the base or the bulk terminal of the transistors. In a CNTFET, the
threshold voltage of the transistor is determined by the diameter of the CNT.
Therefore, a multi threshold design can be accomplished by employing CNTs
with different diameters (and, therefore, chirality) in the CNTFETs. A resistive-
load CNTFET-based ternary logic design.
Figure 1.5.2 shows the schematic diagram and the symbol of sum
operator. SUM output for different combination of two 1-bitternary inputs can
be obtained
Using CMOS devices, ternary logic circuits it has been shown that the
performance of CMOS-based circuit designs can be improved by adding MVL
blocks to binary designs. A 2-bit ternary ALU design is designed, where
negative voltage levels were used to indicate the third state. Various intriguing
designs for single trit addition and single trit multiplication. A ternary logic
system is a multi valued logic (MVL) system with three logic levels which
correspond to logic 0, logic1 and logic 2. In a balanced or ternary neutral system,
the three logic levels are identified as -1, 0 and 1.
CMOS logic style is a combination of the pMOS and nMOS.it provides the
delay of the adder. the main advantage of the CMOS style is voltage scaling and
transistor sizing. but the disadvantage is usage of more transistors leads to
greater area. another one is weak driving capability which can be corrected by
adding buffers at the output terminal.
In transmission gate style the pMOS and nMOS are connected in parallel
and control signals are given to separately to both the channels. It performs
better compared to the CMOS logic style because of its decrease in no of
transistors and in terms of delay.
Pass transistor logic is used to reduce the number of the transistors in the
logic function. In this design style the primary inputs drives drain and source
terminals which leads to reduce number of transistors. due to decrease of the
transistors count the capacitance becomes low. It reduces number of transistors
compared to CMOS and TG styles.
Here, the full adder can be realized through hybrid approach for four different circuits.
Transmission gate, CMOS style and using inverters two designs.
CHAPTER-2
LITERATURE SURVEY
It has high PDP and large memory is required and high transistor count.
The drawback of this design is it has medium Transistor count and medium PDP
Fig 2.4: Proposed designs for ternary NAND and NOR [14]
It has medium transistor count and medium PDP and the design of the circuit is
complex as well.
In 2020, Ramzi A. Jaber [16] was presented a design of ternary half adder with
novel decoder less design.
Using unary operator by cascading TMUX”s technique , without using the
decoder. MVL reduces the Interconnections and energy consumption in the
circuit. THA with 90-transistors as shown in fig 6.
Fig 2.5 shows the TMUX with 15 CNTFET’s using cascading multiplexers
technique without using the decoder in the design, MVL reduces the
interconnections in the circuit and also PDP
CHAPTER-3
EXISTING SYSTEM
In fig 3.1.1 three different unary operators are shown, Unary operators are
the single input single output logic devices which helps in the reduce the logic
gates in the circuit, Unary operators along with the Multi Valued Logic is used to
design the existing design of multiplexer
ECET DEPT OF ECE 15
DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S
In terms of circuit design, it is important to note that MVL methods are not
germane only to implementations that encode logic values as more than two
discrete voltage or current signals, but that MVL methods are also important as
models for the initial design of logic circuits whether they are implemented with
binary or MVL signal levels.
In fig 3.1.2 block diagram and table 3.1.1 shows truth table of multiplexer is
shown and the adders are connected in the multi-trit(3-trit) multiplier. The inputs
of the traditional multiplexer having the 3 inputs 0,1 and 2 as they use the
multivalued logic. NCNTFET will be ON for high input, PCNTFET will be on for
Low input.
In fig 3.2.1 represents the single trit multiplier based on the CNTFET
realisation using 26- transistors which lesser compared to the previous works and
it do have low PDP and transistor count
In the fig 3.3.1 shows ternary half adder and table2 shows truth table of the ternary
half adder is shown
S is the select signal and D0, D1 and D2 are the data lines. where SP is the output of a
positive ternary inverter and SN is the output of a negative ternary inverter. It is worth
noting that the select signals SP and SN are the positive and negative ternary
inverters, each of which requires
The main drawback of the existing model is due use of single voltage
source the heat is increased within the circuit called JOULE POWER effect. In
proposed model two voltages are used to reduce the JOULE POWER effect.
CHAPTER-4
PROPOSED SYSTEM
In fig 4.1.1 and table 4.1.1shows proposed five unary operators with D1 and D2 diameter
and CNTFET operation for D1 and D2 is shown
In table 4.1.2 the unary operators shown which shows the on and off conditions
of the transistors.
A one-trit THA combines two ternary inputs and produces two ternary values (Sum and
Carry).
Based on unary operators, TGs, and two voltage supplies (Vdd, Vdd /2), this research
presents a THA with 36 CNFETs. From the input "A" to the output "Sum," the maximum
propagation delay exists in this. When the input "A" moves from 1 to 2, "B" = 2, and the
Sum changes from 0 to 1, this route is referred to as the critical path (red dotted line).
Fig 4.3.1 represents the proposed ternary multiplier with 23 transistors with lower
power and low PDP compared to the existing work
Product = 0 · B0 + A · B1 + ¯A2B2
Table 4.3.1 represents the truth table for the proposed TMUL which provides
the sufficient information for the on and off conditions of the transistor
Table 4.3.2, 4.3.3and 4.3.4 represents the truth tables of carrier with different
versions. As there are different voltages are used to reduce the Joule power effect
and also total power consumption in the circuit.
Table 4.3.5 compares the proposed ternary half adder with different existing
models [12], [13], [16], [18], [19], [22], [23], [24], [25], [26], [27], [28] and [29]. As
it shows that proposed design consumes low power for switching and also very less
transistor count and low PDP.
Table 4.3.6 compares the proposed ternary multiplier with different existing models
[13], [14], [17], [18], [19], [20], [22], [24] and [29]. As it shows that proposed
design consumes low power for switching and also very less transistor count and
low PDP
CHAPTER-5
SIMULATION RESULTS
5.1 SIMULATION
In this test bench circuit interconnections are done and the measuring devices are
connected externally to find the power, delay and internal noise in the circuit.
Transient analysis of the ternary half adder is observed in w-edit tool to obtain
the two inputs and sum, carry, four print voltage components are used connect to the
output side of the test bench hence the “A”, “B”
“sum” and “carry” are observed in the w-edit tool interface as shown in the
figure 5.1.1.3
To find the power, Print Power measuring device is added to the test bench and
when we run the simulation power values with respect to the different temperatures
were obtained because temperature sweep is included in the circuit. Average power
consumed at temp 0 is 1.393995e+001 watts and max and min are 2.411675e+001
and 0 respectively at time 1.1e-008 for max power as shown in the figure 5.1.1.4.
To find the delay, Measure inverting delay component is connect to the test
bench the simulated output waveforms are obtained with respect to the temperature
and the total delay in the design is 8.7ps. And the simulated result obtained is lesser
compared to the existing design and the Powe Delay Product is 0.78 (*10^-18 j).
which is much lesser than any existing designs mentioned in the above as shown in
the figure 5.1.1.5.
In this test bench circuit interconnections are done and the measuring devices are
connected externally to find the power, delay and internal noise in the circuit.
Temperature sweep is added to find the parameters with respect to the desire
temperature. Measure inverting delay component’s one is connect to the input side of
the test bench and another is connected to the output side. Print power is used to print
the power consumed by the circuit with respect to temperature as shown in the figure
5.1.2.2.
To find the power, Print Power measuring device is added to the test bench and
when we run the simulation power values with respect to the different temperatures
were obtained because temperature sweep is included in the circuit. Average power
consumed at temp 0 is 7.772772e+001 watts and max and min are 1.344613e+001
and 0 respectively at time 1.10206e-008 for max power as shown in the figure 5.1.2.4.
Figure 5.2.3.1 shows the voltage variation compared to existing THA and
TMUL of [13], [16], [17], [19], [24], [28], [29] regarding the energy consumption
PDP. These parameters used are temperature set with the value 27 ◦C, frequency
value at 1 GHz, and supply voltages varying from 0.8 V to 1 V.
Figure 5.3.2 shows the temperature variation compared to existing THA and
TMUL of [13], [16], [17], [19], [24], [28], [29] regarding the energy consumption
PDP. The parameters are frequency value set at 1 GHz, power supply at 0.9 V, and
temperatures varying within the range 10 ◦C to 70 ◦C.
Figures 5.3.1 and 5.3.2 show that the proposed designs resulted in the lowest
PDP compared to other designs regarding voltage and temperature variations.
CHAPTER 6
CONCLUSION
.
CONCLUSION
This project proposed novel 32 nm channel CNFET-based designs of eight
Unary Operators to layout a Ternary Half Adder with 36 transistors and a Ternary
Multiplier with 23 transistors. To obtain the objective, the layout system hired
specific strategies to lower the general strength intake withinside the circuit via way
of means of the use of unary operators, voltage resources Vdd and Vdd /2, and
transmission gates.
After simulating the proposed design the use of TANAR T-SPICE, the
proposed circuits performed a decrease PDP towards all the checkout circuits for
distinctive simulation parameters, PVT variations, and noise outcomes studies. In
addition, the proposed designs proved to have a better noise tolerance and better
robustness to technique variations.
This is aligned with the primary motive of this work to lessen battery
consumption, offer an energy-green implementation for low-electricity transportable
electronics and embedded devices
6.1 ADVANTAGES:
1. Better control over channel formation
6.2 APPLICATIONS:
1. Arithmetic circuits like adder, multiplier etc., are the most important
circuits in digital signal processing and many more applications.
REFERENCES
APPENDIX
Using these engine tools, spice program provides facility to the use to design & simulate
new ideas in Analogue Integrated Circuits before going to the time consuming & costly
process of chip fabrication.
3. Design connectivity.
The user interface consists of the elements shown below. Unless you explicitly retrieve a
setup file, the position, docking status and other display characteristics are saved with a design
and will be restored when the design is loaded as shown in figure A.1.1.
Menu Bar
The menu bar contains the S-Edit menu titles. The menu displayed may vary depending
on the view type that is active. See “Shortcuts for Cell and View Commands” on for the
various methods S-Edit provides for executing commands.
Toolbars
You can display or hide individual toolbars using the View > Toolbars command, or by
right-clicking in the toolbar region. Toolbars can be relocated and docked as you like. For
added convenience, S-Edit displays a tool tip when the cursor hovers over an icon.
Standard Toolbar
The Standard toolbar provides buttons for commonly used file and editing commands, as
well as operations specific to S-Edit such as “View Symbol” as shown in figure A.1.3.
Draw Toolbar
The Draw toolbar provides tools used to create non-electrical objects, such as rectangles,
circles, and lines, for illustrating and documenting a design shown in figure A.1.4.
Segment Toolbar
The Segment toolbar provides tools with which you limit the degree of angular freedom
allowed when you are drawing wires as shown in fig A.1.5.
Electrical Toolbar
The Electrical toolbar provides the tools used to create wires, nets, and ports, and to add
properties as shown in figure A.1.6.
Locator Toolbar
The Locator toolbar displays the coordinates of the mouse cursor and allows you to quickly
change the units of measurement application-wide as shown in fig A.1.8.
Mouse buttons vary in function according to the tool that is active. The Shift, Ctrl and Alt
keys can further change the function. For two-button mice, the middle-button function is
accessed by clicking the left and right buttons at the same time, or by pressing Alt while
clicking the left mouse button.
Customizing Toolbars
You can add buttons for existing commands to existing S-Edit toolbars, add entirely new
toolbars, and add new buttons for entirely new commands to either new or existing toolbars. To
customize toolbars, right-click anywhere in the toolbar area and click on Customize in the
context-sensitive menu as shown in figure A.1.10.
Reset returns an existing toolbar to the default display settings for aspects such as icon
size, tooltips, etc. – see “Menu and Toolbar Display Options” and its original button contents.
The New, Rename and Delete functions apply only to custom toolbars.
1. Right-click in the toolbar area, select Customize and then the Commands tab.
2. Pick the desired command from the Categories list (or use All Commands for a
complete list of available commands), then simply click-and-drag the command from the right
column to the desired toolbar.
3. S-Edit will insert a button displaying the command text, or an icon if one is
already defined.
2. In the Commands tab, scroll down to New Menu at the end of the Categories
3. Click-and-drag New Menu from the right column to the Menu bar in the interface
as shown in figure A.1.13.
4. Right-click on the New Menu button you have just placed to open the control
menu, where you can rename it, then check Begin a Group to populate the menu with pull-
down commands.
5. Select the new menu button in the interface to open the pull-down group, then
clickand-drag from the Commands tab to add the desired command(s). Make sure to drop the
commands within the group area as shown in fig A.1.14.
2. Enter the desired name in the New Toolbar window and click OK to display
3.Note that although it has a name, the new toolbar is small and blank when first placed –
you may have to search a bit to find it as shown in fig 5.1.1.15.
4.If you have just added the toolbar, you can click-and-drag from the Commands pane to
add an existing command. Otherwise, right-click in the toolbar area, select Customize,
highlight a menu in the Categories pane then click-and-drag the desired command from the
Commands pane to your new toolbar as shown in fig A.1.16
As long as the TCL function is loaded into S-Edit during the current editing session,
SEdit will run the function when you press the custom button to execute the operation. Lastly,
if you want a button to work in subsequent sessions, you will need to save it to an S-Edit start
up folder.
1. Enter and execute each of these TCL functions separately in the S-Edit command
window. Note that they must be entered in one unbroken line:
proc Grid Double {} {setup schematic grid set -snap grid size [expr 2*[setup
schematic grid get -snap grid size]] -units iu} proc Grid Half {} {setup schematic grid set -snap
grid size
1. Create a new toolbar named “Custom Snap Grid” (see “Adding a New Toolbar”,
above).
2. If you have just added the toolbar you can click on the Commands tab, scroll
down to the bottom of the list and select Custom. If not, right-click in the toolbar area, select
Customize, highlight the “Custom Snap Grid” menu, click on the Commands tab, and scroll
down to the bottom of the list and select Custom.
3. Grab the text “Execute button text as Tcl” from the right pane and drag it to the
newly created toolbar as shown in figure A.1.17.
1. Repeat step 4 to add a second “Execute button text as Tcl” button to the toolbar.
Right-click on the new button and name it “Grid Half.”
2. With a schematic view open, launch Setup > Technology > Schematic Grids. Note
the current snap grid size, then press Grid Double and Grid Half a few times to confirm that the
buttons are working.
3. The scripts will execute for the duration of the current session. To execute them
each time S-Edit launches you must save the TCL commands, as Grid Half tcl and Grid
Double. tcl, in the S-Edit start up directory (typically C:/Documents and Settings//Application
Data/Tanner EDA/scripts /start up for Windows XP or C:/Users//AppData/Roaming/Tanner
EDA/ scripts/start up for Windows 7 as shown in figure A.1.18
Name: Use this field to edit the button name when it is displayed as text, or to enter the
name of the TCL command to issue. The tooltip will not be affected.
Reset Button Image: Resets all changes to the button image and text.
Edit button Image: Opens the Button Editor where you can perform.
Change Button Image: Opens a small palette of clip art from which you can choose
an icon as shown in fig A.1.21
Default Style:Displays the default (image only) for the selected toolbar.
Text Only:Displays just the contents of the Name field for the selected.
Image and Text:Displays both the icon and the text from the Name field.
Commands:Select the command for which you want to add or change a keyboard
shortcut. As shown in the fig A.1.22.
Press new shortcut key:Highlight a command in the Commands pane, then use
this field to enter the key(s) that will be the shortcut. You can use any combination of the Alt,
Shift and Ctrl keys with any of the character keys. S-Edit will warn you if your entry is already
in use. (Since this field interprets any key you press literally, you cannot delete a value in this
field—simply enter a different value.)
Always show full menus option so that all commands are displayed on the menu. Show full
menus after a short delay:(Not operational.) Reset menu and toolbar
usagedata:
Deletes the record of all the commands used in S-Edit (for short menu display) and
restores the default set of visible commands to the menus and toolbars. However, explicit
changes you have made in the current or earlier sessions will remain.
Large icons:
Check this box to display large toolbar buttons.
Menu animations:
You can choose from the list to add animation to the open menu operation.
Status Bar:
The Status Bar display varies with the type and number of objects selected and the tool in
use. You can use View > Status Bar to toggle display on and off.
Design Area:
The region in Tanner tools where you create, view and edit objects is called the Design
Area. The portion of the design area currently visible is called the Work Area. You can move
or resize design windows as you would in any other application window. Refer to “The Work
Area” on page 38 for further information as shown in fig A.1.24.
Simulation output files (.out): containing the numerical results of the circuit
analyses, for manipulation and display by W- Edit" Waveform Viewer.
model of the circuit to be simulated. Input files can be created and modified with any text
editor. T-Spice is a tool used for simulation of the circuit. It provides the facility of
1. Design Simulation
2. Simulation Commands
3. Device Statements
The ability to visualize the complex numerical data resulting from VLSI circuit
simulation is critical to testing, understanding & improving these circuits. W-Edit is a
waveform viewer that provides ease of use, power & speed in a flexible environment
designed for graphical data representation.
By
KOTHURI SRAVANI
ORIGINALITY
REPORT
19 %
11% 5% 3%
INTERNET PUBLICA STUDENT PAPERS
SIMILARITY
SOURCES TIONS
INDEX
PRIMARY SOURCES
%
2
1 InternetSource
https://www.computer.org/csdl/journal/si/2020/12/09197665/1n8WM03Ndpm
2
https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=202002259857958152
Publication 2%
3
https://www.maximintegrated.com/en/design/technical-documents/app-notes/6/647.html
Student Paper
2%
4
https://ur.booksc.eu/book/83641549/7a46ca
InternetSource
1%
5 %
1
https://silo.tips/download/study-and-analysis-of-different-types-of-comparators
InternetSource
DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S
1%
http://www.diva-portal.org/smash/get/diva2:547130/FULLTEXT02.pdf
6 InternetSource
DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S
https://www.analog.com/media/en/training-seminars/tutorials/MT-083.pdf
7 InternetSource
1%
8 %
1
InternetSource
www.ijipsr.com
9 %
1
InternetSource
https://ime.um.edu.mo/wp-content/uploads/magazines/b1eb74af1559bd472c36ddfbba0be030.pdf
10 %
1
http://ethesis.nitrkl.ac.in/5184/1/109EI0338.pdf
InternetSource
11 %
1
https://freepaper.me/downloads/abstract/10.1109/TVLSI.2020.3021680
InternetSource
12 %
1
https://dblp.org/pid/146/1439.xml
InternetSource
13 %
1
www.ijptonline.com
InternetSource
14
16
15
DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S
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DESIGN OF LOW AREA LOW POWER COMBINATIONAL
CIRCUITS USING CNTFET’S
KOTHURI SRAVANI, M.PRIYANKA
1 2
Assistant Professor, Dept. of ECE, Eluru College of Engineering and Technology, ELURU, AP
2
ABSTRACT: Embedded systems, Internet of Things (IoT) gadgets, and portable electronic devices
have all become highly popular in recent years. The majority of them run on batteries. The major goal
of this project is to reduce battery usage while also providing an energy-efficient solution for low-
power portable electronics and embedded systems. Using 32nm CNFET’s, the project proposes
ternary combinational circuits. This study employs a power supply that provides two voltage supplies
(Vdd and Vdd/2) and so reduces the overall energy consumption in the circuit to reduce energy
consumption by exploiting the unary operator of ternary systems. This proposed design show the
improvements in the 25% in transistor count and 98% in energy consumption reduction’s.
Keywords: CNTFET’s, Unary operators, Ternary combinational circuit
INTRODUCTION:
In terms of circuit design, it is important to note that MVL methods are not germane only to
implementations that encode logic values as more than two discrete voltage or current signals, but that
MVL methods are also important as models for the initial design of logic circuits whether they are
implemented with binary or MVL signal levels. The issue of whether the ultimate realization of a logic
circuit is binary or not depends on the underlying technology and is independent of the use of MVL.
As an example, complementary metal oxide semiconductor (CMOS)-based logic circuitry is generally
implemented in binary logic since technology issues make binary the best choice. The point here is
that this is merely an issue of the encoding of logic values and, as the following circuit examples
indicate, the use of MVL concepts in the design stage often leads to circuits that exhibit better
characteristics than would be obtained if only binary-valued logic were utilized. There are two kinds of
MVL circuits based on MOS technology, namely the current-mode MVL circuits and the voltage
mode MVL circuits. Voltage-mode MVL circuits have been achieved in multi threshold CMOS
design. The carbon nanotube (CNT) FET (CNTFET) is a promising alternative to the bulk silicon
transistor for low-power and high- performance design due to its ballistic transport and low OFF-
current properties. A multi threshold CMOS design relies on body effects using different bias voltages
to the base or the bulk terminal of the transistors. In a CNTFET, the threshold voltage of the transistor
is determined by the diameter of the CNT. Therefore, a multi threshold design can be accomplished by
employing CNTs with different diameters (and, therefore, chirality) in the CNTFETs. A resistive-load
CNTFET-based ternary logic design. However, in this configuration, large OFF- chip resistors (of at
least 100 MΩ values) are needed due to the current requirement of the CNTFETs. The MVL relies on
and eliminates the large resistors by employing active load with p-type CNTFETs in the ternary logic
gates.
TERNARY HALH ADDER(THA):
A THA is a combinational digital circuit that accepts two1-bit ternary inputs and provides two outputs
SUM and CARRY. A new technique was introduced for voltage mode MVL using CNFETs with
resistive pull-ups. A sum gate was designed to perform ternary addition on two inputs IN1 andIN2 to
provide the sum output was carried out using CNFET switch pull-up resistors. and ternary full adder,
and multiplier designs and analysis are presented as examples of the application of these ternary gates
design technique. For the arithmetic circuit design, a modified ternary logic circuit design technique is
used to speed up and reduce power consumption of the circuits. Themodified ternary logic design uses
both ternary logic gates and binary logic gates based on the previous ternary logic design structures to
take advantage of the two logic design styles’ merits. Figure 1.1 shows
the schematic diagram and the symbol of sum operator. SUM output for different combination of two
1- bitternary inputs can be obtained
In fig 1.2 block diagram of the ternary multiplier with unary operators as shown above unary
operators are the one input and the one output logic devices out will be fixed in this work 5 unary
operators are used.
EXISTING SYSTEM:
MULTI-TRIT MULTIPLIER:
A single-trit multiplier can be realized with 26 CNTFETs. The select signal B for carry and product,
requires 9 CNTFETs while 8 CNTFETs are required for the internal logic of the two multiplexers. The
complete circuit. The overall CNTFET requirement is therefore 26. the existed multiplier is based on
the classical Wallace tree structure. The multiplier includes ternary half-adders and two custom full-
adder configurations, named F A1 and F A2 which are modifications of the traditional ternary full
adder.
In fig2.1 represents the single trit multiplier based on the CNTFET realisation using 26- transistors
which lesser compared to the previous works and it do have low PDP and transistor count
In the fig 2.2 shows ternary half adder and table2 shows truth table of the ternary half adder is shown
A ternary multiplexer requiring only 15 CNTFETs can be realized utilizing unary operators for the
seleced signal. The truth table for a ternary multiplexer is given where
S is the select signal and D0, D1 and D2 are the data lines. where SP is the output of a positive ternary
inverter and SN is the output of a negative ternary inverter. It is worth noting that the select signals SP
and SN are the positive and negative ternary inverters, each of which requires
The main drawback of the existing model is due use of single voltage source the heat is increased
within the circuit called JOULE POWER effect. In proposed model two voltages are used to reduce the
JOULE POWER effect.
PROPOSED UNARY OPERATORS
This project uses CNTFET transistors and unbalanced ternary logic system (Low: 0, Middle: 1, High:
2) that is equivalent to (0, Vdd /2, Vdd ). The circuit’s total power consumption is divided into two
types: static power and dynamic power. This project uses a power supply that generates two voltage
supplies Vdd and Vdd /2 to remove these two transistors and accordingly decrease the overall energy
consumption in the circuit. A ternary multiplexer requiring only 15 CNTFETs can be realized utilizing
unary operators for the select signal. The truth table for a ternary multiplexer is given. where S is the
select signal and D0, D1 and D2 are the data lines. where SP is the output of a positive ternary inverter
and SN is the output of a negative ternary inverter. It is worth noting that the select signals SP and SN
are the positive and negative ternary inverters, each of which requires 2 CNTFETs.
In fig 3.1 and table 3.1shows proposed five unary operators with D1 and D2 diameter and CNTFET
operation for D1 and D2 is shown
Table 32: Truth table for unary operators
In table 4.1.2 the unary operators shown which shows the on and off conditions of the transistors.
Half adders and 1-trit multipliers are employed in bigger structures like arithmetic processing units and
are critical components in VLSI circuits. As a result, increasing the efficiency of these circuits can
increase the performance of bigger processing units.
Two input variables and two output variables comprise a half-adder circuit. The cumulative
number is used as an input variable, while sum and carry are used as output variables. The author
devised a novel method that did not require the use of a decoder in order to solve the problem. THA's
design the use of a decoder is no longer necessary. Unary functions are created. The computation of
the unary functions transistor-level circuits The ternary output from these routines is provided by low-
power encoders. A one-trit THA combines two ternary inputs and produces two ternary values (Sum
and Carry).
Based on unary operators, TGs, and two voltage supplies (Vdd, Vdd /2), this research
presents a THA with 36 CNFETs. From the input "A" to the output "Sum," the maximum
propagation delay exists in this. When the input "A" moves from 1 to 2, "B" = 2, and the Sum
changes from 0 to 1, this route is
Fig 4.2 represents the proposed ternary multiplier with 23 transistors with lower power and low PDP
compared to the existing work
The base multiplier is based on the classic Wallace approach. Uses 3: 1 multiplexer and ternary unary
operator logic. This article describes the design of a low power single trit multiplier Describes the use
of CNFETs. The
simulation data for this design shows that the power delay product (PDP) is significantly lower With a
new design of single trit multiplier. 1-trit TMUL multiplies two ternary inputs and two outputs. 3
values (Product & Carry).
This proposed TMUL with 23 CNFETs. Use unary operator, TG, and two power supplies (Vdd, Vdd /
2) In the figure 4.2.2 The red dotted line is the critical path between the input `` A`` and output ``
Product``. Occurs when `` A`` Change state from 1 to 2, "B" = 1 and product It changes from 1 to 2.
Two cascade TGs that create more propagation delay.
SIMULA
TION
RESULT
S FOR
THA
Ternary half adder is designed using Tanner tool designed in the s-edit tool as shown in the figure
5.1.1.1.
Ternary Half adder is designed by 36-transistors using CNTFET’s based on unary operators, TG’s
and two voltage supplies (vdd, vdd/2). The maximum propagation delay in this design takes place
from the input “A” to the output “sum”. This is referred as the critical path.
Fig 5.1.1.2: test bench circuit for ternary half adder
In this test bench circuit interconnections are done and the measuring devices are connected externally
to find the power, delay and internal noise in the circuit.
Temperature sweep is added to find the parameters with respect to the desire temperature. Measure
inverting delay component’s one is connect to the input side of the test bench and another is connected
to the output side. Print power is used to print the power consumed by the circuit with respect to
temperature as shown in the figure 5.1.1.2.
Transient analysis of the ternary half adder is observed in w-edit tool to obtain the two inputs and sum,
carry, four print voltage components are used connect to the output side of the test bench hence the
“A”, “B”
“sum” and “carry” are observed in the w-edit tool interface as shown in the figure 5.1.1.3
Fig 5.1.1.4: power results of ternary half adder
To find the power, Print Power measuring device is added to the test bench and when we run the
simulation power values with respect to the different temperatures were obtained because temperature
sweep is included in the circuit. Average power consumed at temp 0 is 1.393995e+001 watts and max
and min are 2.411675e+001 and 0 respectively at time 1.1e-008 for max power as shown in the figure
5.1.1.4.
Fig 5.1.1.5: delay results for ternary half adder
To find the delay, Measure inverting delay component is connect to the test bench the simulated output
waveforms are obtained with respect to the temperature and the total delay in the design is 8.7ps. And
the simulated result obtained is lesser compared to the existing design and the Powe Delay Product is
0.78 (*10^-18 j). which is much lesser than any existing designs mentioned in the above as shown in
the figure 5.1.1.5.
RESULTS FOR TMUL:
Ternary multiplier is designed using Tanner tool designed in the s-edit tool as shown in the figure
5.1.2.1.
Fig 5.1.2.1: schematic design of TMUL
Ternary Multiplier is designed by 23-transistors using CNTFET’s based on unary operators, TG’s and
two voltage supplies (vdd, vdd/2). The maximum propagation delay in this design takes place from the
input “A” to the output “sum”. This is referred as the critical path.
Fig 5.1.2.2: test bench circuit for ternary multiplier
In this test bench circuit interconnections are done and the measuring devices are connected externally
to find the power, delay and internal noise in the circuit. Temperature sweep is added to find the
parameters with respect to the desire temperature. Measure inverting delay component’s one is connect
to the input side of the test bench and another is connected to the output side. Print power is used to
print the power consumed by the circuit with respect to temperature as shown in the figure 5.1.2.2.
To find the power, Print Power measuring device is added to the test bench and when we run the
simulation power values with respect to the different temperatures were obtained because temperature
sweep is included in the circuit. Average power consumed at temp 0 is 7.772772e+001 watts and max
and min are 1.344613e+001 and 0 respectively at time 1.10206e-008 for max power as shown in the
figure 5.1.2.4.
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