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    Assignment 4

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    SARISHA BIDAWATKA
    This document provides instructions for an assignment on multiplexers and demultiplexers in VHDL. Students are asked to write VHDL code to design a 2:1 multiplexer, 4:1 multiplexer, 1:2 demultiplexer, and 4:1 demultiplexer using smaller logic gates. They must test each design through simulation and demonstrate the functionality on a DE10 Lite board.

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    Assignment 4

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    SARISHA BIDAWATKA
    64 views2 pages
    This document provides instructions for an assignment on multiplexers and demultiplexers in VHDL. Students are asked to write VHDL code to design a 2:1 multiplexer, 4:1 multiplexer, 1:2 demultiplexer, and 4:1 demultiplexer using smaller logic gates. They must test each design through simulation and demonstrate the functionality on a DE10 Lite board.

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    This document provides instructions for an assignment on multiplexers and demultiplexers in VHDL. Students are asked to write VHDL code to design a 2:1 multiplexer, 4:1 multiplexer, 1:2 demultiplexer, and 4:1 demultiplexer using smaller logic gates. They must test each design through simulation and demonstrate the functionality on a DE10 Lite board.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    64 views2 pages

    Assignment 4

    Uploaded by

    SARISHA BIDAWATKA
    This document provides instructions for an assignment on multiplexers and demultiplexers in VHDL. Students are asked to write VHDL code to design a 2:1 multiplexer, 4:1 multiplexer, 1:2 demultiplexer, and 4:1 demultiplexer using smaller logic gates. They must test each design through simulation and demonstrate the functionality on a DE10 Lite board.

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    Indian Institute of Technology Goa

    EE 232 Digtial Circuits and Lab


    Instructor: Nandakumar Nambath
    Assignment IV: Multiplexers and Demultiplexers

    General instructions:
    • Go through the videos on VHDL and the sections 6.1 and 6.6 from Stephen Brown and Zvonko
    Vranesic, “Fundamentals of Digital Logic with VHDL Design,” Tata McGraw Hill before you attempt
    this assignment.

    • You are free to assume any missing data, but state them clearly in your solution. Feel free to use
    the Telegram group to discuss any doubts, but not the solutions.

    • Marks: VHDL code, Modelsim simulations, and viva - 7 Marks and board demonstration - 3 Marks

    1. Update the package with the name EE232 <Group No> with all the entities you have created so far.
    The entities corresponding to all the components should be there in separate VHDL files.

    2. 2:1 Multiplexer: Write a VHDL description for the following entity instantiating 2-input AND,
    2-input OR and NOT gates. (Hint: What is the Boolean expression of a 2:1 MUX output? Watching
    the Multiplexers and Demultiplexers video might help you.)

    entity MUX_2X1 is
    port(I0, I1, S0 : in std_logic; -- Inputs
    O0 : out std_logic); -- Output
    end MUX_2X1;

    • Compile the design and verify the functionality through Modelsim simulations.
    • Assign I0 to SW[0], I1 to SW[1], S0 to SW[2], and O0 to LEDR[0] using the pin planner.
    Compile the design and verify the functionality through Modelsim simulations.
    • Demonstrate the functionality on a DE10 Lite board.

    3. 4:1 Multiplexer: Write a VHDL description for the following entity instantiating the 2:1 multi-
    plexers designed previously. (Hint: Watching the Multi-Input Multiplexers video might help you.)

    entity MUX_4X1 is
    port(I : in std_logic_vector(3 downto 0); -- Inputs
    S : in std_logic_vector(1 downto 0); -- Select lines
    O0 : out std_logic); -- Output
    end MUX_4X1;

    • Compile the design and verify the functionality through Modelsim simulations.
    • Assign I to SW[0...3], S to SW[4:5], and O0 to LEDR[0] using the pin planner. Compile the
    design and verify the functionality through Modelsim simulations.
    • Demonstrate the functionality on a DE10 Lite board.

    1
    4. 1:2 Demultiplexer: Write a VHDL description for the following entity instantiating 2-input AND
    and NOT gates. (Hint: Watching the Multiplexers and Demultiplexers video might help you.)

    entity DEMUX_1X2 is
    port(I0, S0 : in std_logic; -- Inputs
    O0, O1 : out std_logic); -- Outputs
    end DEMUX_1X2;

    • Compile the design and verify the functionality through Modelsim simulations.
    • Assign I0 to SW[0], S0 to SW[1], O0 to LEDR[0], and O1 to LEDR[1] using the pin planner.
    Compile the design and verify the functionality through Modelsim simulations.
    • Demonstrate the functionality on a DE10 Lite board.

    5. 4:1 Demultiplexer: Write a VHDL description for the following entity instantiating the 1:2 demul-
    tiplexers designed previously. (Hint: You may design a 1:4 demultiplexer using 1:2 demultiplexers
    using the same way we designed a 4:1 multiplexer.)

    entity DEMUX_1X4 is
    port(I0 : in std_logic; -- Input
    S : in std_logic_vector(1 downto 0); -- Select lines
    O : out std_logic_vector(3 downto 0)); -- Outputs
    end MUX_4X1;

    • Compile the design and verify the functionality through Modelsim simulations.
    • Assign I0 to SW[0], S to SW[1:2], and O to LEDR[0...3] using the pin planner. Compile the
    design and verify the functionality through Modelsim simulations.
    • Demonstrate the functionality on a DE10 Lite board.

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