Analog & Digital VLSI

Design
EEE/ INSTR F313
BITS Pilani ANU GUPTA
Pilani Campus EEE
 BITS Pilani
Pilani Campus

Digital VLSI Design

Concepts
• Boolean Algebra, and minimization

• Gates, Combinational networks

• Logic design with PLD

• FLIP FLOPS, counters

• Synchronous sequential networks-mealy / moore machine, state

table and its reduction

• ASM- design using ASM chart, state assignment, ASM tables, ASM
realizations

• Asynchronous sequential network-analysis, primitive flow table and

its reduction, races, hazards

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Digital VLSI Design

Digital VLSI Design

• Full Automation
• Maximum benefit of scaling
• High speed
• low power
• Robustness

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Design metrics
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Design of CMOS inverter

for long channel MOSFET s
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INVERTER

STATIC CHARACTERISTICS
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VTC-- DESIGN ISSUES

Static Power Consumption

Full Logic Levels

Sharp Transition

Switching Threshold→ Noise Margins

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PRACTICAL VTC

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FIVE CRITICAL VOLTAGES

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 SWITCHING THRESHOLD
• Vth= VM= Vinv

• Output changes its state

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Noise Margins

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Noise margin vs. noise
immunity.
Question---Does having a Noise margin always guarantee Noise immunity
????

Answer---- not always. How much noise margin is required depends on

the value of total noise generated in a system.

If value of total noise generated in a system is high, large noise margins

will be required that necessitates a high Vdd.

Working at low values of Vdd will not give noise immunity to a system. Else
noise reduction techniques to be used aggressively in design.

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Noise immunity –
required Signal magnitude/ swing to tolerate noise

Binary signaling----

Required swing

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Example---Noise immunity vs. noise
margin

Binary signaling----

Required swing

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Noise sources in a digital system -example

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Cross Talk ( swing dependent noise
source) - Coupling between Lines

Cross talk from a driven line, A, to a static line, B:

Any incremental voltage waveform on A will appear on B

attenuated by the capacitive voltage divider

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Cross talk reduction using keeper
MOSFET to maintain logic ‘1’ at B

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Implementation
Resistive load inverter
Reference: Kang. S.M and Leblebici Y., “CMOS Digital
Integrated Circuits: Analysis and Design,

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VOH

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Operating region of NMOS

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VOL

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VIH
VIL

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Design for Vol
SAT. ENHANCEMENT LOAD INV.
LIN. ENHANCEMENT LOAD INV.
CMOS INVERTER

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Static characteristics

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Operating regions
VOH
VOL
VIL
VIH
V inv=V th --- switching/ logic threshold
Long channel MOSFET-- VM
Long channel VM

Here kp defined is negative as ID= - IS.

Hence I (pmos) is positive
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Symmetric CMOS inverter

 Critical voltage
• Nothing
• We can design for wide noise margins
• Set Vth= ½Vdd
 Critical voltage
• Nothing
• We can design for wide noise margins
• Set Vth= ½Vdd
Choose appropriate VM
Impact of reducing Vdd on
VTC
Vdd ≥ Vtn + │Vtp│

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Reducing supply voltage
 Hysteresis behavior
• If the power supply voltage is reduced below the
sum of the two threshold –

• The VTC will contain a region in which none of

the transistors is conducting

• The output voltage level is determine by

previous state of the output

• The VTC exhibits a hysteresis behavior

Hysteresis behavior
 Vdd < Vtn + │Vtp│

Both
transistors
off
 CMOS Schmitt trigger ckt
used to improve signal slope and noise margins
CMOS BUFFER

SCHMITT TRIGGER
Steady state power
consumption ‘Pstatic’
Pstatic =0 in CMOS inverter

As no path between Vdd and Gnd for current to flow

As for logic ‘1’, PMOS OFF

For logic’0’, NMOS off

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Design of CMOS inverter in sub-

threshold region
Subthreshold region operated
MOS

Io represents the drain current when Vgs = Vt,

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 Subthreshold region threshold voltage
Vtsub

• Sub threshold region threshold voltage ‘Vtsub’ can be

defined as the voltage Vgs at which the drain current is

equal to 0.01Io,

• n= η= subthreshold slope factor

• parameter n is process dependent.

• Typical range of values for n is 1 to 1.5.

Id -- Vgs Characteristics
Id -- Vds Characteristics
Sub-threshold current
Subthreshold region VM ,
Vi= Vo

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Available operating range from Vt, sub to Vt
 Piecewise linear VTC
Noise margins in subthreshold region
Gain of subthreshold CMOS
inverter

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 Sub-threshold swing ‘S’

Required----

A device characterized by steep subthreshold slope (1/S) exhibits a faster

transition between off (low current) and on (high current) states.
 Subthreshold slope ‘1/S’
The transition from the ON state to the OFF state is gradual.
This is more clearly when ID is plotted on a logarithmic scale

log
scale
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Design of CMOS inverter

for short channel MOSFET s
THE SHORT CHANNEL
MOSFET

Operating condition --L> xd1+xd2

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Short channel MOSFET- DIBL

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 Punch through
• This continue until the VDS reaches value that deplete the
whole remaining neutral substrate region where the two space
charge region almost touch each other.
• As the voltage is increased further the drain space charge
region expands while the space charge region of the source
junction contracts
• This means that its internal electric field decreases which
means that the source junction becomes appreciable forward
biased
• So, the net barrier height at the source is appreciably
decrease which enables electrons to flow with large number
from source to drain.
• This is the punch through current signifying the onset of punch
through breakdown.
• Long-channel MOSFET is defined as devices with width and
length long enough so that edge effects from the four sides
can be neglected
• Short channel MOSFET is defined as devices with width and
length short enough such that the edge effects can not be
neglected.
• Channel length L is comparable to the depletion widths
associated with the drain and source, or , channel depletion
width in channel region before inversion layer appears..
• Channel length L must be much greater than the sum of the
drain and source depletion widths

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Velocity saturated device
 Short channel MOS

CONSTANT 105 m/s for silicon

Short channel MOS current
equation

This model is first order and empirical

Long Channel Vs. Short Channel
SAME
Long Channel Vs. Short Channel
Id vs Vgs
Extended sat. region operation

NMOS

PMOS

vsat= 105 m/sec, VDSATn= 0.63V, VDSATp= -1 V

 Switching threshold, Vm—
short channel CMOS Inv.

 w    p V DSATp 
 p c ox   V DSATp W p c ox 
 
 l  p  l  p W c ox v
r   
p SAT

 w    n V DSATn  W c ox v
 n c ox   V DSATn W n c ox   n SAT

 l n  l n
VM--For velocity saturated device-
inverter
Long channel VM
Finding VIL, VIH
Using Piece wise linear approx.
Gain of CMOS inverter
Inverter gain
 Gain of CMOS inverter
Alternative way

Drift velocity, Vde= µVdsat/ L = 105 m/sec

gds (in saturation) is dominated by channel length

modulation. Va is early voltage

1 I D sat
 g ds  Early Voltage, Va = 7 V / um
ro LVa
Noise margins
Short channel MOSFET--Estimation of NM
USING Piecewise lin. approx.
Determine g at Vin~Vm
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Slow/ fast MOSFET---PVT variations

Variation in VM by (W/L)
Impact Of Device Variations on Vm
Effect on kR= unCox[W/L]n / upCox[W/L]p
Why design for Vth≠ ½Vdd?
Choose appropriate VM
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END
 Analog & Digital VLSI
Design
EEE/ INSTR F313
BITS Pilani ANU GUPTA
Pilani Campus EEE
 BITS Pilani
Pilani Campus

Digital VLSI Design

 BITS Pilani
Pilani Campus

Switching characteristics of CMOS

inverter
Delay Definitions- with input slope

V in

50%

tpHL tpLH
V out
90%

50%

10% t
tf tr

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Capacitive load
Cgd

Cgd at output
Cdb - under transient conditions

Equivalence factor

for abrupt junction

Clock (Charge) feedthrough
effect
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Delay calculation
method 1
CMOS Inverter Driving a Lumped Capacitance
Load
• CMOS Inverter can be viewed as a
single transistor either charging the
Cload or discharging the Cload
– Vin is assumed to switch abruptly
– If Vin switches high, the NMOS Tx
discharges Cload while the PMOS
Tx turns OFF
– If Vin switches low, the PMOS Tx
charges Cload while the NMOS Tx
turns OFF
• Cload is comprised of
– Cgate due to the gate capacitance
of receiving circuits
– Cwire of the interconnect metal
– Cparasitics of the inverter output
junctions
Switch Model of CMOS Transistor
MODEL-1
Approximate as a simple RC network where R is given as an equivalent
resistance of the NMOS and PMOS devices and C is given as the total
lumped Cload capacitance

|V G S|

R on

|V G S | > |V T |
|V G S | < | V T |
 CMOS Inverter: Transient Response
Switch model

Vout = VDD (1 – e –t / RONCL ) Vout = VDD (e –t / RONCL )

VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL
Determination of Req
In velocity saturated device
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Delay calculation
method 2
CMOS Inverter Propagation Delay
(AVERAGE CURRENT THROUGH LOAD)

V DD

t pHL = C L (V50%-VDD)
I av

V out

I av CL tpLH = C L (V50%-VOL)
Iav

V in = V DD
WHERE

Iav, HL = ½ [id(VIN=VOH, VOUT= VOH)]+ id(VIN=VOH, VOUT= V50%)]

Iav, LH = ½ [ic(VIN=VOL, VOUT= V50%)]+ ic(VIN=VOL, VOUT= VOL)]

• SIMPLE
• Drawback-----neglects variation of cap. Load during the
entire transition
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Method-3
Differential equation approach
accurate
tpHL
tpLH
Impact of Rise Time on Delay
0.35

0.3
tpHL(nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)
Input slope

or

0.25

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Real signal waveform in IC

Wire delay
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DELAY REDUCTION
Design for Performance-(speed)

• Keep Parasitic capacitances small. Reduce load

• Increase transistor sizes

– watch out for self-loading!

• Increase VDD
 Delay as a function of VDD
5.5

4.5

4
t (normalized)

3.5

3
p

2.5

1.5

1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V)
DD
Delay as a function of VDD(↑)

28

24

20
Normalized Delay

16

12

0
1.00 2.00 3.00 4.00 5.00
VDD (V)
 Device Sizing
-11
x 10
3.8

3.6 (for fixed load)

3.4

3.2
t (sec)

3
p

2.8
Self-loading effect:
2.6 Intrinsic capacitances
dominate
2.4

2.2

2
2 4 6 8 10 12 14
S
Delay as a function of CL(↓)

DELAY α CL

Delay as a function of W/L(↑)

DELAY α (W/L)-1
Delay dependence

• Input pattern dependent (111, 101, 001---)

• Placement of Inputs (based on their

arrival)

• Placement of series/ parallel blocks in ckt

schematic
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Input pattern delay dependence–
discharge delay

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Input pattern dependence of
delay– discharge delay( HL)

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Charging delay

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Input placement dependence

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 BITS Pilani
Pilani Campus

Minimization of delay—optimum size

Optimum PMOS/ NMOS
WIDTH ratio for min. delay

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Optimum PMOS/ NMOS
WIDTH ratio

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CKT. DESIGN PROBLEMS

Chip designers face a bewildering array of choices.

How large should the transistors be? (β opt)

What is the best circuit topology for a function??

How many stages of logic give least delay??

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Need of simple delay model

Delay depends on many factors—charge, discharge,

parasitic, W/L, fan in- fanout, topology

Existing delay models do not give clear indication of

contribution of each factor

Circuit designers waste too much time simulating and

tweaking circuits
53
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 BITS Pilani
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Using LE in design—
Logical effort based delay computation

54
Need of simple delay model

Circuit designers waste too much time simulating

and tweaking circuits

• High speed logic designers need to know where

time is going in their logic (how?)

• CAD engineers need to understand circuits to

build better tools (how?)

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Delay in a Logic Gate

56
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Delay contributors

τ is min. delay in that technology node. Or/ speed of a min.

sized transistor

p-intrinsic delay of the gate due to its own internal

capacitances

h—combines the effect of external load with sizes of

transistors

g– effect of circuit topology

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Delay of a gate– switch model/
logical effort model

Equivalent inverter

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D= gh+p

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 Observations
• Logical effort describes relative ability of gate
topology to deliver current [defined to be 1(best
av. of charge and discharge both for an inverter]

• Electrical effort is the ratio of output to input

capacitance
• Delay increases with electrical effort
• Delay increases ---More complex gates have
greater logical effort and parasitic delay
 Logical effort g
• The logical effort of a gate is the slope of the delay vs.
electrical effort for the gate, divided by the slope for an
inverter.

• Since delay of the gate is set by a sum of RC time constants,

the effort delay comes from the term which is the effective
resistance of the gate driving the load capacitance.

• For CMOS gates, the resistance is inversely proportional to

input capacitance, so the logical effort of a gate is:

62
One can find the LE by either making the input capacitance

of the gate equal to the inverter, and looking at the

resistance ratio,

or

by making the resistance the same and looking at the input

capacitance ratio.

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Choice Of Standard Reference
Estimation of 
CMOS Ring Oscillator Circuit
• An odd number of inverter circuits
connected serially with output
brought back to input will be astable
and can be used an an oscillator
(called a ring oscillator)
• Ring oscillators are typically used to
characterize a new technology as to
its intrinsic device performance
• Frequency and stage are related as
follows:
f = 1/T = 1/(2nP)
where n is the number of stages
and
P is the stage delay
 Ring Oscillator—COMPARING
DIFFERENT TECHNOLOGIES

v0 v1 v2 v3 v4 v5

v0 v1 v5

T=2  tp  N 2 N tp >> tf +tr

Computing Logical Effort
2 i/p nand gate--Equivalent
inverter

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Generalized expressions

Parallel transistors block-

Series transistors block-

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Computing Logical Effort

74
Logical effort of gate with
multiple inputs

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Observations

• More complex gates have larger logical efforts

Complex gates exhibit high g, greater delay

• Logical efforts grow with increase in no. of inputs

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Different gates
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STATIC CMOS GATES--

Complementary CMOS LOGIC
 Design Styles
Full Static CMOS or complementary logic
 NAND
NAND,

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XOR, XNOR

DRAWBACK

complementary signals
are required

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F = D + A. (B+C)
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Parasitic effort, P
Parasitic delay p

• It is fixed for a gate

• More complex gate—higher parasitic delay

• Ref. Pinv=1 (inverter parasitic delay )

• For other gates , parasitic delay is written in terms of pinv

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Parasitic– sum of all Diffusion
capacitances Csb, Cdb

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Parasitic diffusion
capacitances estimation

-- here β = un/ up
--here wd is the width of transistors connected to the
logic gate’s output.
Cdb, Csb are width dependent
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Parasitic delay
Example for p calculation—
NAND/ NOR GATE
Cdmin net parasitic capacitance at out put node only, size
taken into account

where wd is the width of

transistors connected to
the logic gate’s output

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-Parasitic delay calculations of 2 input
NAND gate---including all transistors
--Count no. of p/n transistors in the circuit connected to output node
. Then [p+ n transistors in gate/ Ninv) x Pinv]
--Valid Only for static cmos gate.

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Parasitic delay calculations of
2 input XOR gate

C out , xor ( 4  4  2  2)C d ,min 12C d ,min

   4  2np i nv
C out ,inv ( 2  1)C d ,min 3C d ,min

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-Parasitic delay calculations of
2 input XOR gate

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Effect of width size on
parasitic effort

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 How to compute Pinv graphically
• For inv. g=1, dabs= τ(h+pinv)
• In a given tech., plot d vs. h
• Plot would be st. line with slope τ, & intercept-
(pinv × τ)
• Pinv can be estimated after obtaining τ
• Draw similar plot for other gates
• Once τ is obtained , g and p of other gates can
be found out.
Delay equation plot

94
Calculating delay of an inverter for fanout=4
FO4 delay

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FO4 DELAY

Where FO4 = fanout of 4 inverter delay

HERE ρ = gh = 1 x 4 = 4; so d = 5τ

Thus for ρ = 4
Ď = log 4F X FO4 inverter delay
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 BITS Pilani
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Minimum Possible Parasitic Delay

Propagation delay
dependence on size

Delay will
never be
Delay reduction reduces zero

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Computing Intrinsic Transistor
Capacitance
• Intrinsic PN junction capacitance of the
driving circuit must be added to the load
capacitance Cload
• Consider the inverter example at left:
– Area and perimeter of the PMOS and
NMOS transistors are calculated from
the layout and inserted into the circuit
model
• NMOS drain area = Wn x Ddrain
• PMOS drain area = Wp x Ddrain
• NMOS drain perimeter = 2 (Wn + Ddrain)
• PMOS drain perimeter = 2 (Wp + Ddrain)
• SPICE simulations were done (bottom
left) for a fixed extrinsic load of 100fF
with increasing transistor width (Wp/Wn
= 2.75)
– Results show diminishing returns
beyond a certain Wn (say about 6 um)
due to effect of the increasing drain
capacitance on the overall capacitive
load
MINIMUM DELAY ~ ZERO DELAY

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R= Wp/Wn
Non zero value
Area x Delay ---Figure of Merit
• Increasing device width shows
diminishing returns on propagation
delay time

• Define a figure of merit as area x delay

for the inverter circuit
– Increasing device width Wn shows a
minimum in area x delay product

• Unconstrained increase in transistor

width in order to improve circuit delay
is often a poor tradeoff due to the high
cost of silicon real estate on the wafer!!
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Path delay minimization

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Design of Inverter/ CLB Chain-----

For Min. Delay
Design for Min. propagation delay A to
B?

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Path delay parameters--

G, B, H
Path Delay parameters

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Branching effort along a path

→ Used for sizing

for delay

Where BH is
 Path Delay D
• Sum of delay of all stages
Condition for min. path delay
On Differentiation:
Thus, minimum stage effort of each stage reqd. for
min. delay along a path is
We shd. choose transistor
sizes such that stage effort
is same for all blocks

Thus, minimum delay achievable along a path is

Expression of path logical
effort -- G, H

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Arithmetic mean is minimum if f1=f2, thus
Minimum Delay

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 Observations regarding F
• F depends on only topology and loading

• F is Indep. of transistor sizes

• F is unchanged if inverters are added or

removed

118
Example--- F calculation
Off path

On path

N= 2, D= 14 delay units

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Example-2, transistor sizing
1Cg = Wmin Lmin Cox

=100 Cg

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Capacitance transformation

Compute for
each stage i

Apply capacitance transformation backwards

121
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Transistor sizes

All stages shd. have same sizes

C = n W L Cox; n is a non zero no.

Each stage load = 3 (W L) Cox, L=min size

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Cz = Cy = [Wnmos + Wpmos ] Lmin Cox
Transistor sizes, un=2up
Inverter , load at the input =
[Wnmos + Wpmos ]Lmin Cox

Here Nand gate, Wnmos = 2Wmin, Wpmos = 2Wmin,

Cz= C = [Wnmos + Wpmos ]Lmin Cox
In a given tech., Cox, and L is fixed, say 1um
We take 1Cg = Wmin Lmin Cox

Given Cz = 100Cg = 100 Wmin Lmin Cox ;

then Wnmos= Wpmos
Wpmos = Wnmos = (½ )100 Wmin = 50 Wmin

124
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 EX-2 Chain Of Inverters

In Out
1 u u2 u N-1

Ci
C1
C2
CL

uopt = e
No.of stages 3
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Comparison
Switch model/ logical effort
DELAY calculation–
comparison--- example

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Optimizing no of stages in a path
for min. delay
 To find optimum N

If pinv = 0, 132
For Ň stages in chain with inverters

Best delay per stage , d = gh + pinv

d = ρ + pinv
Graphical sol
As pinv grows, adding inverters become
less advantageous

Fit a straight line

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Design of chain of Inverters— BEST NO OF STAGES
Wp, Wn of inverters--- using
capacitance transformation, N=5

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Wp, Wn of inverters--- using capacitance
transformation, N=5, ρ= 4

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For large N, delay expression-

For ρ = 4
Ď = log 4F X FO4
FO4 DELAY

Where FO4 = fanout of 4 inverter delay

HERE ρ = gh = 1 x 4 = 4; so d = 5τ

Thus for ρ = 4
Ď = log 4F X FO4 inverter delay
Wrong no of stages

141
142
 Wrong size, L=1

W 4sW 16 W

C=1 C=16
C=4s
Ρ=4
Ρ=4/ s
Ρ= 4s
Mis-sized

D = ∑gh + ∑pinv
= (4s + 4/s + 4 ) + 3 pinv (assumed constant)
= 15 units (s=1)
143
144
Power dissipation
Why worry about power?
-- Heat Dissipation
microprocessor power dissipation

DEC 21164
Why worry about power —
Portability

50

Nominal Capacity (Watt-hours / lb)

Rechargable Lithium
40
Ni-Metal Hydride
30

20 Nickel-Cadium

BATTERY 10
(40+ lbs)

0
65 70 75 80 85 90 95
Year
Multimedia Terminals Expected Battery Lifetime increase
Laptop Computers over next 5 years: 30-40%
Digital Cellular Telephony

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Where Does Power Go in
CMOS?

• STATIC POWER---NIL

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Sources of Power consumption

4 components

Steady state----

 Static power consumption

 Leakage power consumption

Switching state-----

 Short circuit power consumption

 Dynamic power consumption

BITS Pilani, Pilani Campus

• The total power in a CMOS circuit is given
by Ptotal = Pd + Psc + Ps where

 Pd is the dynamic average power (previous chart),

 Psc is the short circuit power,
 and Ps is the static power due to ratio circuit current,
junction leakage, and sub-threshold Ioff leakage current

• Short circuit current flows during the brief

transient when the pull down and pull up devices
both conduct at the same time where one (or
both) of the devices are in saturation
Subthreshold leakage power
consumption
Isub, sub-threshold current ( in off state pmos/ nmos )
Pleakage= Vdd Isub (per unit time)

BITS Pilani, Pilani Campus

Static power consumption
Dynamic energy consumption
Energy stored across
capacitor

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Dynamic power consumption-
derivation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Average Dynamic Power in CMOS
Inverter
• Average dynamic power derivation:
– On negative going input, pull-up
device charges the load
capacitance. On positive going
input, pull-down device discharges
the load into ground.
– Average power given by
Pave = (1/T)CL (dvout/dt) (Vdd – vout)dt
+ (1/T)(-1) CL (dvout/dt) vout dt
where the first integral is taken from
0 to T/2 and the second integral is
from T/2 to T
• completion of the integral yields
Pave = CL Vdd2 f where f = 1/T

• Note that the dynamic power is

independent of the typical device
parameters, but is simply a
function of power supply, load
capacitance and frequency of
the switching!
 Vdd

V in V out

CL

E nergy/transition = C L * V d d 2

Pow er = E nergy/transition * f = C L * V dd 2 * f

N ot a fu nction of transistor sizes!

N eed to reduce C L , V dd , and f to redu ce pow er.
Dynamic Power Consumption
- Revisited
Power = Energy/transition * transition rate

= CL * Vdd2 * f01

= CL * Vdd2 * P01* f
= CEFF * Vdd2 * f

Power Dissipation is Data Dependent

Function of Switching Activity

CEFF = Effective Capacitance = CL * P01

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Reduce power consumption

• Reduce Vdd
• Reduce swing at the output
• Reduce CL
• Reduce Switching activity

To keep same speed, can we reduce Vdd,

increase (w/L)?  NO
INC in W INC in CL
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Switching activity computation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Power Consumption is Data Dependent
uniform distribution of inputs

Exam ple: Static 2 Input N OR Gate

Assum e:
P(A =1) = 1/2
P(B=1) = 1/2
Then:
P(O ut=1) = 1/4
P(0  1)
= P(O ut=0).P(O ut=1)
= 3/4  1/4 = 3/16

C EFF = 3/16 * CL

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Non uniform probability of inputs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Transition Probabilities for Basic Gates
Non-uniform distribution of inputs
Example- Power consumption ------
Non uniform/ un-correlated inputs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Power consumption —Correlated signals

1 ½
 BITS Pilani
Pilani Campus

Short circuit power consumption

Short circuit power consumption

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CMOS Short-Circuit Power Dissipation
for defined capacitive load

Derivation
Short Circuit Path
Modelling

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

t1- t2, MOSFET operates in saturation

At t2, current reaches its maximum value

At this point vin=vdd/2, because inverter output waveform is

symmetrical

: Limits(t1, t2)

Conditions— Vin(t) = (Vdd/τ) t;

-- assume vin increases linearly with time

tr = tf = trf
For a balanced , symmetrical CMOS inverter with n=p= ,
and Vtn = |Vtp|, the short circuit power can be expressed
by

where tpin is the period of the input waveform and

trf is the input rise time (or fall time) tr = tf = trf

Effect of load cap on short
circuit power

P short circuit reduces, as CL increases (why?)

Reason---- output start switching (with more delay) after

input has nearly stabilized as CL increases .

So duration for which both transistor are on reduces. So

less short circuit current

BITS Pilani, Pilani Campus

Effect of Cload
Performance metric– power
economy

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Power delay product

Indicates that energy required  0 for Vdd 0  erroneous

Energy delay product=
Short channel MOSFET

Shd. Be minimum

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Energy delay product=
Long channel MOSFET

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956