This document discusses carbon nanotube field effect transistors (CNTFETs) and their modeling and simulation. It begins by introducing carbon nanotubes and describing the structure and operation of CNTFETs. It then discusses the modeling of a CNTFET using a hierarchical approach that accounts for device non-idealities. Finally, it presents Hspice simulation results of basic logic gates like NOT, NAND and NOR designed using the CNTFET model. The simulations demonstrate the feasibility of using CNTFETs as promising successors to silicon MOSFETs for next-generation integrated circuits.
This document discusses carbon nanotube field effect transistors (CNTFETs) and their modeling and simulation. It begins by introducing carbon nanotubes and describing the structure and operation of CNTFETs. It then discusses the modeling of a CNTFET using a hierarchical approach that accounts for device non-idealities. Finally, it presents Hspice simulation results of basic logic gates like NOT, NAND and NOR designed using the CNTFET model. The simulations demonstrate the feasibility of using CNTFETs as promising successors to silicon MOSFETs for next-generation integrated circuits.
This document discusses carbon nanotube field effect transistors (CNTFETs) and their modeling and simulation. It begins by introducing carbon nanotubes and describing the structure and operation of CNTFETs. It then discusses the modeling of a CNTFET using a hierarchical approach that accounts for device non-idealities. Finally, it presents Hspice simulation results of basic logic gates like NOT, NAND and NOR designed using the CNTFET model. The simulations demonstrate the feasibility of using CNTFETs as promising successors to silicon MOSFETs for next-generation integrated circuits.
This document discusses carbon nanotube field effect transistors (CNTFETs) and their modeling and simulation. It begins by introducing carbon nanotubes and describing the structure and operation of CNTFETs. It then discusses the modeling of a CNTFET using a hierarchical approach that accounts for device non-idealities. Finally, it presents Hspice simulation results of basic logic gates like NOT, NAND and NOR designed using the CNTFET model. The simulations demonstrate the feasibility of using CNTFETs as promising successors to silicon MOSFETs for next-generation integrated circuits.
ABSTRACT : Carbon Nanotube (CNT) is one of the emerging II. CARBON NANOTUBE (CNT) technologies within nano technology, that is showing high efficiency and very wide range of applications in many Carbon is a Group 14 element that resides above different streams of science and technology. The Carbon Nano silicon in the Periodic Table. Like silicon and germanium, Tube Field Effect Transistors (CNTFETs) have been explored carbon has four electrons in its valence shell. When carbon and proposed to be the promising candidate for the next atoms are arranged in crystalline structures composed of generation of integrated circuit (IC) devices. Carbon Nano hexagonal benzene-like rings, they from a number of Tube Field Effect Transistors (CNTFETs) are being widely allotropes that offer exceptional electrical properties. In their studied as possible successors to silicon MOSFETs. This paper focuses on modelling of CNTFET and using this model various semiconducting forms, these carbon nonmaterial's exhibit digital circuits are simulated. This standard model has been room-temperature mobilities over ten times greater than designed for unipolar, MOSFET-like CNTFET devices. Hspice silicon. In addition, they can be scaled to smaller feature simulations have been performed on the logic gates designed sizes than silicon while maintaining their electrical using the modelled CNTFET. properties.
Keywords - Carbon Nanotube, Carbon Nanotube Field Carbon nanotubes were discovered by S. Ijiima in 1991 [2] Effect Transistor, modelling, Logic gates. while performing some experiments on molecular structure composed of carbonium. CNTs are hollow cylinders I. INTRODUCTION composed of one or more concentric layers of carbon atoms in a honey comb lattice arrangement. It can be classified into As CMOS continues to scale deeper into the SWCNT (Single Walled Carbon Nano Tube) and MWCNT nanoscale, various device non idealities cause the I-V (Multi Walled Carbon Nano Tube) shown in Figure 1. characteristics to be substantially different from well- tempered MOSFETs. For example, the source/drain series resistance is now a significant component of the total on- resistance. Proposals of metal contacted (Schottky) source/drain UTB SOI FET also alter the I-V characteristics significantly. Novel non-Si devices such as the carbon nanotube FETs (CNFETs) operate with completely different device physics with quasi-ballistic transport in the channel and Schottky barriers at the source/drain contacts[1]. CNTFETs are novel devices that are expected to sustain the Fig.1: SWCNT and MWCNT transistor scalability while increasing its performance. One The way that graphene is rolled is described by a pair of of the major differences between CNTFETs and MOSFETs indices (n, m), which are called "chiral vector". According is that the channel of the former devices is formed by CNTs to the chiral vector of a CNT, it can be determined whether instead of silicon, which enables a higher drive current it's a metallic or semiconducting CNT as shown in Figure 2. density, due to the larger current carrier mobility in CNTs compared to bulk silicon. In this paper, section II Introduces the Carbon nanotubes, section III delves into the CNTFET and modelling aspects of CNTFET. Simulation results of NOT, NAND and NOR are in section IV. Finally, Sections V discuss the conclusion and future scope.
Fig.2: metallic and semiconducting CNT
Sameer Prabhu and Nisha Sarwade are with Department of Electrical Engineering, VJTI Mumbai, Email: [email protected], [email protected])
International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 1, July-2013. Sameer Prabhu, Dr. Nisha Sarwade 51
III. Carbon Nanotube Field Effect Transistor (CNTFET) fabrication feasibility and superior device performance of the MOSFET-like CNFET as compared to the SB-controlled A silicon wafer is covered with a thick silicon- FET. dioxide film and then fabricated gold or platinum electrodes on it using standard semiconductor manufacturing technique. A single carbon nanotube was then positioned as a channel between two electrodes which are source and drain[3]. The underlying silicon wafer, heavily doped with impurities to make it good conductor, served as gate electrode. Applying the appropriate voltage to gate the nanotube is on or off. The first carbon nanotube field-effect transistors (CNTFETs) were reported in 1998, figure 3 shows the structure of CNTFET. There are several types of Fig.4: The 3-D structure of MOSFET like CNFETs with CNTFETs, but CNTFET geometries may be grouped in two multiple channels major categories: planar and coaxial CNTFET. The complete CNFET device model[6] is implemented hierarchically in three levels. Device non- idealities are included hierarchically at each level. Level 1, models the intrinsic behaviour of MOSFET-like CNFET. The second level, denoted as includes the device non- idealities: the capacitance and resistance of the doped S/D CNT region, as well as the possible Schottky Barrier(SB) resistances of S/D contacts. The first two levels deal with only one CNT under the gate. The top level, i.e. level 3 models the interface between CNFET device and CNFET circuits. This level deals with multiple CNTs per device, and Fig.3:structure of CNTFET includes the parasitic gate capacitance and screening due to adjacent CNTs. In terms of the device operation mechanism, CNFET can be categorized as either Schottky Barrier (SB) controlled FET IV. SIMULATION RESULTS (SB-CNFET) or MOSFET-like FET[4]. The conductivity of SB-CNFET is governed by the majority carriers tunnelling This model is designed for unipolar MOSFET like through the SBs at the end contacts. The on-current and CNTFET devices, where each device may have one or thereby device performance of SB-CNFET is determined by more carbon nanotubes. 32nm technology with (19,0) the contact resistance due to the presence of tunnelling semiconducting with 1.5nm diameter CNT is used . The barriers at both or one of the source and drain contacts, supply given is 0.9V and gate and drain voltage can be instead of the channel conductance. SB-CNFET shows varied upto supply voltage. Figure 5,6 shows current ambipolar transport behaviour. On the other hand, voltage characteristics of CNT model. Gate voltage MOSFET-like CNFET exhibits unipolar behaviour by starting from zero is varied upto supply voltage with a suppressing either electron (pFET) or hole (nFET) transport variation of 0.01 x supply. Different curves for various with heavily doped source/drain. value of Vdd with a variation of 0.1 x supply is shown.
A model is developed for nanoscale devices and
circuits[5], including both CMOS technology beyond the 45 nm node and carbon nanotube field effect transistors (CNFETs), with the aim of guiding nanoscale device and circuit design. This model, provides large device speed improvement (6×for nFET and 14×for pFET) of CNFET over CMOS technology at the device level is significantly degraded(by a factor of 5 to8) by interconnect capacitance in a real circuit environment. The quasi-1D structure provides better electrostatic control over the channel region than 3D device (e.g. bulk CMOS) and 2D device(e.g. fully depleted SOI). A MOSFET-like CNFET device structure shown in Figure 4 is used for the modelling because of both the Fig 5: P channel CNT
International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 1, July-2013. Sameer Prabhu, Dr. Nisha Sarwade 52
Figure 8 shows NAND gate comprising of
CNTFETs. It comprises of driver CNTFETs coupled together in parallel between a high supply reference VDD and a series active load transistors, which is coupled to a low supply reference VSS as shown.
Fig 6: N channel CNT
Figure 7 shows an inverter comprising of P-type
and N-type CNTFETs. They are coupled together in series between a high supply voltage VDD and a low supply reference VSS, as shown.
Fig 8: Structure of CNTFET NAND Gate and its behaviour
Figure 9 shows NOR gate comprising of
CNTFETs. It comprises of driver CNTFETs coupled together in series between a high supply reference VDD and a parallel connected active load transistors, which is coupled to a low supply reference VSS, as shown.
V. CONCLUSION AND FUTURE SCOPE
Fig 7: Structure of CNTFET NOT Gate and its behaviour
International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 1, July-2013. Sameer Prabhu, Dr. Nisha Sarwade 53
This paper adequately explains the various
modelling aspects of the proposed CNTFET. The various circuits such as NOT, NAND, NOR gates designed using CNTFET. Basic functions such as AND, OR in CMOS technology are implemented by generating related inverted functions (e.g., NAND, NOR) followed by an inverter. Voltage threshold losing which occurred in passing high and low voltages in NMOSFET and PMOSFET, respectively results in such implementation. CNFET technology provides Fig 9: Structure of CNTFET NOR gate and its behaviour more efficient way to implement these functions in terms of delay, power consumption and area. Voltage threshold is REFERENCE proportional to the 1 , so increasing the diagonal of [1] C. Dwyer, M. Cheung, and D. J. Sorin, “Semi-empirical nanotube (i.e., ) results in decreasing the voltage SPICE models for carbon nanotube FET logic,” in Proc. threshold toward zero. Consequently, PCNFET and Conf. Nanotechnology, Aug. 2004, pp. 386–388. NCNFET could be utilized in pull-down and pull- up network, respectively. AND/OR circuits in CMOS [2] S. Iijima, “Helical microtubules of graphitic carbon”, technology include six transistors, whereas the number of Nature, vol.354, no.6348, Nov. 1991, pp.56-8. transistors in CNFET based circuits reduce to four. [3] Ali Keshavarzi, Arijit Raychowdhury, Juanita Kurtin, Kaushik Roy, and Vivek De, "Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits— Transient Analysis, Parasitic, and Scalability", IEEE Transactions On Electron Devices, Vol. 53, NO. 11, Nov- 2006.
[4] J. Deng, H.-S. P. Wong, “A Compact SPICE Model for
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[5] Fabien Pregaldiny et.al.,―Compact Modelling and
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International Journal of Emerging Trends in Electrical and Electronics (IJETEE – ISSN: 2320-9569) Vol. 5, Issue. 1, July-2013.
