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Fpga

Programmable logic devices include PLDs, CPLDs, and FPGAs. PLDs have limited interconnect programmability and include PALs and PLAs. CPLDs such as MAX7000 have macrocells and a programmable interconnect array. FPGAs like Stratix II are more complex and flexible but have complicated interconnects. They are programmed using SRAM and implemented using look-up tables and configurable routing.

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100 views

Fpga

Programmable logic devices include PLDs, CPLDs, and FPGAs. PLDs have limited interconnect programmability and include PALs and PLAs. CPLDs such as MAX7000 have macrocells and a programmable interconnect array. FPGAs like Stratix II are more complex and flexible but have complicated interconnects. They are programmed using SRAM and implemented using look-up tables and configurable routing.

Uploaded by

sowmiyaraj
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Programmable Logic

Programmable logic
Mask programmable gate arrays and standard cell designs are programmable
the user programs the connection patterns High NRE, not reprogrammable, highvolume applications

Programmable logic usually refers to devices with less NRE and more flexible programming techniques

Programmable Logic Devices (PLDs)


PALs PLAs

PROM Complex Programmable Logic Devices (CPLDs) and Field Programmable Logic Devices (FPGAs)

Standard Logic

Simple PLDs

CPLDs FPGAs

Gate Array Standard Cell

Full Custom VLSI

Increasing NRE Cost and Development Time Increasing density, speed and complexity

Simple PLDs
Devices that can be programmed to implement a wide variety of combinational circuits Typically two layers: an AND plane and an OR plane
Can implement sum of products functions

Simple PLDs

Programmable ROM
Programmable OR plane selects from all possible minterms Decoder maps input pattern to appropriate minterm Sum of minterms realisation

PLA Devices
Programmable logic array device has both a programmable AND plane and a programmable OR plane Flexible, efficient implementation of sum of products combinatorial circuits

PAL Devices
Programmable array logic (PAL) has programmable AND terms and fixed OR plane Simpler, better performance than PLA

PLDs have limited interconnect programmability Typically require a special-purpose programmer to program fusible connections Field-programmable PLDs incorporate EEPROM style transistors to form/ program connections in system Limited size and complexity

Some PAL devices have additional circuitry in addition to or OR gate for each output (a macrocell)
can register the outputs feed outputs back as inputs

CPLDs
A large scale device consisting of arrays of simple PLD macrocells.
Sum of products Registers to store cell output Clock and control logic Local connections to neighbouring blocks

Blocks are interconnected through programmable interconnections

Advantage over PLDs


Large number inputs without excessive increase in area (linear versus exponential increase with PLD) Wide fan-in on input AND gates 100% connectivity between macro cells allowing complex multilevel circuits

Electrically reconfigurable (SRAM transmission gates, EEPROM) or OTP

Atmel ATF1500

Max 7000 CPLD


Altera EEPROM floating gate transistor based CPLD

Main blocks
Logic Array Blocks (LAB)
36 inputs, 16 output, 16 macrocells with flip-flop and combinational logic

Programmable Interconnect Array (PIA)


Global bus connecting LABs and IOBs Full connectivity with predictable timing Less dense connectivity than FPGA

I/O blocks
Connection/config of pins with PIA and LABs

Altera MAX7000

LAB consist of macrocells Each macrocell


Has logic array in form of programmable mini-PAL forming sum-of-products expressions Up to 36 inputs from PIA plus 16 parallel and shared logic expander inputs from neighboring macrocells Flip-flop with programmable input, clocking

Altera 10K Series


Look up table (LUT) based CPLD devices very similar to FPGAs Programmable connection based on SRAM controlled transmission gates On chip RAM, higher density, configurability and speed offer more design possibilities than MAX7000

Altera Flex 10K

Stratix II

Field Programmable Gate Arrays (FPGA)


CPLDs
Predictible timing, fewer but large cells Simpler interconnect, place and route easier

FPGAs
More complex, register rich Flexible but complicated interconnections Performance more dependent on routing

FPGAs
FPGAs are modeled after Mask Programmable Gate Arrays (MPGAs) Look-up table based logic elements Design to silicon in minutes (or less) Dominant technology is SRAM based programming
volatile! EEPROM and anti-fuse technologies also exist

Architecture
Array of programmable logic elements implementing simple sequential and combinational functions Fixed but programmable interconnection channels to route signals Configurable I/O pin interfaces

Modern devices include


RAM blocks low skew clock distribution and PLLs (critical fo high speed clocks) flexible I/O standards (for common interfaces)

RAM based FPGAs programmed by downloading configuration into CMOS RAM Downloaded from host or from associated PROM Highly reconfigurable but startup time to reconfigure
Short programming time facilitates rapidprototyping

Bit contents in RAM control state of CMOS trandmission gates


Program logic elements (functional units) Configure I/O pin function Establish connectivity between logic elements

Tradeoff between complexity of logic elements and routing resources and wasted cell array/logic elements

FPGA/CPLD resources
Large designs can be limited by various resources
Gates (Marketted as equivalent useable gates) Interconnects I/O Pins Memory

Synchronous designs rely on careful low-skew clock distribution

Design Flow
Large chips have too many gates for schematic capture Hardware description language (HDL) based approaches dominate Verilog and VHDL most widely supported and used Designs are automatically synthesised from high-level HDL descriptions

IP Cores
Many vendors provide library and macros or predesigned cores for common operations (multiplexors, ALUs, multipliers ) More specialised IP available: network controllers, serial interfaces High end FPGA have significant power and can include capable processors (e.g. NIOS)

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