Power Management Texas Instruments Incorporated

A low-cost, non-isolated AC/DC buck

converter with no transformer
By Jeff Falin, Senior Applications Engineer,
and Dave Parks, Senior Member, Technical Staff
Introduction The basic buck converter
Off-line equipment such as a smart meter or a power The TPS64203 is a hysteretic buck controller designed to
monitor has electronics that require non-isolated DC power drive a high-side pFET and has minimum turn-on and
under 10 W. Until recently, the only practical options for minimum turn-off switching-time requirements. Unlike a
providing a low-power DC power rail from an AC source traditional hysteretic converter with a switching frequency
were to use an extremely inefficient, unregulated resistive/ that varies with load current, the minimum on and off
capacitive divider following the rectifier, or a flyback DC/DC times essentially clamp the switching frequency when the
converter that was cumbersome to design. Advances in converter begins to run in continuous-conduction mode at
MOSFET technology and an innovative gate-drive circuit high output-power levels. Other members of the TPS6420x
for a hysteretic buck controller have resulted in an ultra­ family actively avoid switching in the audible frequency
low-cost DC power rail. range, effectively having a maximum on and off time.
Figure 1 shows the entire converter. The rectifier circuit Originally designed for battery-powered applications, the
uses a standard, fast-switching rectifier diode bridge (D1) TPS6420x family has an input-voltage range of 1.8 V to
and an LC filter (L1 and C2). The remaining components 6.5 V and very low quiescent current (35 µA maximum).
will be explained in more detail. During start-up, the TPS64203 is biased by Zener diode

Figure 1. AC/DC buck-converter circuit

L1
470 µH VIN
1 2
+
C5
D1 C2 +
R5 0.1 µF
HD04 2.2 µF Q2
200  400 V
AC AC 3904 C4
0.1 µF
C1
120 to 0.01 µF
230 VRMS 400 V S
–
Q3 G FQD2P40
3906 Q4
F1 R2 L2
D 470 µH
1-A Fuse 200 k

D3 D5 C6 + VOUT
R3 ES1G 68 µF 5 VDC at
200 k BAS16 D4 750 mA

D2 BAT54
5.1 V
Q1 R6
FCX658ATA
3.74 k
U1 R4
TPS64203DBV
66.5 
1 EN SW 6
2 GND VIN 5
3 FB ISENSE 4 R1
C3 1.21 k
1 µF

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Texas Instruments Incorporated Power Management

D2 and high-voltage resistors R2 and R3. After the 5-V rail inductance at high line, assuming that K = 0.4 for the
is up, Schottky diode D4 allows the 5-V output rail to inductor’s ripple-current factor.
power the controller. ( VIN − VOUT ) × ton(min) ( 230 V − 5 V ) × 0.65 µs
Power FET Q4 must have a high enough VDS voltage L= =
rating not to be damaged by the input voltage, and a high ∆I L 0.4 × 0.750 A (1)
enough current rating to handle IPMOS(RMS) = IOUT(max) × = 488 µH → 470 µH
√Dmax. It must also be in a package capable of dissipating
PCond = (IOUT(max) × √Dmax)2 × RDS(on). Traditionally, high- The relatively high K value minimizes inductor size and
voltage p-channel FETs have had a gate capacitance or proves to be acceptable because the steady-state output-
turn-on/off times that were too large, a drain-to-source ripple requirement for this particular application was no
resistance (RDS(on)) that was too high, a threshold voltage larger than 0.02 × VOUT , or 100 mVPP at high load. Being
(VTH) that was too large, and/or have simply been too hysteretic, the TPS6420x controllers typically work best
expensive to make a circuit like the one in Figure 1 practi- with some ripple on the output voltage. An output capaci-
cal (i.e., efficient enough relative to cost). Since the high tor with at least 50-mΩ ESR is recommended and would
line of 230 VRMS + 10% tolerance comes from the 350-VPK produce a ripple voltage of ∆VPP(ESR) = ∆IL × RESR, which
AC line, the FET, filter, and input capacitors need to be typically far exceeds the capacitive component of the volt-
rated for 400 V. age ripple. The measured ripple for this application is
The FQD2P40 is a relatively new, 400-V p-channel shown in Figure 2.
MOSFET. With an RDS(on) of 5.0 Ω from a 10-V gate drive Because the TPS64203 is hysteretic, its output voltage
and a total gate charge of less than 13 nC, this FET can will have higher ripple at lower output power when it is
easily be switched by the controller—with relatively fewer running in pulsed-frequency mode. The measured operat-
conductive and switching losses than older FETs—with the ing frequency of the converter is approximately 32 kHz,
help of the innovative drive circuit consisting of Q2, Q3, C4, which agrees with the predicted value of
and D3. The converter’s rectifying Schottky diode, D5, is Dmin 5 V/250 V
selected with a voltage rating capable of blocking the input fSW = = = 31 kHz.
ton(min) 0.65 µs
voltage, a peak-current rating slightly higher than the out-
put voltage, and an average current rating of IDiode(Avg) =
(1 – D) × IOUT(max). With a Dmax of 5 V/120 V = 0.04 and How the drive circuit works
such low output power, the peak-current rating and the Bipolar transistor Q1 and resistors R4 and R5 form a
power dissipation are not a concern in either switch. constant-current-driven level shifter that allows the low-
The buck power stage’s LC filter is designed as explained voltage TPS64203 controller to operate the discrete gate-
in the TPS6420x family data sheet. With the input voltage drive circuit formed by Q2 and Q3. Like the controller, the
being much larger than the output voltage, all of the level shifter is powered by Zener diode D2 at start-up and
TPS6420x controllers will run in minimum-on-time mode. the regulated 5-V rail, through Schottky diode D4, after
Equation 1 computes the recommended buck-converter start-up. Power FET Q4’s gate must be overdriven just
enough to provide the required output current with an
acceptable RDS(on). Too much drive increases switching
Figure 2. Output ripple at VIN = 250 VDC and
losses, while too little increases conduction losses. From a
IOUT = 500 mA
review of the FQD2P40 data sheet and some trial and
error, VGS ≅ 12 V was selected.
Capacitor C4 and diode D3 are critical to the drive
circuit’s functionality. Resistor R5 is selected to set the
gate-drive level of 12 V below the voltage at the rectifier’s
output. Diode D3 clamps capacitor C4 to this level. Specif­
Output Ripple (100 mV/div)

ically, when U1’s switch pin outputs a low signal to turn on

the power FET, the signal gets level shifted to the base of
Q3. Transistor Q3 turns on and quickly charges Q4’s gate-
to-source capacitance, CGS, to 12 V. Without C4 and D3,
turning off Q4 would have required Q3 to be an expensive,
high-voltage bipolar transistor with its drain tied to ground.
When U1’s switch pin outputs a high signal to turn off the
power FET, the signal gets level shifted to the base of Q2.
Q2 turns on, effectively tying Q4’s gate to the input voltage.
It is important to note that without capacitor C4 acting as
a local power supply, transistors Q2 and Q3 would not be
Time (5 µs/div)
able to provide the fast current spikes necessary to quickly
—and therefore efficiently—pull up or pull down Q4’s gate

17

Analog Applications Journal 4Q 2010 www.ti.com/aaj High-Performance Analog Products

 Power Management Texas Instruments Incorporated

capacitance. Also, the level shifter’s current, ILS, set by R4,

Figure 3. Q4 gate and drain voltages during
must be high enough to move Q4’s gate charge, QGate,
one switching cycle
during the ton(min). That is,
I LS = VZ( D 4 ) − VBE QGate
>> .
R4 ton(min)

Capacitor C4 is sized to be much larger than Q4’s gate

capacitance, but it must be small enough that it can be Q4 Gate Voltage
(5 V/div)
recharged during the shorter of the controller’s minimum
on and off times. Figure 3 shows the gate and drain turn-
on/off times during one switching cycle with an input
voltage of 300 V and a 500-mA load. Measured conversion Q4 Drain Voltage
(100 V/div)
efficiency is shown in Table 1.
Current limit and soft start
In low-voltage applications, the TPS6420x uses a high-
side current-limit circuit to compare the drop across
a current-sense resistor, placed between the VIN and
ISENSE pins, to a reference voltage. If the voltage across Time (0.1 µs/div)
the sense resistor exceeds that voltage, the circuit turns
off the switch, thereby implementing a pulse-by-pulse
current limit. In a high-voltage application, the current-
limit circuit cannot be used without overvoltage on the Table 1. Measured conversion efficiency
ISENSE pin, so the ISENSE pin is tied high to VIN. There­
VIN IIN PIN IOUT VOUT POUT EFFICIENCY
fore, the circuit in Figure 1 does not have a current limit.
(V) (A) (W) (A) (V) (W) (%)
A high-side series fuse is recommended to provide short-
circuit protection. 100 0.043 4.3 0.5 5.023 2.5115 58.40698
In typical applications during start-up, the TPS64203’s 200 0.021 4.2 0.5 5.023 2.5115 59.79762
current-limit value is slowly ramped up to provide a 300 0.015 4.5 0.5 5.023 2.5115 55.81111
current-limited, controlled soft start. In this application, 100 0.066 6.6 0.75 5.023 3.76725 57.07955
the current-limit circuit and therefore the soft start are
200 0.031 6.2 0.75 5.023 3.76725 60.7621
disabled; therefore, the start-up inrush current may be
large and the output voltage may overshoot slightly, as 300 0.022 6.6 0.75 5.023 3.76725 57.07955
shown in Figure 4.
Conclusion
Figure 4. Start-up into a 10-W load with
Using a level shifter and gate driver with a localized power VIN = 300 V
source allows the use of a low-voltage buck controller to
provide a DC voltage from an AC power source. Conversion
efficiency near 60% can be achieved by using a simple
circuit and no transformer. This circuit can also be used
for DC/DC conversion where the input DC voltage is above
the maximum rating of the TPS6420x.
Output Voltage (1 V/div)

Related Web sites

power.ti.com
www.ti.com/sc/device/TPS64200

Time (1 ms/div)

18

High-Performance Analog Products www.ti.com/aaj 4Q 2010 Analog Applications Journal

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