DIGITAL CIRCUIT DESIGN

NAME OF FACULTY: Dr.Gurpreet STUDENT NAME: Ayushi shree

DESIGNATION: ASSISTANT PROFESSOR
INSITUTE: AIIT COURSE: BSC.IT

AMITY INSTITUTE OF INFORMATION TECHONOLOGY

AMITY UNIVERSITY UTTAR PRADESH,NOIDA
SESSION: 2021-2024
 DIGITAL CIRCUIT DESIGN
PRACTICAL RECORD
PAPER CODE:
Name of the student: Aayushi shree
Course: BSC.IT

PRACTICAL DETAILS
Date of Date of
S.No. Experiment Name Remarks
Performance Checking
1 Introduction to Logisim 23/09/2021
Introduction to Logic Gates 24/09/2021
1a To design Half Adder using Logic Gates and 30/09/2021
verify the Truth Table

1b To design Full Adder using Gates and Verify their Truth 01/10/2021
Tables.

1c To design Half Subtractor using Logic Gates and verify 7/10/2021

the Truth Table
1d To design Full Subtractor using Logic Gates and verify 8/10/2021
the Truth Table
2a To study and verify the given Boolean expression using 14/10/2021
logic gates
2b To implement Boolean functions using logic gates in 15/10/2021
both SOP and POS forms
3a To design and verify multiplexer circuits (2:1) 28/10/2021
3b To design and verify multiplexer circuits (4:1) 28/10/201
3c To design and verify multiplexer circuits (8:1) 28/10/2021
4 To study and verify a 2-bit comparator using logic 12/11/2021
gates
5 To study and verify a BSD to 7 segment using logic 12/11/2021
gates.

6 To study and verify an Excess-3 converter using 18 /11/2021

logic gates
7 To study and verify a Gray Code converter using 18/11/2021
logic gates.
Date:23/09/2021
Introduction to Logisim

Logisim is an educational tool for designing and simulating digital logic circuits. With
the capacity to build larger circuits from smaller subcircuits, and to draw bundles of
wires with a single mouse drag, Logisim can be used (and is used) to design and
simulate entire CPUs for educational purposes.

THIS IS THE SCREEN OF LOGISIM

 Introduction to Logic Gates
General Description. This device contains three independent gates each of which
performs the logic AND function.

AIM: To stimulate all logic gates and verify their truth tables

Software Used: Logisim

Theory: A logic gate is a device that acts as a building block for digital
circuits. In a circuit, logic gates will make decisions based on a
combination of digital signals coming from its inputs. Most logic gates
have two inputs and one output. Logic gates are based on Boolean
algebra.
 AND GATES

1. AND Gate Schematic:

2.
The AND gate is so named because, if 0 is called "false" and 1 is called "true,"
the gate acts in the same way as the logical "and" operator. The following
illustration and table show the circuit symbol and logic combinations for an
AND gate. (In the symbol, the input terminals are at left and the output
terminal is at right.) The output is "true" when both inputs are "true."
Otherwise, the output is "false." In other words, the output is 1 only when both
inputs one AND two are 1.

THIS IS AND GATE

Equation and Truth Table:

 OR gate

This is OR GATE

The OR gate gets its name from the fact that it behaves after the fashion of
the logical inclusive "or." The output is "true" if either or both of the inputs are
"true." If both inputs are "false," then the output is "false." In other words, for
the output to be 1, at least input one OR two must be 1.

Z=X.Y

Equation and Truth Table:

 Not gate
A logical inverter, sometimes called a NOT gate to differentiate it from other
types of electronic inverter devices, has only one input. It reverses the logic
state. If the input is 1, then the output is 0. If the input is 0, then the output is
1.

THIS IS NOT GATE

Equation and Truth Table:

 NAND GATE

The NAND gate operates as an AND gate followed by a NOT gate. It acts in
the manner of the logical operation "and" followed by negation. The output is
"false" if both inputs are "true." Otherwise, the output is "true."

THIS IS NAND GATE

Equation and Truth Table:

NOR GATE
The NOR gate is a combination OR gate followed by an inverter. Its output is
"true" if both inputs are "false." Otherwise, the output is "false."

This is nor gate

Equation and Truth Table:

XOR GATE

The XOR (exclusive-OR) gate acts in the same way as the logical "either/or."
The output is "true" if either, but not both, of the inputs are "true." The output is
"false" if both inputs are "false" or if both inputs are "true." Another way of
looking at this circuit is to observe that the output is 1 if the inputs are
different, but 0 if the inputs are the same.
 This is xor gate

Equation and Truth Table:

XNOR GATE

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an

inverter. Its output is "true" if the inputs are the same, and "false" if the inputs
are different.
 This is xnor gate

EQUATION AND TRUTH TABLE:

DATE: 25/09/2020
PRACTICAL – 1A

AIM: To design half adder using gates and verify their truth tables.
SOFTWARE USED: Logisim
THEORY
What is an Adder?
An adder is a digital logic circuit in electronics that is extensively used for the addition
of numbers. In many computers and other types of processors, adders are even used to
calculate addresses and related activities and calculate table indices in the ALU and
even utilized in other parts of the processors. These can be built for many numerical
representations like excess-3 or binary coded decimal. Adders are basically classified
into two types: Half Adder and Full Adder.

HALF ADDER
A half adder is a type of adder, an electronic circuit that performs the
addition of numbers. The half adder is able to add two single binary digits
and provide the output plus a carry value. It has two inputs, called A and B,
and two outputs S (sum) and C (carry). The common representation uses a
XOR logic gate and an AND logic gate.

1. EQUATIONS

SUM (X) = A XOR B = A ⊕ B

CARRY (Y) = A AND B = A.B

CIRCUIT DIAGRAMS: HALF-ADDER

• Making Half-Adder using AND-OR gates
 • Making a Half-Adder using XOR gate

TRUTH TABLE
DATE: 01/10/2020
PRACTICAL – 1B

AIM: To design Full Adder using gates and verify their truth tables.

SOFTWARE USED: Logisim

THEORY

1. FULL ADDER:
Full Adder is the adder which adds three inputs and produces two outputs. The first two
inputs are A and B, and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.
A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another.

1. EQUATIONS:

Logical Expression for SUM

= A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN

= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
= (1,2,4,7)

Logical Expression for C-OUT

= A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN
= (3,5,6,7)
CIRCUIT DIAGRAM: HALF-ADDER
• Making Full Adder using NAND gate

• Making Full Adder using XOR gate

1. TRUTH TABLE:
DATE: 07/10/2020
PRACTICAL – 1C

AIM: To design Half Subtractor using gates and verify their truth tables.
SOFTWARE USED: Logisim
THEORY

1. HALF SUBTRACTOR:
The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It
has two inputs, A (minuend) and B (subtrahend) and two outputs Difference and Borrow.

1. EQUATIONS:

Logical Expression for Half Adder

Difference = A ⊕ B
Borrow = A' B

CIRCUIT DIAGRAM: HALF-SUBRTRACTOR

• Making Half Subtractor

1. TRUTH TABLE
DATE: 08/10/2020
PRACTICAL – 1D

AIM: To design Full Subtractor using gates and verify their truth tables.
SOFTWARE USED: Logisim
CIRCUIT:

1. FULL SUBTRACTOR:
A full subtractor is a combinational circuit that performs subtraction involving three bits, namely
A (minuend), B (subtrahend), and Bin (borrow-in). It accepts three inputs: A (minuend), B
(subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout
(borrow out).

1. EQUATIONS:

Logical Expression for Full Subtractor:

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin

CIRCUIT DIAGRAM: FULL-SUBRTRACTOR

SCHEMATIC:
• Making Full Subtractor
 • Making Full Subtractor using NAND Gate

• Making Full Subtractor using NOR gate

2. TRUTH TABLE:

INPUT OUTPUT
A B C D =A ⊕B ⊕C B = AB + BC + AC
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
DATE: 14/10/2020
PRACTICAL – 2A

AIM: To study and verify the given Boolean expression: Y = (A+BC) (B+C’A) using logic gates.
SOFTWARE USED: Logisim
THEORY:
1. Write the truth table
2. Simplify the expression
3. Draw the circuit for given expression and simplified expression and compare the
Logisim generated truth table
1. BOOLEAN EXPRESSION:
Y=(A+BC) (B+C’A)

EQUATIONS:
Y=(A+BC) (B+C’A)
A(B+CA) + BC(B+C’A)
AB + AC’A + BCB + BCC’A
AB + AC’ + BC + BCC’A
AB + AC’ + BC + 0
ABB + AC’ + BC

CIRCRUITDIAGRAM: HALF-ADDER
Y= (A + BC) (B+C’A)
 Y=AB + AC’ + BC

1. TRUTH TABLE:
A B C BC C’A A+BC B+C’A (A+BC)(B+C’A)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 1 0
0 1 1 1 0 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 0 1 0 0
1 1 0 0 1 1 1 1
1 1 1 1 0 1 1 1
DATE: 15/10/2020
PRACTICAL – 2B

AIM: To implement Boolean functions using logic gates in both SOP and POS forms

SOFTWARE USED: Logisim

THEORY:
The sum of product or SOP form is represented by using basic logic gates: AND gate and OR gate. The
SOP form implementation will have AND gates at its input side and as the output of the function is the
sum of all product terms, it has an OR gate at its output side.
An important to remember is that we use NOT gate to represent the inverse or complement of the
variables.

1. BOOLEAN EXPRESSION:
• SOP: Y = ABC + ABC’ + A’BC’
• POS: Y = (A+B+C).(A’+B’+C).(A+B’+C)

1. EQUATIONS:
Y=(A+BC) (B+C’A)
A(B+CA) + BC(B+C’A)
AB + AC’A + BCB + BCC’A
AB + AC’ + BC + BCC’A
AB + AC’ + BC + 0
ABB + AC’ + BC
CIRCRUIT DIAGRAM:
SOP
POS

1. TRUTH TABLE:

• SOP
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

• POS
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
DATE: 28/10/2020
PRACTICAL – 3A

AIM: To design and verify multiplexer circuits. (2:1)

SOFTWARE USED: Logisim
THEORY
A multiplexer (MUX) is a device that can receive multiple input signals and synthesize a single
output signal in a recoverable manner for each input signal. It is also an integrated system that
usually contains a certain number of data inputs and a single output. Here, as a beginner, what
multiplexer really is in the CPU?
Multiplexer means many into one. In electronics, a multiplexer (MUX) is a logic gates circuit
that employed to fetch a bit of data from computer memory at a given address. What’s more, a
computer processor has several multiplexers to control the data and address buses. In other
words, it is a special circuit device that selects one of n inputs and provides it on output.
Multiplexer technology may follow one of the following principles, such as: TDM, FDM, CDM
or WDM. It is also applied to software operations, such as the simultaneous transmission of
multi-threaded information streams to equipment or programs.

1. EQUATIONS:

Logical Expression for Multiplexers

Q = A.I1 + A.I0

1. TRUTH TABLE:

INPUTS OUTPUTS
I0 Y
0 I0
1 I1
DATE: 28/10/2020
PRACTICAL – 3B

AIM: To design and verify multiplexer circuits. (4:1)

SOFTWARE USED: Logisim
THEORY
A multiplexer (MUX) is a device that can receive multiple input signals and synthesize a single
output signal in a recoverable manner for each input signal. It is also an integrated system that
usually contains a certain number of data inputs and a single output. Here, as a beginner, what
multiplexer really is in the CPU?
Multiplexer means many into one. In electronics, a multiplexer (MUX) is a logic gates circuit
that employed to fetch a bit of data from computer memory at a given address. What’s more, a
computer processor has several multiplexers to control the data and address buses. In other
words, it is a special circuit device that selects one of n inputs and provides it on output.
Multiplexer technology may follow one of the following principles, such as: TDM, FDM, CDM
or WDM. It is also applied to software operations, such as the simultaneous transmission of
multi-threaded information streams to equipment or programs.

1. EQUATIONS:
2. Logical Expression for Multiplexers
3. Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1
4.
5. CIRCUIT DIAGRAM: MULTIPLEXER

1. TRUTH TABLE:

INPUTS OUTPUTS
I1 I0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
DATE: 28/10/2020
PRACTICAL – 3C

AIM: To design and verify multiplexer circuits. (8:1)

SOFTWARE USED: Logisim
THEORY
A multiplexer (MUX) is a device that can receive multiple input signals and synthesize a single
output signal in a recoverable manner for each input signal. It is also an integrated system that
usually contains a certain number of data inputs and a single output. Here, as a beginner, what
multiplexer really is in the CPU.

1. EQUATIONS:
2.
Logical Expression for Multiplexers

Y=S0'. S1'. S2'. A0+S0.S1'. S2'. A1+S0'. S1.S2'. A2+S0.S1.S2'. A3+S0'. S1'. S2 A4+S0.S1'. S2 A5+S0'. S1.
S2.A6+S0.S1. S3.A7

2. CIRCUIT DIAGRAM: MULTIPLEXER

1. TRUTH TABLE:

INPUTS OUTPUTS
S2 S1 S0 Y
0 0 0 A0
0 0 1 A1
0 1 0 A2
0 1 1 A3
1 0 0 A4
1 0 1 A5
1 1 0 A6
1 1 1 A7
Date:- 12/11/2021
PRACTICAL – 4
AIM: To study and verify a 2-bit comparator using logic gates
SOFTWARE USED: Logisim
THEORY
A comparator used to compare two binary numbers for each of two bits is called a 2-bit
magnitude comparator. It consists of four inputs and three outputs to generate less than, equal
to and greater than between two binary numbers.

The truth table for a 2-bit comparator is given below:

input output
A1 A0 B1 B0 A>B A<B A=B
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1

From the above truth table logical expressions for each output can be expressed as follows:
A > B : A1B1’ + A0B1’B0’ + A1A0B0’
A = B : A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A < B : A1’B1 + A0’B1B0 + A1’A0’B0
By using these Boolean expressions, we can implement a logic circuit for this comparator as
given below:

Truth table:
DATE:- 12/11/2021
PRACTICLE 2

AIM: - To study and verify a BSD to 7 segment using logic gates.

SOFTWARE USED: - Logisim.

THEORY: -

BCD to 7-segment display decoder is a special decoder which can convert binary coded decimals
into another form which can be easily displayed through a 7-segment display.

CIRCUIT: -

TRUTH TABLE: -
DATE: - 18/11/2021
PRACTICAL – 5
AIM: - To study and verify an Excess-3 converter using logic gates

SOFTWARE USED: - Logisim.

THEORY: -

Excess-3 binary code is an unweighted self-complementary BCD code.

Self-Complementary property means that the 1’s complement of an excess-3 number is the
excess-3 code of the 9’s complement of the corresponding decimal number. This property is
useful since a decimal number can be nines complemented (for subtraction) as easily as a binary
number can be ones complemented; just by inverting all bits.

For example, the excess-3 code for 3(0011) is 0110 and to find the excess-3 code of the
complement of 3, we just need to find the 1’s complement of 0110 -> 1001, which is also the
excess-3 code for the 9’s complement of 3 -> (9-3) = 6.

CIRCUIT: -

TRUTH TABLE: -
DATE: - 18/11/2021
PRACTICAL – 6

AIM: - To study and verify a Gray Code converter using logic gates.

SOFTWARE USED: - Logisim.

THEORY: -

Gray Code system is a binary number system in which every successive pair of numbers differs in
only one bit. It is used in applications in which the normal sequence of binary numbers generated
by the hardware may produce an error or ambiguity during the transition from one number to the
next.

For example, the states of a system may change from 3(011) to 4(100) as- 011 — 001 — 101 —
100. Therefore, there is a high chance of a wrong state being read while the system changes from
the initial state to the final state.
This could have serious consequences for the machine using the information. The Gray code
eliminates this problem since only one bit changes its value during any transition between two
numbers.

CIRCUIT: -
TRUTH TABLE: -
Date:-03-12-2021
PRACTICAL – 6

AIM: -To verify the truth table of RS, D, JK and T flip-flop?

SOFTWARE USED: - Logisim.

THEORY: - The basic NAND gate RS flip flop circuit is used to store the data and thus
provides feedback from both of its outputs again back to its inputs. The RS flip flop actually has
three inputs, SET, RESET and its current output Q relating to its current state as shown in figure
below.
Output:-
D flip flop
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip
flop by connecting the R input through an inverter, and the S input is connected directly
to data input. The modified clocked SR flip-flop is known as D-flip-flop and is shown
below. From the truth table of SR flip-flop we see that the output of the SR flip-flop is in
unpredictable state when the inputs are same and high. In many practical applications,
these input conditions are not required. These input conditions can be avoided by
making them complement of each other.