TCM3105DWL, TCM3105JE, TCM3105JL

TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

• Single-Chip Frequency-Shift-Keying (FSK) J OR N PACKAGE

Modem (TOP VIEW)

• Meet Both Bell 202 and CCITT V23

VDD 1 16 OSC2
Specifications
•
CLK 2 15 OSC1
Transmit Modulation at 75, 150, 600, and
CDT 3 14 TXD
1200 Baud
RXA 4 13 TXR1
• Receive Demodulation at 5, 75, 150, 600, TRS 5 12 TXR2
and 1200 Baud NC 6 11 TXA
• Half-Duplex Operation Up to 1200 Baud RXB 7 10 CDL
Transmit and Receive RXD 8 9 VCC
• Full-Duplex Operation Up to 1200 Baud
Transmit and 150 Baud Receive DW PACKAGE
• On-Chip Group Equalization and (TOP VIEW)
Transmit/Receive Filtering
• Carrier-Detect-Level Adjustment and VDD 1 24 OSC2
Carrier-Fail Output CLK 2 23 OSC1
• Single 5-V Power Supply CDT 3 22 TXD

•
NC 4 21 NC
Low Power Consumption
RXA 5 20 TXR1
• Reliable CMOS Silicon-Gate Technology NC 6 19 NC
TRS 7 18 NC
description NC 8 17 TXR2
The TCM3105 is a single-chip asynchronous RXT 9 16 TXA
frequency-shift-keying (FSK) voice-band modem NC 10 15 NC
that uses silicon-gate CMOS technology to RXB 11 14 CDL
implement a switched-capacitor architecture. It is RXD 12 13 VSS
pin selectable (TXR1, TXR2, and TRS) for a wide
range of transmit /receive baud rates and is NC – No internal connection
compatible with the applicable BELL 202 or
D package are available taped and reeled. Add the R suffix to
CCITT V23 standards. Operation is fully device type (e.g., YCM3105DWLR).
reversible, thereby allowing both forward and
backward channels to be used simultaneously.
The transmitter is a programmable frequency synthesizer that provides two output frequencies (on TXA),
representing the marks and spaces of the digital signal present on TXD.
The receive section is responsible for the demodulation of the analog signal appearing at the RXA input and
is based on the principle of frequency-to-voltage conversion. This section contains a group delay equalizer (to
correct phase distortion), automatic gain control, carrier-detect-level adjustment, and bias-distortion
adjustment, thereby optimizing performance and giving the lowest possible bit error rate.
Carrier-detect information is given to the system by means of the carrier-detect circuits, which set a flag on the
CDT output if the level of received in-band energy falls below a value set on the CDL input for a specified
minimum duration.
The TCM3105JE and TCM3105NE are characterized for operation from – 40°C to 85°C.The TCM3105DWL,
TCM3105JL, and TCM3105NL are characterized for operation from 0°C to 70°C.

Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCTION DATA information is current as of publication date. Copyright  1994, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

Terminal Functions
TERMINAL
NO. DESCRIPTION
NAME
DW J OR N
CDL 14 10 Carrier-detect-level adjust for external adjustment of carrier-detect threshold
CDT 3 3 Carrier-detect output. A low-level output indicates carrier failure
CLK 2 2 Output for a continuous clock signal at 16 times the highest selected (transmit or receive) bit rate
NC 4, 6, 8, 10, 6 No internal connection
15, 18, 19, 21
OSC1, 23, 15, Oscillator connections. The crystal (typically 4.4336 MHz) is connected to OSC1 AND OSC2. If an external
OSC2 24 16 clock is used, OSC2 is left open and the clock is connected to OSC1.
RXA 5 4 Receive analog input to which the received line signal must be ac coupled
RXB 11 7 Receive bias adjust for external adjustment of the decision threshold of the comparator to minimize bias
distortion
RXD 12 8 Receiver digital output for the demodulated received data in positive logic. The high logic level is a mark
and the low logic level is a space.
RXT 9 – Receive test access. Output of limiter is available on RXT. (DW only)
TRS 7 5 Transmit /receive standard select input, which with TXR1 and TXR2, sets the standard bit rates and
mark/space frequencies
TXA 16 11 Transmit analog output for the modulation signal, which must be ac coupled
TXD 22 14 Transmit digital input for data to the transmitter in positive logic. The high logic level is a mark, and the low
logic level is a space. The data can be accepted at any speed from zero to the selected speed and may
be totally asynchronous.
TXR1 20 13 Bit-rate select 1 input which along with TXR2 and TRS, sets the bit rates and mark/space frequencies
TXR2 17 12 Bit rate select 2 input, which along with TXR1 and TRS, sets the bit rates and mark/space frequencies
VDD 1 1 Positive supply voltage
VSS 13 9 Most negative supply voltage (normally ground); connected to substrate

2 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
 TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

functional block diagram

Transmit Digital- Transmit
Digital FSK XMT Low-Pass
TXD Modulator
to-Analog
Filter Filter TXA Analog
Input Converter Output

Receive Bias Receive

Adjust RXB
Comparator RXD Digital
Receive Low-Pass Receive FSK Output
Analog RXA Comparator
Filter Filter Demodulator
Input and
Automatic Group Receive
Gain Delay Offset RXT Test
Control Equalizer Compensation DW Package Only Access

Carrier-
Carrier-
Carrier
Detect Delay CDT Detect
Detector Output
Carrier-Detect CDL
Level Adjust

Oscillator OSC1 4.4336-MHz

Connection Oscillator
OSC2
Timing
Bit-Rate TXE1 and CLK Clock
Select TXE2 Control

Transmit/Receive TRS
Standard Select

timing diagram
RXA
Input
(amplitude of received signal)

Off/On Threshold

On/Off Threshold

CDT td(on-off)
Output
td(off-on)

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 10 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Operating free-air temperature range, TA: TCM3105DWL, TCM3105JL,TCM3105NL . . . . . . – 10°C to 70°C
TCM3105JE, TCM3105NE . . . . . . . . . . . . . . . . . . . . – 55°C to 85°C
Storage temperature range: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
NOTE 1: Voltage values are with respect to VSS.

recommended operating conditions

TCM3105DWL
TCM3105JE
TCM3105JL
TCM3105NE UNIT
TCM3105NL
MIN NOM MAX MIN NOM MAX
Supply voltage, VDD 4 5 5.5 4 5 5.5 V
High-level input voltage, VIH 2 VDD 2 VDD V
Low-level input voltage, VIL 0 0.8 0 0.8 V
Analog input level, peak to peak (ac coupled) 0.3 0.78 0.3 0.78 V
Clock frequency, fclock 4.4334 4.4336 4.4338 4.4334 4.4336 4.4338 MHz
Analog load impedance at TXA 50 50 kΩ
Operating free-air temperature range, TA – 40 85 0 70 °C

4 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
 TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TCM3105DWL
TCM3105JE
TCM3105JL
PARAMETER TEST CONDITIONS TCM3105NE UNIT
TCM3105NL
MIN TYP† MAX MIN TYP† MAX
High-level output RXD, CDT,
VOH IOH = – 100 µA 2.4 VDD 2.4 VDD V
voltage CLK
Low-level output RXD, CDT,
VOL IOL = 1.6 mA VSS 0.4 VSS 0.4 V
voltage CLK
VDD = 4 V 1.55 1.55
Analog output voltage kΩ
RL = 50 kΩ,
TXA VDD = 5 V 1.4 1.9 2.3 1.4 1.9 2.3 V
level, peak to peak RL = 100 pF
VDD = 5.5 V 2.1 2.1
RXB 2.3 2.7 3.1 2.3 2.7 3.1
Adjust voltage VDD = 5 V V
CDL 2.8 3.3 3.9 2.8 3.3 3.9
Analog output dc offset TXA VDD/2 VDD/2 V
TXD, TRS,
Digital input current VI = 0 to VDD ±1 ±1 µA
TRX1, TRX2
Analog input current RXA ± 15 ± 15 µA
Bias input current RXB, CDL VI = 3 V ± 150 ± 150 µA
VDD = 4 V 3 6 3 5
IDD S pply current
Supply VDD = 5 V 5 10 5 8 mA
A
VDD = 5.5 V 8 16 8 12
Ci Input capacitance, all inputs f = 1 MHz 10 10 pF
Co Output capacitance, all inputs f = 1 MHz 10 10 pF
Phase jitter 200 200 µs
Bias distortion‡ ± 15% ± 15%
Carrier-detect threshold, off/on§ – 45.5 – 43 – 45.5 – 43 dBm
Carrier-detect threshold, on/off§ – 48 – 45.5 – 48 – 45.5 dBm
Carrier-detect hysteresis 2.5 2.8 2.5 2.8 dBm

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TCM3105DWL
TCM3105JE
TCM3105JL
PARAMETER TEST CONDITIONS TCM3105NE UNIT
TCM3105NL
MIN TYP† MAX MIN TYP† MAX
RX = 600 or 1200 b/s 12 25 12 25
td(off
d(off-on)
on) Carrier-detect off-to-on delay time ms
RX = 5, 75, or 150 b/s 48 80 48 80
RX = 600 or 1200 b/s 12 20 12 20
td(on
d(on-off)
off) Carrier detect on-to-off
Carrier-detect on to off delay time ms
RX = 5, 75, or 150 b/s 48 75 48 75
Transmit frequency deviation from
fclock = 4.4336 MHz ±1 ±1 Hz
assignment (see Table 1)
† All typical are at VCC = 5 V, TA = 25°C.
‡ Bias distortion is the departure from a 50% duty cycle when a series of alternating mark and space tones is received.
§ This is the threshold with the CDL input properly adjusted.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

PRINCIPLES OF OPERATION

The TCM3105 FSK modem is made up of four functional circuits. The circuits are the transmitter, the receiver,
a carrier detector, and control and timing (see Figure 1).

Bias Adjust RXB

Receiver RXD Digital Output
Analog Input RXA

Carrier
Detector CDT Detect Output
Level Adjust CDL

TXR1, TXR2, TRS Timing

and CLK Clock Output
Master Clock (internal) Control

Digital Input TXD Transmitter TXA Analog Output

Figure 1. TCM3105 System Partitioning

transmitter
The transmitter comprises a phase-coherent FSK modulator, a transmit filter, and a transmit amplifier. The
modulator is a programmable frequency synthesizer that drives the output frequencies by variable division of
the oscillator frequency (4.4336 MHz). The division ratio is set by the states of the transmit/receive standard
input (TRS), the bit-rate select inputs (TXR1 and TXR2), and the digital data input (TXD).
A switched-capacitor low-pass filter limits the harmonics and noise outside the transmit band, and the
characteristics of this filter are set by the frequency-select inputs as previously described. The harmonics
introduced by the transmit filter clock are removed by a continuous low-pass filter.
The transmitter output level varies with power supply voltage and so must be compensated in the 2-wire to 4-wire
converter to give a constant output level to the line.

receiver
A continuous low-pass antialiasing filter is followed by the receiver amplifier, which automatically controls the
gain to give a constant output level from the receiver filter. The receiver filter limits the bandwidth of the signal
presented to the demodulator reducing out-of-band interference and has very high rejection of the transmit
channel frequencies. These are typically present at much higher levels than the received signal.
The group delay equalizer is a switched-capacitor network that compensates the delay introduced by the
receiver filter and the network. The output from the equalizer is then limited to give an FSK modulated
squarewave that is presented to the demodulator.
The demodulator is an edge-triggered multivibrator that triggers off positive- and negative-going edges. The
output of the demodulator is a stream of constant-length pulses at a frequency that is double the frequency of
the limited input signal. The dc component of this signal is proportional to the received frequency and is extracted
by a switched-capacitor, low-pass, post-demodulator filter.
The variation of dc level with received frequency is presented to a comparator that slices at a level externally
fixed by the RXB bias-adjustment pin. This voltage depends on received bit rate and internal offsets. The
comparator output is then the received data at RXD.

6 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
 TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

carrier detect
The carrier-detect circuits comprise an energy detector and digital delay. The energy detector compares the
total signal level at the output of the receive filter to an externally set threshold level on the CDL input. The
comparator has a 2.5-dB hysteresis and a delay to allow for momentary signal loss and to prevent oscillation.
The output detector is available on CDT where a high level indicates that a carrier is present. The data output
is clamped to a mark condition when the carrier-detect output switches off at the end of transmission.

control and timing

An on-chip oscillator runs from an external 4.4336-MHz crystal connected between OSC1 and OSC2 or an
external signal driving OSC1. A clock signal equal to 16 times the highest selected bit rate (transmit or receive)
is available on the CLK output.
The single-supply rail means that all analog functions are referenced to an internally generated reference. All
analog inputs and outputs must be ac coupled.

transmit and receive modes

The various modes of operation of the TCM3105 are given in Table 1. The data convention is that a logic high
is a mark and a logic low is a space.

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

Table 1. Modes of Operation

TRANSMIT RECEIVE
CLK
TRANSMITTED RECEIVED FREQUENCY FREQUENCY
STANDARD TRS TXR1 TXR2 FREQUENCY
BAUD RATE BAUD RATE ASSIGNMENTS ASSIGNMENTS
(kHz)
(Hz) (Hz)
M 1300 M 1300
L L L 1200 1200 19.11
S 2100 S 2100
M 1300 M 390
H L L 1200 75 19.11
S 2100 S 450
M 1300 M 390
L L H 600 75 9.56
S 1700 S 450
M 1300 M 1300
CCITT V.23
V 23 H L H 600 600 9.56
S 1700 S 1700
M 390 M 1300
L H L 75 1200 19.11
S 450 S 2100
M 390 M 1300
H H L 75 600 9.56
S 450 S 1700
M 390 M 390
L H H 75 75 1.19
S 450 S 450
M 1200 M 1200
CLK L L 1200 1200 19.11
S 2200 S 2200
M 1200 M 387
CLK/8 L H 1200 150 19.11
S 2200 S 487
M 1200 M 387
CLK/8 L H 1200 5 19.11
S 2200 S 0
M 387 M 1200
BELL 202 CLK H L 150 1200 19.11
S 487 S 2200
M 387 M 387
CLK H H 150 150 2.39
S 487 S 487
CLK† H† L† M 387 M 1200
5 1200 19 11
19.11
H† H† H† S 0 S 2200
Transmit Transmit M 1200
H H H 1200 19.11
Disabled Disabled S 2200
H = high level, L = low level
† In these modes, the modulation is controlled by TRS and TXR2. TXD is tied high.

8 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
 TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

APPLICATION INFORMATION

VDD VDD

7 10
RXB CDL
5 1 VDD
VDD, VSS, or CLK TRS VDD

11
TXA
14
TXD
2-Wire
Line to TCM3105 Microprocessor
Line Signaling Termination 4-Wire UART
FSK MODEM
Converter
8
RXD
4
RXA
2
CLK
13
TXR1
12
TXR2
3
CDT

OSC1 OSC2 VSS

15 16 9

Pin numbers shown are for the J and N packages.

Figure 2. Typical System Configuration

•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

APPLICATION INFORMATION

30 pF 30 pF

16 15
5V
OSC1 OSC2
Receive 8 7 100 kΩ
Data RXD RXB
Transmit 14
Data TXD
TCM3105
1 ZT
VDD 5V = 300 Ω
5V 2
1:1 T
10 TX Gain Adj
100 kΩ CDL
0.1 µF 250 kΩ
100 kΩ
11 ZL ⇒
TXA +
100 kΩ ZT
Carrier 3 100 kΩ _U1A = 300 Ω
Detect CDT + 2
5 U1B R
TRS _
A ZT′
13
Select Mode TXR1 A
(bit rate and 12
TXR2
standard) ZL′
2 A
CLK 50 kΩ
VSS RXA RX Gain Adj A 100 kΩ
9 4 100 kΩ
0.1 µF 250 kΩ
100 kΩ +
+ U1D_
U1C
_
100 kΩ
5V
A 100 kΩ ZT ZT′
47 kΩ =
ZL ZL′
A

U1 = LM124
47 kΩ 10 µF

Pin numbers shown are for the J and N packages.

Figure 3. Telephone Line Interface Circuit

10 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
 TCM3105DWL, TCM3105JE, TCM3105JL
TCM3105NE, TCM3105NL
FSK MODEM
SCTS019C – NOVEMBER 1985 – REVISED MAY 1994

APPLICATION INFORMATION

30 pF 30 pF
A T
100 kΩ
15 16
OSC1 OSC2 0.1 µF ZL ⇒
5V 11 ZT = 600 Ω
TXA +
7 100 kΩ _U1A R
100 kΩ RXB
A ZT′
1
5V VDD 5V
ZL′ 5V
10
100 kΩ CDL
47 kΩ
TCM3105 A
8 A
Receive Data RXD
14
Transmit Data TXD
13
TXR1 0.1 µF 47 kΩ 10 µF
4 +
Standard and 12 RXA U1B
_
TXR2
Bit Rate
5 TRS 100 kΩ
3 CDT
Carrier Detect 100 kΩ

Clock
2
CLK ZT ZT′
= U1 = 1/2LM124
VSS ZL ZL′

Figure 4. Simplified Telephone Line Interface Circuit

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•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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