SET-1

1). Differentiate between i) RISC and CISC Processors ii) Microcontroller and microprocessor.

i).

ii).
2). Explain the architecture of a typical embedded device based on ARM core with a neat diagram.

Typical embedded system mainly has two parts i.e., embedded hardware and embedded software.

Embedded hardwares are based around microprocessors and microcontrollers, also include
memory, bus, Input/Output, Controller, where as embedded software includes embedded operating
systems, different applications and device drivers. Basically these two types of architecture
i.e., Havard architecture and Von Neumann architecture are used in embedded systems.

Architecture of the Embedded System includes Sensor, Analog to Digital Converter, Memory,
Processor, Digital to Analog Converter, and Actuators etc.

The below figure illustrates the overview of basic architecture of embedded systems :

Embedded Product Development Life Cycle (EDLC) :

Developing an embedded system or product mainly goes through this three phases which are –

1. Analysis

2. Design

3. Implementation

If we will go a little bit deeper to the development steps it includes these 7 steps :

1. Requirement analysis

2. Examine
 3. Design

4. Develop

5. Test

6. Deploy

7. Maintenance

Now Let’s discuss some of the advantages and disadvantages of Embedded systems.

Advantages of Embedded System :

• Embedded systems are fast in performance.

• These systems consumes less power

• Small in shape and size.

• These systems are so scalable and reliable.

• Works on wide variety of sectors and environments.

• Improve product quality and enhance performance.

• Performs specific tasks without error.

Disadvantages of Embedded System :

• Difficult to backup of embedded files.

• Sometimes complex to develop.

• Integration may be a problem.

• Offer very limited resources for processing.

• Troubleshooting may be difficult.

• Maintenance may be a problem.

3). a). Discuss the following with diagram. i) Von Neuman architecture with cache ii) Harvard
architecture with TCM.

Von Newman architecture with cache:

it’s a theoretical design based on the concept of stored-program computers
where program data and instruction data are stored in the same memory.
The architecture was designed by the renowned mathematician and physicist
John Von Newmann in 1945.
The Von Newmann architecture consists of three distinct components, a
central processor unit (CPU), Memory unit and input/output (I/O) interfaces.
The ALU is responsible for carrying out all arithmetic and logic operations on
data, whereas the control unit determines the order of flow of indtruction of
need to be executed in programs by issuing control signals to the hardware.

Harvard Architecture:
It is a computer architecture with physically separate storage and signal
pathways for program data and instructions. Unlike Von Newmann
architecture which employs a single bus to both fetch instructions from
memory and transfer data from one part of a computer to another, Harvard
architecture has separate memory space for data and instruction.

b). Discuss the ARM design philosophy.

THE RISC DESIGN PHYLOSOPHY:

The ARM core uses reduced instruction set computer (RISC) architecture. RISC is a design philosophy
aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock
speed.

The RISC philosophy concentrates on reducing the complexity of instructions performed by the
hardware because it is easier to provide greater flexibility and intelligence in software rather than
hardware. As a result, a RISC design places greater demands on the compiler.

In contrast, the traditional complex instruction set computer (CISC) relies more on the hardware for
instruction functionality, and consequently the CISC instructions are more complicated. The
following Figure illustrates these major differences.

4). With an example, explain the following ARM instructions i) BIC ii) MVN iii) ADC iv) RSC v) LDR.

i). BIC:

Example: This example shows a more complicated logical instruction called BIC, which carries out a

logical bit clear.

PRE r1 = 0b1111

r2 = 0b0101

BIC r0, r1, r2

POST r0 = 0b1010

This is equivalent to – Rd = Rn AND NOT (N).

ii). MVN

Here v1 is isa(instruction set architecture).

Example: Loading the constant 0xff00ffff using an MVN.

PRE none...

MVN r0, #0x00ff0000

POST r0 = 0xff00ffff

As you can see, there are alternatives to accessing memory, but they depend upon the constant you
are trying to load.

The LDR pseudo-instruction either inserts an MOV or MVN instruction to generate a value (if
possible)

or generates an LDR instruction with a pc-relative address to read the constant from a literal pool—a
data area embedded within the code.

iii). ADC

iv). LDR

Example:

PRE r0 = 0x00000000

r1 = 0x00090000

mem32[0x00009000] = 0x01010101

mem32[0x00009004] = 0x02020202

LDR r0, [r1, #4]!

Preindexing with writeback:

POST(1) r0 = 0x02020202

r1 = 0x00009004

LDR r0, [r1, #4]

Preindexing:

POST(2) r0 = 0x02020202

r1 = 0x00009000

LDR r0, [r1], #4

Postindexing:

POST(3) r0 = 0x01010101

r1 = 0x00009004

5). a). Write an ALP to find factorial of a given number.

AREA Factorial, CODE,READONLY

ENTRY

MOV R0,#4;

CMP R0,#0

BEQ ANS

CMP R0,#1

BEQ ANS

MOV R1,R0

UP SUBS R1,R1,#1

BEQ STOP;

MUL R2,R1,R0

MOV R0,R2

B UP

ANS MOV R0,#1;

STOP B STOP;

b). Explain the ARM swap instruction with an example code.

Swap Instruction: The swap instruction is a special case of a load-store instruction. It swaps the
contents of memory with the contents of a register.

This instruction is an atomic operation—it reads and writes a location in the same bus operation,
preventing any other instruction from reading or writing to that location until it completes.
Example: The swap instruction loads a word from memory into register r0 and overwrites the
memory

with register r1.

PRE mem32[0x9000] = 0x12345678

r0 = 0x00000000

r1 = 0x11112222

r2 = 0x00009000

SWP r0, r1, [r2]

POST mem32[0x9000] = 0x11112222

r0 = 0x12345678

r1 = 0x11112222

r2 = 0x00009000

6). a). Explain the barrel shifter operation in ARM processor, with a neat diagram.

Barrel Shifter:

In above Example, we showed a MOV instruction where N is a simple register. But N can be more
than

just a register or immediate value; it can also be a register Rm that has been preprocessed by the
barrel

shifter prior to being used by a data processing instruction.

Data processing instructions are processed within the arithmetic logic unit (ALU).

A unique and powerful feature of the ARM processor is the ability to shift the 32-bit binary

pattern in one of the source registers left or right by a specific number of positions before it enters

the ALU.

Pre-processing or shift occurs within the cycle time of the instruction.

o This shift increases the power and flexibility of many data processing operations.

o This is particularly useful for loading constants into a register and achieving fast

multiplies or division by a power of 2.

There are data processing instructions that do not use the barrel shift, for example, the
MUL (multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add)

instructions.

Figure shows the data flow between the ALU and the barrel shifter.

Register Rn enters the ALU without any pre- processing of registers.

We apply a logical shift left (LSL) to register Rm before moving it to the destination register. This

is the same as applying the standard C language shift operator « to the register.

b). Write an ALP for forward and backward branch by considering an example.

Example: This example shows a forward and backward branch. Because these loops are address
specific,

we do not include the pre- and post-conditions. The forward branch skips three instructions. The

backward branch creates an infinite loop.

B forward

ADD r1, r2, #4

ADD r0, r6, #2

ADD r3, r7, #4

forward

SUB r1, r2, #4

---------------------------------------------------

backward

ADD r1, r2, #4

 SUB r1, r2, #4

ADD r4, r6, r7

B backward

In this example, forward and backward are the labels. The branch labels are placed at the beginning
of the line and are used to mark an address that can be used later by the assembler to calculate the
branch offset.

SET – 2
1). Explain the architecture of a typical embedded device based on ARM core with a neat diagram.

Already Done.

2). Explain instruction sets available in ARM processor.

3). a). Discuss ARM bus technology.

ARM Bus Technology:

Embedded devices use an on-chip bus that is internal to the chip and that allows different peripheral
devices to be interconnected with an ARM core. There are two different classes of devices attached
to the bus:

1. The ARM processor core is a bus master—a logical device capable of initiating a data transfer with
another device across the same bus.

2. Peripherals tend to be bus slaves—logical devices capable only of responding to a transfer request
from a bus master device.

A bus has two architecture levels:

A physical level—covers the electrical characteristics and bus width (16, 32, or 64 bits).

The protocol—the logical rules that govern the communication between the processor and a
peripheral.

b). Discuss the RISC design philosophy and mention the four rules.

Already done

4). Explain the following ARM instructions i) RSB ii) BL iii) LDMIA iv) OR v) RRX with an example.

i). RSB

Example: The following reverse subtract instruction (RSB) subtracts r1 from the constant value #0,

writing the result to r0. You can use this instruction to negate numbers.

PRE r0 = 0x00000000
r1 = 0x00000077

RSB r0, r1, #0 ; Rd = 0x0 - r1

POST r0 = -r1 = 0xffffff89

ii). LDMIA:

Example: In this example, register r0 is the base register Rn and is followed by !, indicating that the

register is updated after the instruction is executed. You will notice within the load multiple
instruction

that the registers are not individually listed. Instead the “-” character is used to identify a range of

registers. In this case the range is from register r1 to r3 inclusive.

Each register can also be listed, using a comma to separate each register within “{” and “}” brackets.

PRE mem32[0x80018] = 0x03

mem32[0x80014] = 0x02

mem32[0x80010] = 0x01

r0 = 0x00080010

r1 = 0x00000000

r2 = 0x00000000

r3 = 0x00000000

LDMIA r0!, {r1–r3}

POST r0 = 0x0008001c

r1 = 0x00000001

r2 = 0x00000002

r3 = 0x00000003

iii). ORR

Example: This example shows a logical OR operation between registers r1 and r2. Register r0 holds
the
result.

PRE r0 = 0x00000000

r1 = 0x02040608

r2 = 0x10305070

ORR r0, r1, r2

POST r0 = 0x12345678

iv). RRX

5). a). Write an ALP to find larger of two numbers stored in memory location ARRAY and store the
result in R0.

Not found.

b). Explain the multiply instruction of ARM processor.

Multiply Instructions: The multiply instructions multiply the contents of a pair of registers and,
depending upon the instruction, accumulate the results in with another register. The long multiplies
accumulate onto a pair of registers representing a 64-bit value. The final result is placed in a
destination register or a pair of registers.

Example: This example shows a simple multiply instruction that multiplies registers r1 and r2
together

and places the result into register r0. In this example, register r1 is equal to the value 2, and r2 is
equal to

2. The result, 4, is then placed into register r0.

PRE r0 = 0x00000000

r1 = 0x00000002

r2 = 0x00000002

MUL r0, r1, r2 ; r0 = r1*r2

POST r0 = 0x00000004

r1 = 0x00000002

r2 = 0x00000002

6). a). Explain the barrel shifter operation in ARM processor, with a neat diagram.
Already done.

b). Write an ALP to find the sum of first 5 numbers.

mov ax, 1
mov cx, 10
xor dx, dx ;This puts zero in DX
Label1:
add dx, ax ;This adds int turn 1, 2, 3, ... ,10 to DX
inc ax
loop Label1