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Every effort has been made to ensure accuracy, however neither the publisher nor the authors guarantee the accuracy or completeness of any information published herein, and neither the publisher nor the authors shall be responsible for any errors, omissions, or damages arising out of use of this information. VLSI Design (EC : Sem-7) : 2011-12 : 2012-13 2013-14 4% Edition : 2014-15 5t Edition : 2015-16 6 Edition : 2016-17 7 Edition : 2017-18 8 Edition : 2018-19 9" Edition : 2019-20 [mn SSS Printed at : Balajee Offset, Del 10% Edition : 2020-21 Mos Introduction: A Brief History, sn Partitioning, Logic Design Pat zi Desi esign Verification, 105 Transistors, Design, Circuit Design Fabrication, Packas (a0 C—64 C) UNIT-2 : DELAY AND POWER i : Oe Delay: Introduction, Transient Response, RC delay Lae ha Delay Model, Logical Effort of Paths, Timing, ay! Power: Introduction, Dynamic Power, Static Power. (65 C-86C) 17-3 : INTERCONNECT ; a Energy - Delay Optimization, Low Power Architectures: Interconnect: Introduction, Interconnect ‘Modelling, Interconnect Logical Effort with Wires. YNAMIC LOGIC CIRCUITS (87 C—122 C) Dynamic logic circuits: Introduction, basic principle of pass transistor circuits, synchronous dynamic circuit techniques, dynamic CMOS circuit techniques, domino CMOS logic: Semiconductor memories: Introduction, DRAM, SRAM, ROM, flash memory. UNIT-5 : LOW-POWER CMOS LOGIC CIRCUITS (123 C—-158 C) ‘Low-Power CMOS Logic Circuits: Introduction, Overview of Power Consumption, Low - Power Design through voltage scaling, Estimation and Optimization of switching activity, Reduction of ‘Switched Capacitance and Adiabatic Logic Circuits. Design for Testability: Introduction, Fault Types and Models, Controllability and Observability, Ad Hoc Testable Design ‘Techniques, Sean Based and BIST Techniques. SHORT QUESTIONS (159 C—176 C) SOLVED PAPERS (2016-17 TO 2019-20) (c—s20)Introduction to VLSI Introduction ; A Brief History Preview, MOS Transis CMOS Lom ransistors A Concept Outline: Part1 }. Long and Medium Answer Type Questions Part-2 + (22C - 390) oe Fabrication and Layout sign Partitioning, Logic Design, Ci i ign Verificatic he cic oe ircuit Design, Design Verificatio A. Concept Outline : Part-2 ... B. Long and Medium Answer Type Questions 4(EC-7)C a function of times hhas been a count a8 = When we plot log ofthe component we get etraight lie, ei that oer three bewniea i in the com . eect he eoughly doubled every 18 farm _ seated early by Gordon Moore. This regular ‘known as Moore's law: oe: CMOS technology provides two tyBes of transistors n-type transistor (nMOS) p-type transistor (pPMOS) ‘Transistor operation is based on elec also called Metal Oxide Semiconductor (MOSFETs) or simply FETs. trie fields so the devices are ‘Field Effect Transistors oF me ‘Quetdnl] Briefly describe the evolution and enhancement of integrated circuit. ‘Answer 1. ‘The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in integration technologies. 2 ‘Typically the required computational and information processing power of these applications is the: driving force for the fast development of this field Era Year | Complexity Single transistor 1958 | <1 Unit logic (one gate) 1960 | 1 Multi-function 1962 | 2-4 Complex function 1964 | 5-20 Medium Scale Integration (MSI) 1967 | 20-200 Large Seale Integration (LSD 1972 | 200 - 2000 Very Large Scale Integration (VLSI) | 1978 | 2,000 - 20,000 Uitra Large Scale Integration (ULSI) | 1989 | 20,000-?.3. One of the most important characteristics of information ser their increasing need for very high processing power and bandwid 4. This trend towards portable, distributed system architecture is oy, the main driving forces for system integration, network computing video services. 4. The monolithic integration of a large number of function on a sngy chip usually provides : a. Less area/volume and therefore, compactness. b. Less power consumption. ¢. Less testing requirements at system level. 4 Higher reliability, mainly due to improved on-chip interconnect, 5. Therefore, current trend of integration will continue in foreseeable future. 6. Advances in device manufacturing technology allow the steady reduction of minimum feature size. 7. Fig. 1.1.1shows the evolution of the minimum feature size of transistors in integrated cireuits, since late 1970’. 8, In 1980, at the beginning of the VLSI era, the typical minimum feature size was nearly 2 um and 6 nm was expected around year 2011. 9. The actual development of the technology however, has far exceeded these expectations. 10. ‘The first 64-Mbit DRAM and INTEL Pentium containing more than 3 million transistors were already available by 1994. ' 11. The first 4G bit DRAM based on 0.15 jm manufacturing technology was announced by NEC in early 1997. 12. As per International Technology Roadmap for semiconductors (ITRS), MOS with feature size of 70 nm will be available by 2008. 4umt 24m 16 Minimum © !™ 14m size 0.5 pm. 90 nm. 32 nm. 20 nm. 1975 1980 1985 1990 1995 2000 2005 2011 aS RTD state Moore's Law. as 18 months, a8 Wee the: ee has roughly doubled tng is known 28 : ity is the i complexity is ‘The main factor that has enabled this increase of oe : a ae umber of compone cs fan " number of being advantageous 1 Clearly, one on an IC if they are smaller, o> " a ime for memory chiPs- fra. 1.2:1 shows the level of integration Vo g. 1.2. nts with greater 10B 1B 100M Number jo transistors perchip 1M 100K 10K 1975 1980 1985 1990 1995 2000 2010 2011 Year It can be observed that in terms of transistor count, logic chips contain significantly fewer transistors in any given years mainly due to large consumption of chip area for complex interconnects. ‘Memory circuits are highly regular and thus more cells can be integrated with much less area for interconnects. boEe, Introduction to VLSI tinue to be strong di reliable performances cireuit u. s dynamic circuits, : 'w Projected to decrease up to. sev j vo, {insistorsor even higher w > fo several hundreds of billions of Bipolar and gin ‘arsenide (GaAs) circuits have been used for very high speed and this practice inue. MMIC's, GaAs MOSFET technology has been highly successful, Jong as the downward scalin, ; 0 ig of CMOS technology remains strong, other technologies are likely to remain the technology of tomorrow. Que 13, ] Explain the structure and working of MOS transistors. A. Structure of MOS Transistors : 1 13. A MOS (Metal-Oxide-Semiconductor) structure is created by superimposing several layers of conducting and insulating materials to form a sandwich-like structure. ‘These structures are manufactured using a series of chemical processing steps involving oxidation of the silicon, the diffusion of impurities in to the silicon to give it certain conduction characteristics, and the deposition and etching of aluminium or other metals to provide interconnection, Source Gate Drain source Gate Drain Polysilicon t SiO, i nt Ss P+ P___bulk Si a (@) Fig. 18.1. (b) Cross-sections and symbols of nMOS transistor and pMOS transistor are shown in Fig. 1.3.1. The n+ and p+ regions indicate heavily doped n- or p-type silicon. P+ bulk Si Each transistor consists of a stack of the conducting gate, an insulating layer of silicon dioxide and the silicon wafer, also called the substrate, body or bulk. The gate is typically formed from polycrystalline silicon (polysilicon). An nMOS transistor is built with a p-type body and has regions of n-type semiconductor adjacent to the gate called the source and drain. A pMOS transistor consists of p-type source and drain region with an n-type body. occ © ‘VLSI Design sca) current peewee? , Working of MOS Tranter ene flow of © so the Oe Thegate ina contzolinput Te grouns 1 i 10. the sourceanddrain- Consider an nMOS transis®™ aoain to body prn junctions of the S0UF** © 1 current OW" OFF. te is also grounded, We transistor is Oona If the gate % &,. Hence, we 889 electric fie! biased junction®. "".s raised, it creates Om If the gate voltage 4 i re Si-SiOs act free electrons to the ‘underside of the attr e If the voltage is raised ¢ as an nough, the lector el is inverted Fe act as ‘a thin region under the gate called a type semiconductor. Hence, formed from source to drain, is ON. ; For a pMOS transistor, the at Sarai saat ean @ OFF fiased and no current flows, 80 ans ea 1 ane ea en gate voltage is lowered, positive charges 2 + age inverts When the gat vo iO, interface. A sufficiently 1ow SP ered from unde rsieecl and a conducting path of positive carr source to drain, so the transistor is ON. ee Tn summary, when the gate of an nMOS transistor 58,0) is ON and there is a conducting path from source Ps When the gate is low, the nMOS transistor is OFF and alm current flow from source to drain. | ansistor is j ite, being ON when the gate is low ApMOS transistor is just the opposite, being n th , and OFF when the gate is high. This switch model is illustrated in Fig. 1.3.2, where g, s, and d indicate gate, source, and drain. g=0 5 8 a i“ a omos ef, on ore 3 Fig. 1.3.2; Transistor a q1 Fig. 1.4.10) shows a CMOS i 7 MOS inverter , transistor and one pMOS transistor, or Nor ., the input A is ‘0’, the nMOS i When the i , transistor is OFF Cansistor is ON. Thus, the output ¥ is pulled up te cnn! Mog 4, ‘ames Vn but not CNB. Pee + phen A is, the aMOS is ON, the pMOS is OFF, and the down to ‘0’. This summarized i Yis in Fig. 1.4.16), aried inthe truth able andthe eymbliep Lnverter truth table A Y a 1 1, Fig. 1.5.1() shows a 2-input CMOS NAND gate. It consists oftwo series nMOS transistors between Y and GND and two parallel pMOS transistors between Y and V,y. 2. Ifeither input A or Bis‘0,’ at least one of the nMOS transistors will be OFF, breaking the path from Y to GND. But at least one of the pMOS transistors will be ON, creating a path from ¥ to Vg, Hence, the output Ywill be‘T. 110-DC Ma Yoo r4 y=aB a Y , > B ® i eI istors will be ON and both inputs are ‘1’, both of the nMOS trs ¢ i . oftae pos ‘eansistors will be OFF. Hence, the output will be 0. is in Fig. 1.5.16) 4 ‘The truth table is given below and the symbol is shown in Fig 16. U re ¥ a ON: 1 0 0 OFF of} 4 OFF oN i 1] 0 OFF ON 0 aja ON OFF TE Write short note on combinational logic. 1 The inverter and NAND gates are examples of complementary CMOS logic gates, also called static CMOS gates. 2. Ingeneral, a fully complementary CMOS gate has an nMOS pull-down network to connect the output to ‘0’ (GND) and pMOS pull-up network to connect the output to ‘I’ (Vp) as shown in Fig. 1.6.1. The networks are arranged such that one is ON and the other OFF for any input pattern. 3. The NANDgate used a series pull-down network and a parallel pull-up network. 4. Twoormore transistors in series are ON only ifallof the series transistors {2 ON. Two or mere transstorsin parallel are ON ifany of the parallel ransistors are ON. is illust in Fig. 1.6.2 fo m= trated in Fig. 1.6.2for nMOS and pMOS 5. By using combinations of the: sf inatic nee : "se constructions, CMOS combinationalwmone tty luctonto ag pMOS pull-up | network Inputs uit pMOS pull-down network . b b b OFF @ _ on a wae i 2 a a = 4p a t 1 1 0 ‘ey b 5 oN - b b w@ on OFF {are shown in Table, tt verte “and NAND gates, 6 possible levels at the output are te ‘been encoun ON. the pull-up or pull-down is FF and Ea oe as cation |-upand are OFF, the hig es i ene pais This js of importance 3m ‘multiplexers, memory ‘lements and bus drivers. : 8. The crowbarred X level exists when both pull-up and pull-down are simultaneously ‘turned ON. -, 9. ‘Tuiscquses an indeterminate love and also static power tobe dissipated. Tras asually an unwanted condi'ecr in any CMOS digital circuit. rSurput states of CMOS logic gate pull-up OFF pull-up ON pull-down OFF Z 1 [_patkdown ON 0 ‘crowbarred (X) GasUA | Sketch a 2input CMOS NOR gate and also discuss its working. 1. A2-input NOR gateis shown in Fig. 1.7.1. The nMOS transistors are in parallel to pull the output low when either input is high. ansistors are in series to pull the output high when both 2. The pMOS tr ‘as indicated by the truth table. inputs are low, x sa with ts LAND gat, there is never a case in which the output is NOR gate truth table B ¥ o 1 1 o 0 0 1 0 @ Fig. 1.7.1. 2-1 ‘input NOR gate schematic (a) ans et OY =A+B14(EC-7)C Introduction to VLSI TRH] Explain CMOS compound gate for function Y= @B+CD)- 1. Acompound gate is formed by using a combination of series and parallel switch structures. Fig. 1.8.1 shows such an AND-OR-INVERT-22, or AOI22. 2. ThenMOS pull-down network pulls the output low ifeither A and B are ‘Y orifeither C and D are‘l’. Therefore, the AND expressions (A’B) and. (C:D) may be implemented by series connection of switches. (i., AB and CD ORing operation requires the parallel connection of these two structures). c4 Ip aq pbs ¥=(AxB)+(CxD) [-e B. D Bes 4, The pMOS pull-up network is the conduction complement. Therefore, transistors that appear in series in the pull-down network must appear in parallel in the pull-up network and transistors that appear in parallel in the pull-down network must appear in series in the pull-up network. Sketch « complementary CMOS gate computing y= G+B+O-D. j z 1. Fig. 19.1 shows such an OR-AND-INVERT-$-1 (OAIS1) gate. 2. The nMOS pull-down network pulls the output low if Dis ‘Y’ and either Agr Bor Care'Y 20D isin serie with th paral combintionof 42 C. ‘The pMOS pull-up network is the conductios aa rapa ith the series combination ofA, Band C- D et et v Fig: 1911. CMOS compound gate for function Queti0| Explain the concept of strong ‘0’ and weak ‘1’ in pass transistors. 1 An nMOS transistor is an almost perfect swite! thus, we say it passes a strong'‘0” 2 However, the nMOS transistor is imperfect at passing a ‘I’. The high voltage level is somewhat less than V;,, We say it passes a degraded or weak ‘1’. 3, ApMOS transistor again has the opposite behavior, passing strong ‘1's putdegraded ‘0's. The transistor symbols and behaviors are summarized in Fig. 1.10.1. y¥=G@+B+0) D +h when passing a ‘0’ and . =0 Input g_ 1 Output nMOS sa sod 8-0-0 strong 0 gel 4 g=1 S00 1--po- degraded 1 (a) (b) (©) g g=0 Input ,— 9 Output g=0 Output mwos A sored 0-o-p0- degraded 0 =1 F 5 B= od 1-e-p0- strong 1 @ (e) ry ‘Fig. 1.10:1, Pass transistor strong and degraded outputs, 4. When an MOS or pMOS is used alone in an i sation callit pen Gonaiton, ne *2 imperfect witch, wo17 (EC-7) © 16(EC-7)C Introductionto vig, | VLS!Design ‘Truth table for tristate Que: Explain the working of transmission gate (TG). ava Z ¥ eae] on a z Zz 1. By combining an nMOS and a pMOS transistor in parallel ow 1 i Fig. 1.11.1(a), we obtain a switch that, turns on when ‘l'is applied tog vo o Fig, 11.10) in which ‘0s and ‘’s are both passed in an acceptable [1 1 1 fashion Fig. 1.11.1(c). We term this a transmission gate or pass gate. 2, Inacircuit where only‘! or‘I’ has to be passed, the appropriate transistor a4 (nor p) can be deleted, reverting to a single nMOS or pMOS device. 3, Note that both the control input and its complement are required by the At transmission gate. This is called double rail logic. Some circuit symbols ad y for the transmission gate are shown in Fig. 1.11.1(d). - Input Output EN: g= 0, gb=1 g=1,gb=0 £ aod de-so- strong 0 4 Al a_}> g=1,gb=0 g=1,gb=0 EN=1 Tv a-obo-b 1-0-po- strong 1 Y=A sb @) fo) (a) 6) (c) (d) @ Fig. 1.12.2. Tristate inverter. 8 i f 3. Fig. 1.12.1(a) shows a tristate inverter. The output is actively driven Rte eo a P b from V;) or GND, 80 it is a restoring logic gate. gb gb 4. When EN is 0’ Fig. 1.12.1(0), both enable transistors are OFF leaving @ the output floating. Fig. 1.11.1. ‘Transmission gate. 5. When ENis‘1’ Fig. 1.12.1(c), both enable transistors are ON. They are conceptually removed from the circuit, leaving a simple inverter. understand by tristate buffer ? Also explain Qire 1.12. | What doyou the operation of ‘CMOS tristate inverter. wr. When the enable input ~ buffer. 1 arized 1 ,. 1.12.1 shows symbols for a tristate buffer EN isl’, “be output ¥ equals the input A, just as in an ordin: When the enable is 0’, Y isleft floating (a ‘Z’ value). This is ur in Table : EN EN A pha A to Fig. 1.12.1. Tristate buffer symbol. 2. Fig. 1.12.1(d) shows symbols for the tristate inverter. Quel) What is multiplexer ? Briefly discuss about two-input transmission gate multiplexer and inverting multiplexer. Answer 1 2 A multiplexer chooses the output i Amultplons output to be one of several inputs based on a A two-input or 2:1 multiplexer, chooses i ‘A two input or 2: multiplexer, chooses input DO when the select is ‘The truth table is given in Table the logic function is Y= S-D0+S-D: ‘Two transmissi ; Sos Ok multiplexer, aa chewete ce Sea to form a compact 2 input enable exactly one of the two tranemic sion a at pais complement given time.. Ea lt” 18(EC-7).C Introduction to Vig) Multiplexer truth table sis DI DO x te on x 0 o on x 1 1 vo o x 0 vo 1 x 1 nonrestoring multiplexer. We 5. Again, the transmission gates produce a. gates in several could build a restoring, inverting multiplexer out of ways. 6. Oneis the compound gate connected as shown in Fig. 1.18.2(a). Another is to gang together two tristate, inverters, as shown in Fig, 1.19.10). i L.A po Ly poo “tb : pil pi ole s @ ®) Fig. 1.13.1. Transmission gate multiplexer. more compact and faster because it in, if the complementary select is the symbol Fig. 1.13.2(c). 7, The tristate approach is slightly requires less internal wire. Agai generated within the cell, itis omitted from po-4 >—S po--4[ p14 sl Lamia erat S440 po sh s sue sH 4 Le Ur ™ @) w Fig, 1.13.2. Inverting multiplexer. ‘Que 1.14, | Explain the operation of ‘CMOS positive-level-sensitive De-lateh. @ OR Describe the working of D-latch. 6. ‘VLSI Design 1. AD-atch using one 2+ Fig. 1.14.1(@). It consists ‘and complementary outputs ‘of a data input Qand Q. 2. When CLK = Fig. 114.10). 3. When CLKis switched to the inverter pair is establis Qindefinitely. 4. While the latch iso 4 constructed from a pair of transmission ished Fig. 1.14. input multiplexer and two +], the latch is transpare wae ag ‘hold the current 19(EC-D) C inverters is shown in ‘p, aclock input CLK, and true nt. Q=Dand @= D around .. A feedback path: state of 1(d) to ‘The multiplexer can be input D is ignored. ppaque, the! i hown in Fig. 1.14.10). gates, ouK Ore @ —L p—r Q D a Hy - o cr = or (@) (6) Q @ qe a CLK=1 © ‘sensitive latch because the el of the clock signal, as heen in| 's @ positive-level-sensitive latch, represented by the symbol in Fig. 1.14.1() aaa20 (EC-7) C Introduction to VLS] 6. Byinverting the control connections to the multiplexer, a negative level sensitive latch maybe constructed. TETAG]] xptain the operation of master-slave flip-flop, OR Describe the working of CMOS positive-edge-triggered D flip-flop. 1. Bycombining two level-sensitive latches, one positive-sensitive and one negative-sensitive, we construct on edge-triggered flip-flop as shown in Fig. 1.15.1(a) and (b). 2. By convention, the first latch stage is called the master and the second is called the slave. 3. While CLKis low, the master negative-level-sensitive latch output @™) follows the D input while the slave positive-level-sensitive latch holds, the previous value Fig. 1.15.1(c). 4, When the clock transition occurs from 0 to 1, the master latch ceases to Sample the input and holds the D value atthe time of the clock transition passing the stored master value (QM) to the )). The D input is blocked from affecting the utput because the master is disconnected from the D input Fig. 1.16.10, 5. When the clock transitions from 1 to 0, the slave Jatch holds its value and the master starts sampling the input again. ‘The slave latch opens, output of the slave latch (Q) CLK | QI Si a 40H | 2g Q B Ol g Bl Sour ) 21 C-DC VLSI Design ow @ pore cuk=0 |, © om Dar ame+ @ CLK D Q © CLK — Ee ” Fig. 1.15.1: CMOS positive-edge-triggeredD flip-flop: 6. Insummary, this flip-flop copies D to Q on the rising edge of the clock, as shown in Fig. 1.15.1(e). Thus, this device is called a positive-edge triggered flip-flop also called a D flip-flop, D register or master slave flip-flop. Fig. 1.15.1() shows the circuit symbol for the flip-flop. ‘Que 1,16, | How hold-time problems are avoided in flip-flops ? OR Explain the role Be e role of two-phase non-overlapping clocks in CMOS i.e., if one flip-fl 4 because of variations in ker arbors early and another triggers late22 (EC-7) C Introductionte vig Fig. 1.16.1 show the flip-flop clocked with two non-overlapping ‘As long as the phases do not overlap even with worst-case skews, Jeast one latch will be opaque at any given time and hold-time problemy will never occur. 3. latches. QM on aL oF pti aK ee pee Fig. 1.16.1. CMOS flip-flop with two-phase non-overlapping clocks. PART-2 CMOS Fabrication and Layout, Design Partitioning, Logic Design, Circuit Design, Physical Design, Design Verification, . Fabrication, Packaging and Testing. CONCEPT OUTLINE : PART-2 ‘* Transistors are fabricated on thin silicon wafers that serve as both a mechanical support and an electrical common point called the substrate. . pMOS transistors are often wider than nMOS transistors because holes move more slowly than electrons so the transistor has to be wider to deliver the same current. © Stick diagrams are easy to draw because they ‘do not need to be drawn to scale. ©. The design rules are usually described in two ways : 1. Micron rules, in which the layout constraints ‘such as minimum feature sizes and minimum allowable feature separations are stated in terms of absolute dimensions in micrometers. 2. Lambda rules, which specify the layout constraints in terms of single parameter (2) and thus allow linear, proportional scaling, of all geometrical constraints. + Digital VLSI design is often partitioned into five levels of abstractions: architecture design, micro architecture design, logic design, circuit design, and physical design. Itis offen useful to provide reset and/or enable signals to flip-flop ang ‘VLSI Design rn substrate have to jticon surface, Initially silico jon of the 5 mal oxidation of ct mre sequence st ries or aiO) lever oor ‘results in gro Fig. 117.10). toresist, which is ne substance called Photore= "47 1(¢). s coated with the (polymer as Show> ‘acid-resist OTB a : portioi : --1 ig exposed to UV light the expose’ ‘When photoresit pees ea Pesily etch that portion. se mask, it allows the become soft so that sol chown in Fig. 1.17-1(@). exposed to light ‘The entire layer i alight sensitive, i iti re we Ui lect the specified position for exposure vo ge of UV light from its transparent portion ass ‘The type of photoresist initially hard in nature but when Te SoBe soft are called as positive photoresist. ture step, the soft portion is etched off using the UV expos FO ow near a main Fig. 1.17-1(e). solvents (HF acid) as show! the SiO, region which is not covered can be etch ‘al solvents shown in Fig. 1.17.1(/). Now, ed away by using chemi . Weobtain an oxide window that reaches down to the silicon surface, the vee euning photoresist can now be stripped from rest of SiO, surface by sing another solvents as shown in Fig. 1.17.1). ‘The sequence of fabrication step actually is a single pattern transfer on to the SiO, surface. . The fabrication of semi-conductor devices requires several such pattern transfer to be performed on SiO,, polysilicon and metal. »24(EC-7) C Si-substrate (a) Sa SiO, (Oxide layer) (6) Photoresist SiO, (Oxide layer) ) e UV-Light +— Mask ty Opaque position ‘Transparent postion Insoluble photoresist SiO, (Oxide layer) Expose soluble photoresist Chemical / Dry etch @ Hard photoresist SiO, (Oxide layer) Si-substrate (e) Hard photoresist SiO, (Oxide layer) Si-substrate SiO, (Oxide layer) 6. Polysilicon is used both as gate electrode and for 25 (EC-7) C ee esss—sS—M TD 1. Initially, we take a piece of p-type Si-substrate as shown in Fig. 1.18.12), ‘The process starts with thermal oxidation of Si-substrate as shown in Fig. 1.18.16), 3. Using mask and etch open the desired portion from the substrate as shown in Fig. 1.18.1(c) and Fig. 1.18.1(d), ° ESE: SiO, layer @) UV Light +t a Opaque position Peseta Seer Si-substrate <— Photoresist SiO, layer 4. The surface is now covered with thin oxide layer which forms the gate oxide ofthe MOS transistor. « Fig. 118.10). interconnect medium. 7. After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates, & The thin gate oxide not covered by polysilicon is also etched a way, to Nek inn twit Cs eros wl dende Secon ag Eee formed as shown in Fig. 1.18.1(). Polysilicon layer +——Thin oxide Si0, layer26 (EC-7)C 10. uu. 12, 13. 14. rules or MOSIS design rules). ‘The open area is doped with high concentration of n-type impurities yi diffusion or ion-implantation process as shown in Fig. 1.18.1), ‘The polysilicon gate which is patterned before doping, actually'creaty the precise location of the channel region and hence, the location of he source and the drain region. \ So, it is also called as self-aligned process. Once the source and ran region are completed, the entire surface is again covered with insulating layer, and then patterned in order to provide contact window forthe drain and source as shown in Fig. 1.18.1(h). Polysilicon layer ‘Thin oxide 7 nila Si-substrate Ld @ Insulating oxide Thin oxide — SiO, layer ®) Si-substrate ‘Metal contact Insulating oxide MK Thin oxide <— Sid, layer tol Lo Si-substrat ‘The surface is covered with evaporated aluminum which wil form the interconnections. Finally, the metal layer is patterned and etched completing the interconnections of the MOS transistors on the surface as shown in Fig. 118.100. However, second (or third) layer of metallic interconnect can also be added on top. j;] Write a short note on layout design rules ()-based design @ 27(EC-1).C mastee z 2 3 r be and how closely ‘Layout design rules describe how small features can be and they can be packed in manufacturing 8 eter ®, which Lambda-based design rules based on a sing! ramet characterizes the resolution of the Process. jis generally half of the minimum ‘thistength is the distance between the source R01 "ry soem hoot by the minimum width ofa polysilicon Wr typically specified in microns for dimensions above 0. and in nanometers below. . ee MOSIS has developed a set of scalable lambda-based design rules tover a wide range of manufacturing Processes: ‘A set of design rules for layouts with two metal: process isas follows. Metal and diffusion have minimum Contacts are 2A x 2. and must be surrot and below. Polysilicon uses a width of 2. on Polyslioon overlaps difusion by 24 where a transistor is d aspacing of 1h away where no transistor is desired. o Polysilicon and contacts have a spacing of 32 from other polysilicon or contacts. Newell surrounds pMOS transistors by 62. and avoids nMOS transistors by. Fig. 1.19.1 show the basic MOSIS design rules for a process with two metal layers. Transistor dimensions are often specified by their ‘Width/Length (W/L) ratio. Moral2 a layers in an n-well width and spacing of 42. vunded by 1 on the layers above Maal Diffusion _Polyeiicon 4 ‘well aECDC es er Introduction to VIS} . transistors are often wider than. transistor ‘holes ™move more slowly than clectrons 80 feo tos beet to r deliver the same current. Sketch a stick diagram for a io CMOS 3-iny and also estimate the cell width and height. put — 6 tracks = a Anawer | 1. Fig. 1.20.1 shows a stick diagram. 5 tracks = 402 Fig. 1.21.1. CMOS compound gate for function ¥ + (A+ B + C)- D. Quotas] way Ychart is design flow ? Explain the three domains of VLSI design flow. Answer 1. The chart was first introduced by D. Gajski. Y-Chart illustrates a simplified design flow for most logic chips, using design activities on ential in implementation of VLSI three different domains which resemble the letter Y. al Yechart havior Fig. 1.20.1. 3-input NAND gate area estimation. Scrctaral to ‘Algorithm ‘There are four vertical wire tracks, multiplied by 84 per track to gives ‘nite sate machine cell width of 322. 3. There are five horizontal tracks giving a cell height of 40 (ie. 8 Qeerat] Sketch a stick diagram for a CMOS gate com Y = (A+B+O)-D and estimate the cell width and height 1. Fig. 1.21.1 shows stick diagram. Counting horizontal and vertical gives an estimated cell size of 40 by 482. 2. Module Description ‘Transistor Boolean equation(EC-7) C 2. & 10. Behavioral Representation Logic (Gate-level) Representation Circuit Representation Layout Representation Fabrication and Testing ‘The next design evolution defines FSM implemented with registers and ALU. These modules are then geometrically placed onto chip surface using CAD tools. ‘The third evolution starts with behavioral module description. Individosl modules arc ihen implemented with leaf cells. Logic gates (i. can be plac ‘.by using a cell placement and routing pro: ‘The last stage involves implementation of leaf and m: i" Bg. 1.22.2 below provides a more simplified view of the VLSI desi Note that the verification of design plays a very important role in eve" step during this process. —- ‘The failure of design during verification cat ive re-design #t latter stage and results in increased time tomarket. Although top-down design flow appeals for design in reality 5 tow -ocess, but i there is no uni-directional top-down design flew, Both top-down a4 ttom-up approaches have to be combined for a successful desig™ 10. uw. 12. into sub-m\ : ividing module into sul hierarchy involves divi le. ers ‘af the smaller parts becomes re tathree domains Similarly, the design of VLSI Pa ha iesin different Itis important! implicit + tural decomposition of © domains be : CMOS 2 bit adder into -ate carry and sum de be decomposed a Send individual logic gates. — | Adder @bit) [Sum] partitioni i i alization of ‘The above partitioning provides a valuable guidance for re these blocks on the chip. The approximate shape and area of each sub- cae sehould be estimated in order to provide a useful floor place. Regularity means that the hierarchical decomposition of a large system weerid result in simple as well as similar blocks as much as possible. Regularity can exist at all level of abstraction. For example, design of aeny structures consisting of identical cells at transistor level and at gate level. Ifthe designer has a small library of basic building blocks, a number of different functions can be constructed by using this principle. Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction. Modularity in design means that the various functional blocks which make up the large system must have well-defined functions and interfaces. Each block or module can be designed independent such flexibility is provided by modularity. All the blech from eact other Gardin rn ity. All the blocks can be combined ———s es on design process to form the large system. ‘modularity enable the parallel process during the design”32 (EC-7) C 13. The concept of locality ensures that connections between module are mostly between neighbouring modules, avoiding distang. connections as much as possible. During interfacing each module in the system, make internals of each module becomes unimportant to the exterior modu . Far-interconnections can be avoided as they provide long delays in the system. All the time-delays operations should be performed local, without the need to access far placed modules. % RGUTAT] Draw and discuss in brief about top-level MIPS block diagram. Answer 1. The chip is partitioned into two top-level units: datapath, as shown in block diagram in Fig. 1.24.1. 14. the controller and — or ee eel FART , | HET as] EYAL i ph = = Soca San Fig. 1.24.1, Top-level MIPS block diagram. ‘The controller comprises the control FSM, the decoder, and the two gates used to compute PCEn. ‘The ALU decoder consists of combinational logic to determine ALU control. ‘The 8-bit datapath contains the remainder of the chip. It can be viewed as a collection of wordslices or bitslices. Awordslice is a column containing an &-bit flip-flop, adder, multiplexer, or other element. Introduction to vy | sure that the ! ; shows part ofthe design hierarchy for the MIPS processov, troller contains the controller_pla and aludec, which srl esc mom a brary of standard cells such as NANDs, 5 inverters. : ; datay posed i i also is e omy of 8-bit wordslices, each of which also Ppcally built from standard cells such as adders, register file bits, jaultiplexers, and flip-flops. Some of these cells are reused in multiple et Sail ‘The design hierarchy does not necessarily have to be identical in the logic, circuit, and physical designs.9. Que 1.27, | Explain the concept of circuit design. me L it ify the design at a higher leve 1s provide a way to specify h me imi designer productivity. ‘They were originally wt documentation and simulation, but are now used to sy ef directly from the HDL. / ‘The we ‘most popular HDLs are Verilog and VHDL. VHDL sg ‘VHSIC Hardware Description | - coding styles. spot Poe esol reser primitive gates and irameineene HDL specifies what.a cell does. ‘A logic simulator simulates HDL code. It can report whether ae expectation, and cam Giayly waveforms to help qq ; 7 iler for hard : i se tool is similar to a compiler for hardware tha A sic ae rary of gates called standard cells to mid while meeting some timing constraints. ™ i ll is called a module. The inputs and out ee aia ‘aC program and bit widths are given fir ball Taternal signals must also be declared in a way analogous to variables. ‘The processor is described hierarchically using structural Verngl upper levels and behavioral Verilog for the leaf cells, ‘The datapath is specified structurally in terms of wordslices, ih jn turn described behaviorally. hom Circuit design is concerned with arranging transistors {0 Petr particular logic function in given circuit design, we can estimate! delay and power ; Because a transistor gate is a good insulator, it can be modeled s capacitor C. When the transistor is ON, some current / flows 7 souree and drain, Both the current and capacitance are prepo™ the transistor width. ‘The delay of a logic gate is determined by the current that ‘itcan and capacitance that itis driving, as shown in Fig. 1.27.1 for one im" driving another inverter. The capacitance is charged °F according to the equation : 35 (EC-7)C 4 x ¥, @ ‘pp fre fi a GNP © rigs ats ad power (@)inwertar pai, () transistor level Fig. 1.271, Cirit delay S00 Purrent during switching, (c) static leakage model showing capacitance © ‘current during quiescent operation. |. Tfanaverage current Iis applied, the timer to switch between Oand Von is t= WV (1.27.2) T Hence, the delay increases with the load capacitance and decreases with the drive current. One of the goals of circuit design is to choose transistor widths to meet delay requirements. 5. Energy is required to charge and discharge the load capacitance. This is called dynamic power because it is consumed when the circuit is actively switching. 6 The dynamic power consumed when a capacitor is charged and discharged at a frequency fis Pamanie= CVonf -(1.27.8) 7, Evenwhen the gate is not switching, it draws some static power. Because an OFF transistors leaky, a small amount of eurre tI ay en power and ground, resulting in a static power dissipation of between Prac = I, Yop (1.27.4) Que 1.28, | What do you unders: aint id by floor planning in physical36 (EC-7)C 1. Physical design begins with a floorplan. The floorplan es area of major units in the chip and defines their relative patty 2. The floorplan is essential to determine whether a proposed 4a fit in the chip area budgeted and to estimate wiring lengthy eh congestion. Wit | 3. An initial floorplan should be prepared as soon as the logic j defined. As usual, this process involves feedback. logic ‘Bony 4. The floorplan will often suggest changes to the loge microarchitecture), which in turn changes the floorplan, (aj 5. The challenge of floor planning is estimating the size of each unit, proceeding through a detailed design of the chip. With 6. Fig. 1.28.1 shows the chip floorplan for the MIPS processor inelyg:, the pad frame. The top-level blocks are the controller and datapath, 100 pads ips 48m) contr bight determine rom assotx 3 Asse with matches comity datapath 7 sirng canna 25 treks = 2004 : g}) 5 | 8/8 “datapath 3 & i Pl 25501 x 13202 i (4M) BS bitsie +1 tipper ow +3 dca rom = row 108 row = 15008 eight ‘ih dterined rom slic plan Fig. 1.28.1. MIPS floorplan. | 7. Awiring channel is located between the two blocks to provide of route control signals to the datapath. the cl to the pairs on inders are Vpp 9% Lhe standard cell based design is one of the most provalent full custom "design styles which require development of full custom mi co 2 Differentlogc cells are developed, characterized, and stored ina stand: cell library. including inverters, 3. Atypical library may contain a few hundred cells i 2 NazeH gates, NOR gates, complex AOI, OAI gates, D-latches, and flip- flops. 4. The different gates can have standard size, size so that designer can choose the proper size speed and layout density. 5, Each cell is characterized according to several different characterization categories including, a. Delay time versus load capacitance. double size and quadruple to achieve high ciscuit b. Cell data for place and route. ¢. Fault simulation model 4. Timing simulation model e. Maskdata £. Circuit simulation model 6. To enable automated placement of the cell: i , s and routing of inter- connections, each cll layout is designed with a fixed herint, ws thar ‘number of cells can be abutted side by side to form rows. 7 7 i ic ° ‘The power and ground rails typically run parallel to the upper and lower boundaries of the cell, thus, neighbori bus and a common ground { acighboring cells share a common power 8. Theinput and output pis ofthe cell, itput Pins are located on the upper and. lower srioe 10. Betw een cell rows are channels for dedicated inter cell routing.eee 380-7 ¢ EC-1) C 11. The Introduction to Vig . 39 physical desi, 1 D placed into reeeinnad layout of logic cells ensure that when celle Mee ; — aatanonly nae lcon wale be abutted side by side, po Bht are matched and neighbouring cells ay 5, Maltpl hips are anu tured sata ratio eee Sean ground lines in each row ede natural connection for power and | senha ‘masking and implant steps. 12. Standard cell : : sae de ec based desi , iced into dice (chips) and packaged. each correspondis jd dation approach consists of several macro-blocks, 6. Processed wafers are sliced into dice (C™D® ire Ys pede an clock generator, specific unit of the system architecture such as, 7. The wire-bonded package uses thin gold wire onnect Pes a re, the lead frame in the center cavity of the package. i i |. Te capable of handling high- & Chips are tested before being sold. Testers ae Corin self-test Standard-cell Row U it} Routing Channel T I Routing Channel Routing Channel Routing Channel Fig. 1.29.1, A simplified floorplan of standard-cells based design.) 13. After chip logic design is done using standard cells from the library, the most challenging task is to place the individual cells into rows and interconnect them in a way that meets design goals in circuit speed, chip area, and power consumption. Many advanced CAD tools for place and route have been developed and 14. used to achieve such goals. Que 1.26. | Write a short note on fabrication, packaging and testing of VLSI chip. |. Once a chip design is complete, 2. Tapeout gets it’s from the old practice of writing a: specification of masks to magnetic tape; today, the descriptions are usually sent to manufacturer electronically. 3, ‘Two common format descriptions are the Caltech Interchange Formst (CIF) (mainly used in academia) and the Calma GDS. [Stream Format (GDS) (used in industry). 4, Masks are made by etching a pattern of chrome on @ electron beam. it is taped out for manufacturing. glass with speed chips cost millions of dollars, so many features to reduce the tester time required. ©o0A. Concept Outline : Part-1 B. Long and Medium Answer Type Questions GONCEPT OUTLINE : PART-1 Delay is the time when the output reaches Vp/2. ‘The solution of the differential equation which describes the output voltage as a function of time is called the transient mse. ‘The gate that charges or discharges a nodes called the driver and the gates and wires being driven are called the load. + A timing analyzer computes the arrival times, j.c., the latest time at which each node in a block of logic will switch. ‘The “slack” is the difference between the required and arrival times. Positive slack means that the circuit meets timing. Negative slack means that the circuit is not fast enough. A. Concept Outline : Part-2 B. Long and Medium Answer Type Questions 40 (EC-7) C We begin a few definitions illustrated in Fig. 2.1.1. : B08 tothe eee ime Maximum tie from theinput crossing sony ne i fom Maen 5 Time fora waveform to rise from 20 % to 80 % of its senda ce bite fora waveform to fall trom 80 % to 20 % of ita Rage rate, t,.= (+12.a: 8. Rise/fall times are also sometimes called slope or edge rate. Propagation and contamination delay times are also called max-tim| and min-time respectively. an inverter. 1. Fig. 2.2.1(a) shows an inverter X, driving another inverter X, at th 2 end of a wire. Suppose a voltage step from 0 to V,,, is applied to node A and we Wi to compute the propagation delay, t,,, through X,, i.e., the delay the input step until node B crosses V7, ‘These capacitances are shown in Fig. 2.2.1(6). Fig. 2.2.1(c) shows equivalent circuit diagram in which all the capacitances are lun intoa single C,,,. Before the voltage step is applied, A = 0. N, is OFF, P, BeVpy- ‘After the step, A = 1. N, turns ON and P, turns OFF and B toward 0. is ON, Compute the step response (or transient response) df 43 (EC-7) C VLSI Design put & The rate of change of the voltage V, at node B depends on the output The refance and on the current through Ny Ce EP I, A220) yppose rensstors ob 1s. The current dt ors obey the long-channel models. tienda ios ea bey fp linear or saturation region. The gate feat Ves the Ec Sn is at V,, Thus, V,,= Vp 20d feat V,, the source is at 0, vee Pe nitially, Vs, Voo> Vn Vor 80s 38m aturation. ® x1 PL G my a= Cant Cag + : ty Ont Con GUAR CapaetaAl - for inverter delay caloulations: 8 AsV, falls below V,,.- VN, ent rs the linear region. The differential yn governing V, is given by, YY, * My iB —_— z s Va>Von-V, at ~C. vy (2.2.2) (%e0-v.-%8}¥, 3 Ve a = i 2 4 6 Qn sf ‘Tristate, Multiplexer I : : J 7 4 also depends on the ratio of diffusion capacitance 7. The parasitic delay: gate capacitance. FRR 4 sing ovcittator is constructed from an odd number of inverters, as shown in Fig. 2.10.1. Estimate the frequency of an Nestage ring oscillator. : & B= 53 Fig. 2.9.1. Logical gates sizéd for unit resistance. 3. Fig. 2.9.1 shows inverter, 3-input NAND, and 3-input NOR gates with transistors widths chosen to achieve unit resistance assuming pMOS transistors have twice the resistance of nMOS transistors. +4. The inverter presents three units of input capacitance. The NAND presents five units of capacitance on each input, so the logical effort is cai 5/3. 5. Similarly, the NOR presents seven units of capacitance, so the logical WiglatOG Ringweanaee effort is 7/3. This matches our expectation that NANDS are better than NORs because NORs have slow pMOS transistors in series, ‘The logical effort of the inverter is g = 1, by definition. Table lists the logical effort of common gates The electrical effort of each inverter is also 1 because it drives a single identical load. The parasitic delay is also 1. Gate Type ‘Number of Inputs gq ‘The delay of each stage isd =gh +p=1+1=2. aati nigel ee 4 2g An N-stage ring oscillator has a period of 2N stage delays because a TOF i value must propagate twice around the ring to regain the original NAND as | 5/3 molarity. NOR [58 | 73 neeet the period is 7 = 2 2N. The frequency is the reciprocal of ‘Tristate, Multiplexed 2 2 2 Paes XOR, XNOR 44 | 6126 Note that ring oscillators are often used as process monitors to judge if particular chip is faster or slowe: Parasitic Delay : 1. The parasitic delay of a gate is the delay of the gate when it drives zero load. It can be estimated with RC delay models. 2. Acrude method good for hand calculations is to count only diffusion capacitance on the output node. 3. For example, consider the gates in Fig. 2.9.1, assuming each transistor on the output node has its own drain diffusion contact. ‘Transistor widths were chosen to give a resistance of R in each gat® ‘The inverter has three units of diffusion capacitance on the output @ the parasitic delay is 3RC =. In other words, the normalized parasit | delay is 1. than nominally expected. What do you understand by logical effort of paths ? Also give the limitations of logical effort. Logical Effort of Paths; Designers often need to choo sizes for a parti fnoose the fastest circuit topology and gate design. cular logic function and to estimate the delay of the diECDC Delay and Pony ‘a simple method “on the back of an envelope logy and number of stages of logic for a function” Logical Effort pr choose the best topol rae the linear delay model, i allows the designer to quickly est "ae ‘number of stages for a path, the minimum possible delay; forthe ‘en topology, and the gate sizes that achieve this delay. Limitations of Logical Effort : Logical Effort is based on the linear delay model and the simple the making the effort delays of each stage equal minimizes path delay This simplicity is the method of greatest strength, but also results number of limitations : i 3. Logical Effort does not account for interconnect, Logical Effort ig most applicable to high-speed cireuits with regular layouts wher, outing delay does not dominate. Such structured include adders, multipliers, memories, and other datapaths and arrays. Logical Effort explains how to design a critical path for maximum, speed, but not how to design an entire circuit for minimum area gy power given a fixed speed constraint. Paths with non-uniform branching or reconvergent fanout are difficult to analyze by hand. iv. ‘The linear delay model fails to capture the effect of input slope Fortunately, edge rates tend to be about equal in well-designed circuits with equal effort delay per stage. Que 2.12. | Briefly describe delay in multistage logic networks, El Delay in multistage logic networks : Fig. 2.12.1 shows the logical and electrical efforts of each stage ina multistage path as a function of the sizes of each stage. Observe that logical effort is independent of size, while electrical effort depends on size. 1. 2. 8 & = 5/3 h,=h/10 hy = yix ‘Fig. 2.12.1. Multistage logic gate. 3. The path logical effort G can be expressed as the products of the logicl efforts of each stage along the path, G=Tlg, (22) ‘The path electrical effort H can be given as the ratio of the outrit capacitance the path must drive divided by the input capacitaD® presented by the path. 55 (EC-7) C ‘VLSI De Costas, (2.12.2) H= Cos Curae une stage efforts of each stage. 5, The path effort Fis the ene : a : F= Mf=Me! : stam eneiing alec dapat ok teh WE RRARNEES PN bya . stage to the capacitance on the path; p= Coan Cotas (2.12.4) * Comput . rts 7, The path branching effort B is the product of the branching effor between efforts between stages. en B= Ib, A212 oduct of the logical, 01 define the path effort F as the pr c 8 now seal, and branching efforts of the path. Note that the electrical effort of the stages is actually BH, not just H. 2126) Fined we the Pith delay 9. Wecan now compute the delay of a multistage network. The Pat Dis the sum of the delays of each stage. It can also be written as the sum of the path effort delay D, and path parasitic delay P = D= Dd,=D,+P D,y= Ef P==p (2.12.7) 10. The product of the stage efforts is F, independent of gate sizes. The path effort delay is the sum of the stage efforts. 11. The sum of a set of numbers whose product is constant is minimized by choosing all the numbers to be equal. In other words, the path delay is minimized when each stage bears the same effort. 2. ue path has N stages and each bears the same effort, that effort must e i aher™ (2.12.8) 13. ‘Thus, the minimum possible delay Z i aa gat puiimam possible delay of an.V-stage path with path effort F Mhisisaxey rman ore isis akey result of Logical Effort. It shows that the mini: the path can be estimated knowing only the number of etagen, path The cat Parasitic delays without the need to assign transistor sizes. fora ante ines Hansformation formula to find the best input capacitance given the output capacitance it drives, fo} (2.12.9) £ BER] exptain tne types of timing analysis delay models.56 (EC-7) C Slope-Based Linear Model : 1. Asimple approach isto extend the linear delay model, reflecting the input slope. ing 2, Linear delay models are not accurate enough to ad of slopes and loads found in synthesized circuits, ap hors My been superseded by nonlinear delay models, ayo Nonlinear Delay Model : 1. Anonlinear delay model looks up the delay from a table load capacitance and the input slope. Daseg, 2. However, they do not contain enough information to delay of a gate driving a complex RC interconnect tei accuracy desired by some users. vi Thoy also lack the accuracy to fully characterize noise event, . Current Source Model : 1 The limit development of current source models. A current source model theoretically should express the current as a nonlinear function of the i a = yn of the input and output. Voltages, 3. A timing analyzer numerically voltage as a function of time for the propagation delay. ’ ‘The Liberty Composite Current Source Model (CCSM) instead cutput current as a function of time for a given input slew rie, output capacitance. 5. The competing Effective Current Source Model i (ECSM) stores voltage as a function of time. The two representations are eq and can be synthesized into a true current source model, integrates the output into an arbitrary RC net a work and tai PART-2 Power : Introduction, Dynamic Power, Static elements thet = oe P(t) consumed or ‘supplied by a! roduct of the and the voltage across the ager current through the element Pit) = : © Mheenergy en HOV. The energy consume: is the integral of the E= [, Pwdt «The average power over time interval Tis Pe Z- tf P(t. act is ity that the clreuit node . ivity factor (a) is the probability t! x node a a tony oto 1, because that is the only time the cireuit conse Peyer arises from the switching of the load it consists of ewitching power and short-circuit power. Payante =P +P yroreciceuit oe «Static powers consumed even when a chip is not switching. Pasue= Cass + Tote + Fatnton)” Vo ‘quea.t4-] a. Instantaneous power P(t) b. Energy () . Average power (P,,,). Refer Concept Outline : Part 2, Page 56C, Unit-2. Examples: Fig. 2.14.1 shows a resistor. The voltage and current are related by Ohm's Law, V = IR, so the instantaneous power dissipated in the resistor is Vine Pe) = Va) _ pr R= POR This power is converted from electricity to heat. 2 Fig. 2.14.2 shows a voltage source V,,,. It supplies power proportional to its current Pyppft) = Ipp(t)V pp 3. Fig. 2.14.3 shows a cay ' ;pacitor. When the capacitor is charged from 0 to Vit stores energy E,, E.= [1mviwat-(c PW yoae =c{vinav = x cv, ° ° . ‘The capacitor releases this energy when it discharges back to 0.+ vad : vote ye What are the sources of power dissipation in Dynamic dissipation due to: sf Fig: 2.14.2. Voltage source. bi <= e dVidt a. Charging and discharging load capacitances as gates switch, b. “Short-circuit” current while both pMOS and nMOS stacks m partially ON. B. Static dissipation due to: a. Subthreshold leakage throug! +h OFF transistors, b. Gate leakage through gate dielectric. ¢. Junction leakage from source/drain diffusions. Contention current in ratioed Putting this together gives the total power of a circuit Peyeamie = Poviing * P, 2. Power can also be considered in act 3. Active power is the power oar + Toate + Zjunee +L, “ananie + Prec circuits. Poe (215) Fentation Von (2153) (2163) tive, standby and sleep modes. work. It is usually dominated by P 4. Standby poweris the stopped and ratioed circ consumed while the chip is doing usefll Power consumed while the chip is idle. Ifclocks#®_ bide uits are disabled, the standby power is stl viable if the chip will idle & and energy to wake up so sleeping i§ for long ei nough. suppl; ‘upplies to unneeded circuits are turned off @ : . This drasti but the chip returer nor stically reduces the sleep power req 59(EC-7) C ee dissipation in CMOS Explain the components of Power circuits. rea 2.16.1, ifthe input Static dissipation + MOS transistor is i inverter in Fig. dering the static CMOS im shown in, conti eraonociated nMOS transistor is OFF and the p) ON. The output voltage is Vp of logic ‘l” : When the input = 1’, the associated nMOS transistor ON and the pMOS transistor is OFF. The output voltage is Ovolts (GND). Note that one of the transistors is always OFF when the gate isin either Note th oie states, Ideally, no current flows through the OFF transistor so the power dissipation is zero when the circuit is quiescent, i.¢., when no transistors are switching. os Zoro quiescent power dissipation is principle advantage of CMOS over competing transistor technologies. However, secondary effects including C; Veo. The delay, using a a-power law model, is given by t= us, the EDP is ChagV" oo Von -V.¥ Differentiating with respect to V, ‘op and setting the result to 0 gives the voltage at which the EDP is minimized. Veen = -V, 3-a EDP = k ~ Minimum Energy Under a Delay Constraint : In practice, designers generally face the problem of achieving minimum energy under a delay constraint. ‘The best supply voltage and threshold for operation at a given delay is where the delay and energy contours are tangent. For a given supply voltage and threshol logic and sizing choices Energy under a del: about half of ld voltage, the designer can make ‘that affect delay and energy. ‘y constraint is also minimized when leakage is dynamic power.Anewen | : 1. VLSI design used to be constrained by the number of ty, could fit on a chip. Extracting maximum speed from maximized overall performance. S 2. Now that billions of nanometer-scale transistors fit on designs have become power constrained and the most ¢ 2 chi seen is the highest performer. This is one of the facta design i «industry's abrupt shift to multicore processors,” “al A. Microarchitecture : 7 1. Energy-efficient architectures take advantage of the trocar principles of modularity and locality. iy] 2. The processor performance grows with the square of transistors. “ook othe i 3, Building complex, sprawling processors to extract the lat instruction-level parallelism from a problem is a highly ineffici energy. 4, Microarchitectures are moving toward larger numbers of simpler seeking to handle task and data-level parallelism. Smaller have shorter wires and faster memory access. 7 5. Memories have a much lower power densit; i ve om) ' ty than logic because} activity factors are miniscule and their regularity simplifies 6. _ Special-purpose functional units can offer. s P i an order of magnitude energy efficiency than general-purpose ae 4 B. Parallelism and pipelining: 1. Parallelism and pipelinia ; ing have been effe wi consumption, as shown in Fig. 3.2.1. offekive ware tela tr oo f hE EB E #72 (a) = [HIE BLA Bi} () f £ ha 5 Fig. 82:4, Functional waite tayo 1. Fundtonal units :(@) normal, (parole: 60 be the voltage co nergy efficiency: ‘llelism offers a sligh a son leakage is unimportan DOT an the pipeline reeis'er®- * Tem a tial fraction of total power, pipelining 9 Teakage io oo ne N times as much : ees preferable because the parallel hardware has eee it the tential Now that Vpp is closer to the best energy-deley point, the po 7. Neply reduction and enerey saving are diminishing. jodes + Power Management Mi : : i aa designers have now Jearned they must turn offportions of the chip ; hen ‘they are not active by ‘applying clock and power gating. 2, Many chips now employ @ variety of power management modes giving @ trade-off between power savings and wake-up time. 3. The power management modes are shown in Fig. 3.2.2. co HFM co LFM cuc2 c4 cé Core Voltage I i i ao Core Clock = SU Ju OFF OFF OFF pu JU J i OFF OFF 11 Caches |_| Hi Flushed Flushed OFF L2 Caches Partial Flush OFF Wake-Up Time active active om mom ay <1ne <30p8 <100y8 Power i a - -_ fe 4.7 In the low frequency mode, the clock drops as slow as 600 MHz while the power supply reduces to 0.75 V.5. In sleep mode Cl, the core clock is turned ofp flushed and power-gated to reduce leakage, but grt the to active state in 1 microsecond. ep 6. _Insleep mode C4, the PLL is also turned OFF, In sleep mode C6, the core and caches are al pop, power to less than 80 mW, but wake-up time riggs mE : VLSIDe! ‘The sum of width and spacing, width ratio tw is called the aspect rati at. PART-2 \» Impact, Interconnect Engineering, Logical CONCEPT OUTLINE: PART-2 ‘The wires inking transistors together are calied ‘© Whenone wire switches, it tends to affect its neighbonn capacitive coupling, this effect is called crosstalk." Interconnect delays are estimated using the Elmore ; based on the resistance and capacitance of the a driver and load, ‘The wire delay grows with the square of its le “Fig. 83.1. Interconnect geometry. WESFAT | Bricty discuss about interconnect modeling. |. Awire isa distributed circuit with a resistance and capacitance per unit length. Its behaviour can be approximated with a number of lumped ngth, slap elements. are often broken into shorter segments driven by rp 2. Three standard approximations are the L-model, x-model, and T-model, * Vast numbers of wires are required to connect all thetr 50 named because of their shapes. 80 processes provide many layers of interconnect packaid together. ‘The capacitive coupling between these tightly packed be a major source of noise in a system. These challenges are managed by using many meta li various thicknesses to provide high bandwidth for sho 3, Fig.3.4.1 showshow adistributed RC circuit is equivalent to N distributed RC segments of proportionally smaller resistance and capacitance, and how these segments can be modeled with lumped elements. 4, As the number of segments approaches infinity, the lumped approximation will converge with the true distributed circuit. a 'N Segments wires and lower delay for longer fat wires, | R RN RN RN RN ie <> We —000 POR Ee R R R2 R/2 sara Y= Oe £ Cia yer Je L-model a-model el BES] write « short note on wire (or interconnett) 5. ‘The L-model is a poor choice becat aber of ts L poor choice because a large number of segments are i 6 The x-model is much better. Three cient to give results z Fig. 3.3.1 shows a pair of adjacent wires, hte ke segments are suffi give res . neighbours and 1 fe 1, thickness t, and spacing 5% 7. The T-model is comparable to the x-model, but produces a circuit with ea tlength spacing model conductnglayer ange “electric of height & between th ‘one more node that is slower to solve by hand or with a circuit simulator.72 (EC-7) C & Therefore, itis common practice to model long wires with a3.5 winodel for simulation. Ifinductance is considered, itis place; with each resistor. in How to compute the resistance of wire Or intercon, it ancé typically have sheet resistances nee and up to sever higher sheet resistance. Large unsilicided. RE doping and thus even highe is 1. The resistance of uniform slab of conducting material can be 3. Wells have on top nS som wells oF unsilicided polysilicon. ee expr resistors = pe ot . : tw | (85 ‘where pis the resistivity. This expression can be rewritten ag l t R= Re itn] terion where, Re js the sheet resistance and has units of (square, _| 2 To obtain the resistance of a conductor on a layer, multiply the si! — eae by eae ee oie wig. 2:5:2. Copper barrier layer and dishiig. resistance of -o shapes in Fig. 3.5.1 is equal beca atti aaa a tecwidth ratio is the same even though the sizes are ‘liferent 9 Contacts and vias Rare teeta which is dependent on "he 3. The resistivity of thin metal films used in wires tends to be hi contacted mat a | because of scattering off the surfaces and grain boundaries. 10. ool ceases be used to form low-resistance connections, a5 own in Fig. 3.5.3. Joos, jeafe >| Fearn peattams ataright angleor reverse, asquare array of contacts : ance rally required, while fewer contacts can be used when the flow is ‘ - L in the same direction. y y t t - | 1 Block 4 Block R=R,Ww) R=R, (2/2w) | Fig: 3.5.3: Multiple bias for low-resiataiiée connections, = R, (Uw) a : mnectic ca Wig. S81, "Two conductors with a 8 36. | Compute the sheet resistance of a 0.22 pm thick Cu wire shown in Fig. 3.5.1, co] 65 nm process. Find the total ‘i hown in Fig. 3.5.1, copper must be surrounded by fy resistance if the wire is 0.125 nductivity diffusi ‘i a i wide and 1 om ae eed ee barrier that effectively reduces the wire a mum long. Ignore the barrier layer and dishing. ste] nd hence raises the resistance. Moreover, the P can cause dishing that thins the metal. 5, If the average barrier thi t . 5 F |. The sheet resistance is oe 8s is t.., and the height is redue - g | R, = 2:2x10°Q-m _ 9 199, 0.22x10%m ~ 0 20%/ square Ra ae Ft _. i 68) 2 ‘ 7 m 1 moo a ‘The total resistance is aah ~ aera) (WO Blair) ‘ JT4(EC-7).C 1000um 0.125.m FER ow to model the capacitance of wires? R= (0109/0) =8009 1. Anisolated wire over the substrate can be modeled ag, j aground plane. conde, 2. The wire capacitance has two major components: the Y capacitance of the bottom of the wire to ground antl | ‘tance arising from fringing fields along the edge of with finite thickness. 4 3. In addition, a wire adjacent to a second wire on the exhibit capacitance to that neighbour. These effects ee Fig. 3.7.1. 4. Theclassic parallel plate capacitance formula is c= Soul t h ; The ngngcpaitneismor complicated compute Oe appealing srrecnaton eats lane conductor bo 2 egy shown in Fig. 3.7.2. ana 6. The total capacitance is, t assumed to be the sum of a parallel pis , svi anda apt of ait? I. results in an expressi itance that is 10 % for aspect ratios ees aa gesae aie 75 (EC-7)C . Half Cylinders Parallel Plate t wg, ee (8.7.2 cxtal| 42+ ah , [ah(2h 2h, [2h(2h 2 ofthe ana )) ‘An empirical formula that is computationally efficient and relatively accurate is as as c= eu s.ac7+3.06(2) +1.06( ] (8.7.3) which is good to 6 % for aspect rat oless than 3.3. These formulae do not account or neighbours on the same layer oF higher layers. ‘A cross-section of the model used for capacitance upper bound calculations is shown in Fig. 3.7.3. . ‘The total capacitance of the conductor of interest is the sum of its capacitance to the layer above, the layer below, and the two adjacent conductors. Soe Layern +1 hg, ¢, ; HH | Layer n (3.74)mone Hr How to model the inductance of wires ? 1. Most design tools consider only interconnect resistance and ca Tatanes is difficult to extract and mode, 8 engineers prefer (one | in such a way that inductive effects are negligible. Nevertig’®| aoa ee needs to be considered in high-speed designs for widy | such as clocks and power busses. Mig | 2. Current flowing around a loop generates a magnetic field propor. the amount of current. to the area of the loop and 3 Changing the current requires supplying energy to change the maga field, This means that changing current induces a voltage propor te the rate of change. The constant of proportionality is eal ye inductance. a Vela (Bay | 4, Inductance and capacitance also set the speed of light in a medi Even if the resistance of a wire is zero leading to zero RC delay, | speed of light fight-time along a wire of length with inductance a capacitance per unit length of L and Cis | t= WIC 889) 5. Jf the current return paths are the same as the conducts on whi electric field lines terminate, the signal velocity vis. 1 lie "TEE ase aa ‘where, u, is the magnetic permeability of free space (4x 10-7H/m) a | _ eis the speed of light in free space (3 x 10° m/s). 6. Changing magnetic fields in tum produce currents in other lops. Hen signals on one wire can induetively couple onto another, this is cal | inductive crosstalk. 7. The inductance of a conductor of length / and width w located aheilt ‘above a ground plane is approximately Le (Heyy Sh, 2 (38 ent “a ’ assuming w < fyand thickness is negligible. 8. Inductance depends on the entire looy sil) depend 0 p and therefore cannot be eet into sections as with capacitance. Its therefore imprest! attract the inductance from a chip layout. TEEGIA] Write a short note on skin effect. mae impedance Z Fe arent oe loge Gominted by inden. * frequency, © im hee ‘The inductance is minimized: if the — flows: a vnductor closer to the return Pat / ; ea in cross-sectional area of i skin effect can reduce the effective nigh : ‘thick . Seaductors ed raise the effective resistance at frequency. ‘The skin depth for a conductor is - ze (3.9.1) 8= You ‘pheve, wis the magnetic permeability of the dielectric (normally same sin free space, 4x 10” H/m). “itt ‘importance is the highest frequency with sign fica . ‘The fee Fourier transform ofthe signal. hi snot the chip operat ‘but rather is associated with the faster edges. % rise/fall time as the signal has frequency, ‘Asine wave with the same 20-80 . period of 8.651,, Therefore, the frequency ‘associated with the edge can be approximated as 2n = (8.9.2) ©" 8.68, where, ty is the average 20-80 % rise/fall time. GuesAG | Determine the skin depth for a copper wire in a chip with 20 ps edge rates. ‘Answer 1. According to eq. (3.9.2), the maximum frequency of interest is on _ : 8.65% 20 ps { = 3.6 x 10" rad/s = 5.8 GHz 2. According to eq. (3.9.1), the skin depth is 2(2.2*10*Q-m) (8.610 rad/s) (4nx107 Him) = 0.99 um qtr] ‘Using the lumped models examine the delay and energyhave an average activity. by the layer of metal. Answer _ a 2, 3. Que 8.13. | Explain the impact of wires on crosstalk (or noise). Answer a Interconnet increases circuit delay for two reasons, Firet, capacitance adds loading to each gate. Second, long wires have Tesistance that contributes distributed RC delay or flight time, The Elmore delay of a single-segment L-model is RC. Asthe nt segment of the L-model increases, the Elmore delay decreases RC/2 The Elmore delay ofa xor T-model is RC/2n0 matter ‘Segment are used. Because both wire resistance and wire capacit wire delay grows quadratically with. length. ‘Using thicker and wider: wires, lower-resistance metals ‘such ag and lower-dielectric constant insulators helps, but Tong nevertheless often have unacceptable delay. =“ Polysilicon and diffusion wires (sometimes called runney resistance, even if silicided. Diffusion also has very’ high Energy: The switching energy of a wire is set by its capacitance. Lo: significant capacitance and thus require substantial am ance increase with 8) have bi capartan | ng wires | lount of energy ‘There are (20 mm) /(250 nm) = 80,000 tracks of metal across the die which 40,000 are occupied. ' ‘The wire capacitance is (0.2 PF/mm) (20 mm) (40,000 tracks) = 1602 The power is (0.1) (160 nF) ( 1.0 V)? (3 GHz) = 48 W As shown in Fig. 3.13.1 win irae | agian Te May have capacitance to their adja When wire A switches, i ittends to bring its nei -withitat Feapant ofeapacitive coupling alsocallederaceere oe | VLSI Design 79 (EC-7) C et a ee a etnce dominates and crosstalk i large loads, the load capacita 0 om painpirnt ‘Conversely, crosstalk is very important for long wires. A HH B Cena - Coa ms ‘Fig. 3.19.1. Capacitancés to adjacent neighbour and to ground. Crosstalk Delay Effects : sirection oft ire and its neighbour are switching, the direction of the porn penne rina dh ier delay of the switching. Table 3.13.1 summarizes this effect. ‘The charge delivered to the coupling capacitor is Q = C4 AV, where AV is the change in voltage between A and B. IfA switches but B doesnot, AV = V,,,. The total capacitance effectively seen by A is just the capacitance to ground and B. Ifboth A and B switch in the same direction, AV=0. Hence, no charge is required and C,, is effectively absent for delay purposes. IfA and B switch in the opposite direction, AV= 2V,,,, Twice as much charge is required. Equivalently, the capacitor can be treated as being effectively twice as large switching through V,,,. This is analogous to the miller effect, ‘The Miller Coupling Factor (MCF) describes how the capacitance to adjacent wires is multiplied to find the effective capacitance. Table: 3.13.1. B av Cs MCF Constant Vip CyatCwy | 1 Switching same directionasA | 0 Cus 0 | Switching opposite toA Vp | Cyut2C,y | 2 Crosstalk Noise Effects : introduces noise as B parti Perpetrator and B the victim. Ifthe victim is floating, we can model the it iti : a circuit. any in Ranting, wo uit as a capacitive voltage im noi i i oes ise, as shown in Fig. 3.13.2, AV. is (8.18.1)Fig. 3.18.2. Coupling to floating victim, 3. Ifthe victim is attively driven, the driver will supply eu and reduce the victim nose, We model the drivers as resis 2 in Fig. 3.13.3. * th 4. The peak noise become dependent on the time constant. Tatio aggressor to the victim het ©, 1 Ay, = __* ee Cyan + Cay Le (a Raggresor hope ay, y v Pigi8'1313. Coupling to driven vietim. where, ~PamlCnae*Cag) Retin Cynd-v + Cag) 3 10 Aggressor Vietim (Undriven):50 % es Nietim (Half Size Driver: 16 % Victim (Equal-Size Driver: 8%. oe. Vietim (Double-Size Driver 4* | — tO 240 280 320 960 400 ig: 88:4. Wavotorms of coupling noise. 40 80 81 (EC-7) C ‘yLSIDesign coupling when the aggressor is driven 13.4 shows simulat : ven 5. ith a unit inverter. The een it “a werter of half, i ize of t ‘ea equal, or twice the size of . , ae hhen the victim is floating, the noise remains : Ce ees So neon, the driver restores the vietim. Larger (faster) Trivers oppose the coupling sooner and result in noise that is a smaller percentage of the supply voltage. Que 8:14 | Discuss the parameters selected by the designer to trade off delay, bandwidth, energy and noise. ewer | 1, Asgatedelays continue to improve or even get slower, wire engineer’ integrated circuit design. 2, The designer selects the wire width, spacing, and layer usage to trade off delay, bandwidth, energy and noise. 3. By default, minimum pitch wires are preferred for noncritical interconnections for best density and bandwidth. 4. When the load is dominated by wire capacitance, the best way to reduce delay is to increase spacing, reducing the capacitance to nearby neighbours. This also reduces energy and coupling noise. When the delay is dominated by the gate capacitance and wire resistance, widening the wire reduces resistance and delay. However, it increases the capacitance of the top and bottom plates. 6. Widening wires also increases the fraction of capacitance of the top and bottom plates which somewhat reduces coupling noise from adjacent wires, However, wider wires consume more energy. 7. The wire thickness depends on the choice of metal layer. The lower layers are thin and optimized for a tight routing pitch. 8. Middle layer are often slightly thicker for lower resistance and better current-handling capability. 9. Upper layers may be even thicker to provi is P v provide a low-resistan grid and fast global interconnect. eistanee power Que 3.15. | Deseribes how repeaters can be used to break a long wire into multiple segment: Mee penne es oe such that the overall delay becomes a Answer 1. Both resistance and capacitance i J pacitance increase with wire length /,sothe RC“ delay of a wire increase with /2, as shown in Fig. 3. ie while long wire delays remain constant ‘ing has become a major part of‘The delay may be reduced by splitting the wire into 1y inserting an inverter or buffer called a repeater to a wire, as shown in Fig. 3.15.1(6). The new wire involves N segments with RC flight time of ¢y delay of, ifthe numberof segments are proportional gt fy the overall delay increase only linearly with. 7 Wire Length:! ively Ver. @ N Segments (segment. SSS ia ie iN Driver Repeater 7 Repeater Repeater Receiver | Cy | Fig. 8.16.1. Wire with and without repeaters,! Suppose a unit inverter has resistance R, gate capacitance (, ax diffusion capacitance C,,,.A wire has resistance R, and capacitance | per unit length. Consider inserting repeaters of Wtimes unit size, * L Rwy AWWW\- Hm Testo" Fig. 8.15.2, Equivalent circuit for segment of repeated wird.) | Rig. 3.15.2 shows a model of one segment. The Elmore delay ofthe | repeated wire is * L (ef 4 t,, = N| =| C,—+Cw(+P, ) R—|“*—+¢ew (3.15) i" [2 Reno w te { Differentiating eq. (3.15.1) with respect to N and W shows that thebet | length of wire between repeaters is | 1 _ pROasP) | 4. (PRCO+e,) (8.152) N RC, | The delay of an FO4 inverter is 5RC. Assuming P._, «0.5 using fli | transistors, eq. (3.15.2) simplifies to a i POs wy = 0.77204 a RC, ‘The delay per unit length of a Properly repeated wire is .(g.a68) 83 (EC-7)C vaste (8.15.4) 4s «(9+ (OU+P,,)YROR_C, = 167 FOAR,C, oe ransist a achieve this delay, the inverters should use an MO’ idth of . « pee (8.15.5) Welne L 2 In other words, repeaters sized for minimum delay energy of an unrepeated wire. [ERAG] Explain the various crosstalk control schemes. ‘The capacitance crosstalk is proportional to the ratio of coupling capacitance tototal capacitance. ‘There are several approaches to controlling this crosstalk : i. Increase spacing to adjacent lines. Shield wires. Ensure neighbours switch at different times. Crosstalk cancellation. z ‘The easiest approach to fix a minor crosstalk problem is to increase the spacing, Ifthe crosstalk is severe, the spacing may have to be increased by more than one full track. Insuch a case, itis more efficient to shield critical signals with power or Ground wires on one or both sides to eliminate coupling. An alternative to shielding is to interleave buses that are guaranteed to switch at different times, For example, if bus A switches on the rising edge of the clock and bus B Euriches on the falling edge of the lock, by interleaving the bits ofthe 'wo busses you can guarantee that both nei i creams rican arantee th neighbours are constant during ‘This avoids the del: lay impact of coupling. Fig. 3.16. ires shi (a) enone side BeamPact of coupling. Fig. 8.16.1 shows wires shielded ) on both sides, and (c) interleaved. >...Vaa 0 1 gnd @% 83 Vay and twisted differential signaling. Each technique seeks to, cma 10. HL Fig. 8.16.1. Wire shielding topologies. Alternatively, wires can be arranged to cancel the effects of crogs, ‘Three such methods include staggered repeaters, charge com, 1% amounts of positive and negative crosstalk on the victim, effet producing zero net crosstalk. a Fig. 8.16.2(a) shows two wires with staggered repeaters. Each sogme, of the victim sees half of a rising aggressor segment and half off aggressor segment. Although the cancellation is not perfect because delays along the segments, staggering is a very effective approach, Fig. 3.16.2(b) shows charge compensation in which an inverter transistor are added between the aggressor and victim. The transista connected to behave as a capacitor. When the aggressor rises and con, the victim upward, the inverter falls and couples the victim downward eT L ST L Vietim | Aggressor _/| a ) Fig. 8.16.2, Crosstalk control schemes. TERE Write a short note on regenerators. L in series with wi limited to ‘aters are placed in series with wires and thus are Fepatetional busses, An alternative is to use regeneration (also called poosters) placed in parallel with wires at periodic intervals, as shown in Fig. 3.17.1. Long Wire Regenerator When the wire is initially (’ the regenerator senses a rising transition and accelerates it. Conversely, when the wire is initially ‘I’ the regenerator accelerates the falling transition. ‘Long Wire 4. Regeneration generally uses skewed gates to sense a trangition.and LO-skew gate does the reverse. regenerator. 6. When the wire begins to rise, the LO-skewed NAND gate defag, transition midway and turnson the pMOS driver to assist, | 7. The normal-skew inverters eventually detect the transition ag4 | node x, turning off the pMOS driver. | 8. When the wire begins to fall, the H-skewed NOR gate turns ai nMOS to assist. te Explain the method of logical effort to give inci, about designing paths with interconnect (or wires). Interconnect complicates the application of logical effort because ty wires have a fixed capacitance. 2. The branching effort at a wire with capacitance C,,,, driving a gate lag, Of Cys, 18 Cou, + Cin)” Cyue: This branching effort is not constan, depends on the size of the gate being driven. 3. Every circuit has some interconnect, but when the interconnectis shat (Coins << Cy, it can be ignored. Conversely, when the interconnect is long (Cyn, >> Cpu); the gate at the end can be ignored. 4. ‘The most difficult problems occur when C,,,, > C,,,.: These mediun length wires introduce branching efforts that are a strong functions! the size of the gates they drive. 5. Fig. 3.18.1 shows three stages along a path. By writing the Elmore dey and differentiating with respect to the size of the middle stage, we fd the interesting result that the delay caused by the capacitance of ste should equal to the delay caused by the resistance of the stage, OR, +R) = RC, +C,,,,) RC Dynamic Logic Circuits ie Logic Cireuits : Introduction Dynamic Logie Crstse Transistor Cirewits Basic Principle of Pas: jt Outline : Part-1 ag anid Badin Anawer Type Questions Part-2 Synchronous Dynamic Cireuit Techniques Dynamic CMOS Circuit Techniques Domino CMOS Logic i 92C ‘A. Concept Outline : Part-2 220 B. Long and Medium Answer Type Questions (106C - 122C) Part-3 ‘Semiconductor Memories : Introduction DRAM, SRAM, ROM Flash Memory A. Concept Outline : Part-3 B. Long and Medium Answer Type Question: 87(EC-7).C