8-1

CHUNG-YU WU
Chapter 8 Advanced Design Techniques and Recent
Design Examples of CMOS OP AMPs

§8-1 Advanced Design Techniques of CMOS OP AMPs

§8-1.1 Improved PSRR and frequency compensation

∂Vout C gs  ∂I o 1 ∂V  C 1 ∂I o
P.6-26 ≈  + GS1  + gd
∂V ss C I  ∂V ss 2 g m1 Vss  C I 2 g m3 ∂V ss

∂Vout C gd  ∂I o 1  C gs 1 ∂I o
≈ − +
C I  ∂V DD 2 g m3  C I 2 g m1 ∂V DD
1
∂V DD

Where I o represents the input stage bias current.

If I o is independent of V ss and V DD
and the input devices have no body effect.
∂Vout ∂Vout C gd
==> →0 →−
∂V ss ∂V DD CI
Ref.: IEEE JSSC, vol. SC-15, pp.929-938, Dec. 1980
BIAS GENERATOR
+VDD OP AMP

M9 M3 M4 M6
IREF

V- V+
M10 Vo
M1 M2
M8
Io
M11
M12 M7
M5
VBIAS

-VSS
* I REF is generated by using the power supply independent current source.
*V BIAS is nearly independent of V DD and V ss .
*It is better to use separate p-wells for M 1 and M 2 to avoid the body effect.
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*Tracking RC compensation
Conceptual circuits :
+VDD

+
gm1VIN VIN2
+ -
Vos2 MB(M6)
-
Voltage
Mc
source CC
(M10) CL
MA (M8)
(RC)
I KI

-VSS
In the quiescent case ,Vin2=VOS2

Cc
If (W / L) A ≈ [(W / L) B • (W / L)C • K ]1/ 2
Cc + CL
Cc + CL
=> RdsA ≈ ≈ Rc
gm 2Cc

The requires Rc is Rc = 1 / g m2 [1 + (C d + C L ) / Cc ] ≈ 1 / g m 2 [(Cc + C L ) / CC ]

Thus LHP zero=LHP pole P2
and P3 becomes the second pole.
The stability considerations,
P3 ≥ Ado P1

g m1
or Cc ≥ c 1c L
gm 2

allows a smaller gm2 and larger C L

* RdsA ≈ Rc indep of temperature, process , and supply variations.
=>Tracking design to make sure that z=P2
=>No pole-zero doublet problem!
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CMOS Design
+VDD
M1 M3
M5 M8 M13
VBIAS

- M15
+
M9 M11
Vout

M6 Cc
M17
M2 M7 M16

M10 M12 M14

M4

-VSS
* M17,Cc : Tracking RC compensation.
* M9,M11:Sharing the separate n-well.
* VBIAS is not strictly independent of VDD and VSS.

§8-1.2 Improved frequency compensation technique.

Ref.: IEEE JSSC ,vol.sc-18, pp 629-633, Dec.1983
Grounded gate cascode compensation

+VDD

M5 M9
M11 M12
2x 3x
VBIAS1 MB M7

+ -
M13 M1 M2
IBIAS
VBIAS2 Cc
MC1 MC2 M8 5pF Vo
M16 3x

M10 M6
M14 M15 M3 M4 3x

VBIAS1
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MB,Cgs7:low pass filter for high frequency noises.
M8,M9,M10:new compensation circuit.
M11~M16:Bias generator.
Conceptual circuits:
+VDD

2Io CS1 I1 Cc

A
_
gm1
-gm2 Vo
+ Vi
R1 CS2 I1 R2

-VSS
d
Net current in CC (C c V ) enters the second stage.
dt o
The input voltage Vi can’t reach the node A
è * Better PSRR (∵ no low-freq. zero ) , especially PSRR
* Allow larger capacitive loads.
* Slight increase in complexity , random offset and noise.

§ 8-1.3 Improved cascode structure

1. To improve gain:
Ref: IEEE JSSC , vol. SC-17, pp. 969-982, Dec. 1982 ☆☆
+VDD

M1 M2

M9
Vo
Rc Cc
M1A M2A

M7

M4A
M6
M3A
M4
M8
M3
-VSS
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* Substantial reduction in input-stage common-mode range.
* Improved wilson current source is used as the load to improve the balance of the
first stage. +VDD
2. Single-stage push-pull class AB CMOS OP AMP M6
Ref: IEEE JSSC , vol.sc-17, pp.969-982, Dec. 1982 M5
* Inverting mode only. (+ grounded) M7
* Capable of high current driving and M2 M4
BIAS OUT
high voltage gain. IN
* Not a differential-amplifier-based
M1 M3 Cc
OP AMP.

_ M8
+

M10 M9
3. Cascoded CMOS OP AMP with high ac PSRR
Ref: (1) IEEE JSSC , vol. SC-19, pp.55-61, Feb. 1984 -VSS
(2) IEEE JSSC , vol SC-19, pp. 919-925, Dec. 1984
1) Original version
+VDD

200/10 200/10 25/10

Mp2 Mp3 Mp4

1125/10
A Mp5
50/10 Mp7 100/10
50/10
Mp5 Cc Vout
- MN1 MN2 + 100/10
IBIAS
5µA CL

100/10 MN5 42.5/10 MN8

200/10
MN3 MN7 500/10
MN9 100/10 MN4 100/10
42.5/10
MN6
-VSS
Chrarcteristics:
VDD=VSS=2.5V
Input offset voltage 5mV
Supply current 100ìA
Output voltage range -VSS~VDD
Input common mode range -VSS+1.47V ~ VDD
CMRR @ 1KHz 99dB
Unity-gain frequency 1.0MHz
Slew rate 1.8 V/ìsec
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* Better input common-mode range.
* Vic↓è VDSN4↓è IDSN4↓è VA ↑è MN8 is turned on è Vout→-VSS
voltage spike at Vout.
* The possible spike in the settling period.
2) Improved version
+VDD

M7
VBIAS1 M12 M6
M5
M8
VBIAS2 M3
M4

M13 Vout
- + Cc

M1 M2

VBIAS3
M9
M14 M10 M11

-VSS
* M 12 , M 13 and M 14 : Let the drain bias currents of M 10 and M 11 follow
the change of I D7 under positive input common mode voltage.
⇒ No voltage spike at Vout
Also serves as CMFB
* Better PSRR and input common-mode range.
* C c is decoupled from the gate of the driver M 8 .

4.Simple cascoded CMOS OP AMP

Ref.:IEEE JSSC , vol.SC-19 , pp.919~925 , Dec. 1984
+VDD
* Good PSRR
M5 M6 M8
* Reduced input common
VBIAS1 Vout range.
M3 M4
⇒ restrict its applications
Cc
to those which use a virtual
- M1 M2 + ground.

VBIAS2 M5
M9

-VSS
 8-7
5.Single-stage cascode OTA CHUNG-YU WU
Ref.: IEEE JSSC , vol. SC-20 , pp.657~665 , June 1985 ☆☆

+
1 A
T6 T2 T4 T8 T14
T12

T10
In- In+ Out
T1 T3
CL
Io T9

T5 T7

IBIAS
T11 T15 T17
T13
-

T9 ,T10 : Cascode structure

* Output conductance ↓ without any noise penalty and with only a very small
reduction of phase margin.
⇒ Gain↑ no any compensation is necessary.
* Maximum output swing↓

§ 8-2 Advanced Design Techniques on High-frequency Non-differential-type CMOS

OP AMPs
1. Single-ended push-pull CMOS OP AMP
*Current-gain-based design
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+VDD

M8 M9

M5 M6

M14 M13

M15 M7
OUTPUT

M1 M2 M16 M12 CL
INPUT
IB1

M3 M11
M4 M10 -Vcc

TABLE I
Parameter Measured Value
DC-Open Circuit Gain 69dB
Unity0Gain Bandwidth 70MHz
Phase Margin 40o
Slew Rate 200 V / µ sec
PSRR (DC+) 68dB
-
PSRR (DC ) 66dB
Input Offset Voltage 10mV
CMRR (DC) 62dB
Output Voltage Swing 1.5VP
Output Resistance 3 MΩ
Input Referred Noise (@1KHz) 0.54 µV / Hz
DC-Power Dissipation 1.1mWatt
V DD = +3V ; VCC = −3V ; I B1 = 50 µA ; CL=1pF
TABLE II
Bias Current Unity-Gain DC-Open Circuit DC-Power
Bandwidth Voltage Gain Dissipation
25 µA 50MHz 70dB 0.55mW
50 µA 70MHz 69dB 1.1mW
100 µA 100MHz 66dB 2.2mW
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V DD = +3V ; VCC = −3V ; CL=1pF
2.Low output resistance CMOS OP AMP
* C L is a compensation capacitor
*For low-resistance load
*Smaller maximum output voltage swing.
* I B1 = 50 µA, C L = 1 pF , f u = 60MHz

+VDD

M8 M9

M5 M6
M17

M14 M13 M22

M18
M15 M7

OUTPUT
CL
M1 M2 M16 M12
INPUT
M19 M21
IB1
M11
M3
M4 M10 M20
-Vcc

§ 8-3 Advanced Design Techniques on High-drive MOS Power or Buffer OP AMPs

§ 8-3.1 Efficient Output Stages.
A. CMOS output stage using a biplar emitter follower and a low-threshold PMOS
source follower.

+ VDD

VBIAS

Vout

Vin

- VSS
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B. Complementary class B output stage using compound devices with

common-source output MOS.

+ VDD

MP

A
Vout
Vi

MN

- VSS

§ 8-3.2 High-drive power or buffer CMOS OP AMPs

1. Large swing CMOS power amplifier (National Semiconductor)

+ V DD

+ M6
V IN M16 M9
-
A1
-
+

C0 V OUT

M8 M8A M10

-
+

A2
VBIASN M17 M13 VBIASN M12 M11
M6A

-VSS
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* Noninverting unity gain amplifier

Vout

+
A1 M6
-

Vi ~
+ V DD

Vin ≅ V out
M 6 provides the negative feedback
* A1 , M 6 and A2 , M 6 A form a class AB push-pull output stage.

* Full swing from + VDD to − V SS

* M 9 , M 10 , M 11 , and M 12 form a current feedback to stablize the bias current

of M 6 and M 6 A .

Offset in A1 ,e.g. VinA1 − ↑⇒ VoutA1 ↓⇒ I DM 6 ↑ and I DM 9 ↑⇒ I DM 11 ↑

and I DM12 ↑⇒ VGSM 8 A ↑ and VinA 2 + ↓ ⇒ Vout ↑, i.e.

VinA1 + ↑⇒ Vout ↓⇒ VinA1 − ↓ (virtual short between + and -) ⇒ VinA 2 − ↓

througt M 8 ⇒ All the bias voltage and current are restored to the normal
values and the offset is absorbed by M 8 A .

Since the current feedback is not unity gain ,some current variation in
transistors M 6 and M 6 A still exists.

VCC

M3 M4 M6

MPC
CC
VIN VOUT

M1 VSS M2

VBIASN

M5
VSS
 8 - 12
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Large positive common mode range allows M 6 to source large amount of

current to the load. (because Vin ≅ V out )

The maximum VGS 6 which M 1 and M 2 still in the saturation region is

VGS 6 max = −( VDD − ( VIN − VGS 1 + VDSAT 1 )) = −( VCC − VIN + VTH 1 )

⇒ VTH 1 ↑⇒ VGS 6 max ↑⇒ I DM 6 ↑

(1). Threshold implant to increase VTHO1

(2). Negative substrate bias − V SS to increase VTH 1

+ VCC

MP3A
M3H V BIASP
M5A
M4H MP4
+
VIN M16 M3 M4 MP5
- M9 MP4A
M6
C0 MP3 MRC M8A
MRF
CC CF M10 M1A
M2A
M1 M2
MN3A
M8
MN4 M5A
M4A M3A
MN5A
M17 M5 MN3 M13 M12 M11 MN4A M4HA M3HA
V BIASN

- VSS

V OUT

* The input stage is not shown in the diagram.

* M 16 , M 8 , M 17 form the second stage with C D the Miller compensation
capacitor.
* If Vout → −V SS , VDSM 5 → 0 and I DSM 5 → 0.

⇒ M 1 , M 2 , M 3 and M 4 are off

⇒ M 3 H and M 4 H are still on to keep VGS 6 ≅ 0V .

Otherwise , M 6 will be turned on.

Similarly, M 3HA and M 4 HA turn off M 6 A in the positive voltage swing

* M P 3 , M N 3 , M N 4 , M P 4 and M P 5 are output short-circuit protection circuitry.

Normally, M P 5 is off.
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When I DM 6 ≅ 60mA, I DMP3 ↑⇒ I DMN 4 ↑⇒ VGSMP5 ↑ .

⇒ I DM 6 is limited to approximately 60 mA.

Table I
POWER AMPLIFIER PREFORMANCE
Parameter Simulation Measured
Results
Power dissipation( ± 5V ) 7.0mW 5.0mW
Avol 82dB 83dB
Fu 500KHz 420KHz
Voffset 0.4mV 1mV
PSRR+(dc) 85dB 86dB
(1KHz) 81dB 80dB
PSRR-(dc) 104dB 106dB
(1KHz) 98dB 98dB
THD VIN=3.3Vp RL=300Ω 0.03% 0.13%(1KHz)
CL=1000 pF 0.08% 0.32%(4KHz)
VIN=4.0Vp RL=15 kΩ 0.05% 0.13%(1KHz)
CL=200 pF 0.16% 0.20%(4KHz)
Tsettling (0.1%) 3.0us <5.0us
Slew rate 0.8V/us 0.6V/us
1/f noise at 1KHz N/A 130nV/Hz
Broad-band noise N/A 49nV/Hz
Die area 1500mils2

TABLE II
COMPONENT SIZES ( µm, pF )
 MI6 184/9 M8A 481/6
MI7 66/12 M13 66/12
M8 184/6 M9 27/6
M1,M2 36/10 M10 6/22
M3,M4 194/6 M11 14/6
M3H,M4H 16/12 M12 140/6
M5 145/12 MP3 8/6
M6 2647/6 MN3 244/6
MRC 48/10 MP4 43/12
CC 11.0 MN4 12/6
M1A,M2A 88/12 MP5 6/6
M3A,M4A 196/6 MN3A 6/6
M3HA,M4HA 10/12 MP3A 337/6
M5A 229/12 MN4A 24/12
M6A 2420/6 MP4A 20/12
MRF 25/12 MN5A 6/6
CF 10.0

Maximum loads : 300 Ω and 1000pF to ground.

Ref.:IEEE JSSC , vol.SC-18 , pp.624-629 , Dec.1983

2. High-performance CMOS power amplifier (Siemens AG)

(1). New input stage : 3 gain stages.

+ VDD

BIAS M5 M10 M11

M13
+ M1 M2 -

M8 M9

CC
M7

M3 M4 M12
M6

- VSS

* Cc is connected to the source of M9 to improve PSRR

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* Three poles and one zero :
− 2 g m 6 g m8 g m13
Z= LHP.
C c g m6 g m13 + C 1 g m8 g m12

− g ds10 g o
P1 ≅
g m13C c
1/ 2
− g m8 (C c + C O ) g g  g m8 (C O + C C )  
2

P2 , P3 ≅ ± j m8 m13
−   
2C O C c  C O C1  2C C
O c  
where g o ≡ g ds12 + g ds13

C O = C L + C db12 + C db13

C1 = C gs13 + C db11 + C db 9 + C gd 9

Design guidelines for stability :

g m8 large , g m13 >> g m 6

(2). Output stage

+ VDD
VBIAS

Vout

Vin

- VSS

Class AB source follower

* One pole and one zero at high frequencies.

* Not full swing

 8 - 16
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+ V DD

-
A1 M1
+

Vin Vout

+
A M2
- 2

- VSS

Pseudo source follower

* The quiescent current in M1 and M2 will vary widely with variations in

Vos1 and Vos2.

* Suitable common-mode range of the two amplifiers A1 and A2 are

required.

* Large phase shift at high frequencies due to A1 and A2 ⇒ stability

problem.

Combined output stage:

* M1 and M2 are turned off in the quiescent state by building a small offset
voltage into A1 and A2 ⇒ M3-M6 control the output quiescent currents.
* M2 (M1) sinks (sources) approximately 95% of the required currents.

* M1 and M2 provide a high-frequency feed-forward path.

+ VDD

BIAS
-AMP 1
Vos M15
+
error amp.

M3 M5

M4 M6

+
Vos AMP 2 M17
-
VIN error amp.

- VSS

Still has a smaller swing limited by M5, M6 .

 8 - 18
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+ VDD

M4 M6

M15

Vout
M1 M2
M13

M7

M14 M15
CC

M8
M5

- VSS

* M13, M14 and M15 form a circuit to turn off M15 when Vout < VTP13
(negative)

* Cc : compensation.

* Three poles and one zeros.

g m7 + g mbs 7
Z1 ≈ −
Cc + Cgs 7

− gL
P1 ≈
g m15
C L + CC
g ds 6
1
 g 2
 g m 7 g ds6 (C L + Cc m15 )
 g (C + C L )  
2
g (C + CL ) g ds 6 where
P2 , P3 ≈ − m 7 c ± j −  m 7 c  
2Cc C L  C cC L C1  2C cC L  
 

C1 = C gs 9 + Cdb 6 + Cdb 7 + C gd 7
 8 - 19
+ V DD CHUNG-YU WU
M L7
ML3
BIAS4
C C3
M5
M L10 ML11
M10 M11
BIAS3 M L6
M12 M H4 MH5
M15
M1 M2
M14
M L9 M L1 ML2
CC1 MH8
M8 M9
M H9 MH1 M H2
ML8
M16
M 17
M7 BIAS2 MH6
MH10 MH11
C C2
M3 M4 M6 M 13 BIAS1 MH7 ML4 ML5
M H3
- VSS

TABLE I Component Sizes

M1 400/15 MH1 48/10 ML1 48/6

M2 400/15 MH2 50/10 ML2 50/6
M3 150/10 MH3 500/15 ML3 300/15
M4 150/10 MH4 300/6 ML4 150/5
M5 100/15 MH5 300/6 ML5 100/5
M6 150/10 MH6 200/5 ML6 300/6
M7 150/10 MH7 250/15 ML7 100/15
M8 300/5 MH8 700/6 ML8 400/5
M9 300/5 MH9 15/6 ML9 5/5
M10 300/10 MH10 10/15 ML10 5/15
M11 300/10 MH11 20/15 ML11 15/15
M12 1200/10 Cc1 20pf
M13 600/10 Cc2 4pf
M14 200/5 Cc3 4pf
M15 200/5
M16 600/6
M17 600/6
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TABLE II
POWER AMPLIFIER PERFORMANCE SUMMARY
(First Revision)

parameter Measured Results

Supplies ±5V
Open-Loop Gain 93dB
Bandwidth 1.2MHz
Power Dissipation x 12.7 mW
ó 1.76mW
Output Swing (RL=200Ù) ±3.1V
PSRR+ at DC 93dB
1 kHz 91dB
10 kHz 76dB
100 kHz 60dB
PSRR- at DC 102dB
1 kHz 89dB
10 kHz 75dB
100 kHz 53dB
Slew Rate 1.5V/ìs
Input Common Mode Range +3.3V
-5.5V
Die Area (5ìm CMOS) 1000 mils2
Harmonic Distortion (3 kHz)
Vin=3 Vp RL=200Ù
HD2 -73dB
HD3 -78dB

Maximum Loads : 1000pF and 200Ù to ground.

Ref.: IEEE JSSC , vol. sc-20, pp.1200-1205, Dec. 1985.

 8 - 21
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3. Efficient Unity-gain CMOS buffer for driving large CL.

High-drive OTA buffer Bias stage

VDD + V DD

MX5 MA1 M A4 MX1 MB1

A
MX7 M B2
VB1
V B1 M X2
MA2 MA3 Vout
Vin+ Vin- MR1
MR1
V B2 CL
B V B2
V B3 M A5 MX3 MX8 M B3
VB3

MX6 MX4 MB4

V SS - VSS

TABLE I
TRANSISTORS’ DIMENSIONS
TRANSISTOR W (µm) L (µm)
MX1, MX5 225 3
MX2 75 3
MX3 30 3
MX4, MX6 90 3
MR1 6 21
MA1, MA4 45 3
MA2, MA3 450 3
MA5 36 3
MX7 600 3
MX8 240 3

* MR1 has a low W/L and is operated in the linear region

⇒ like a linear resistor.

* MX2 and MX3

Quiescent operation:

² MX2 and MX3 are on.

⇒ Keep VGSMX7 and VGSMX8 low to reduce dc power.

 8 - 22
⇒ Provide a low-impedance level at node A and B. CHUNG-YU WU
The low-order poles created by the Miller cap. of MX7 and MX8 can be
avoid

* If Vin << 0

MX3-MX6 are turned off and MX1 and MX2 are on

⇒ Node A has a high voltage ⇒ MX7 off.

VB = VA because of MR1 ⇒ MX8 on.

* In the bias circuit, MR2 ↔ MR1, MB1 ↔ MX1, MB2 ↔ MX2, MB3 ↔ MX3, MB4 ↔
MX4.

In the quiescent case, VGSMX1 ≈ VGSMX7 and VGSMX4 ≈ VGSMX8

⇒ The current in MB1 and MB4 controls that in MX1 and MX4 and MX7 and MX8.
* RBIAS controls the current through MB2 and MB3.

⇒ i.e. the current through MX2 and MX3.

Characteristics:

3 µm CMOS area: 100mils2.

CL ≥ 100pF and RL ≥ 10 kΩ : stable.

CL=5000pF ⇒ f ≈ 100kHz.

TABLE II
BUFFER’S PERFORMANCE
PARAMETER MEASURED VALUE SPICE
Supply Voltage ± 2.5 V ± 2.5 V
Supply Current 285 µA 270 µA
Voffset < 10 mV 5 mV
Voltage Gain + 1.00 V/V + 1.00 V/V
F3dB (CL=100pF) 6 MHz 8 MHz
Gain Peaking 0.4 dB 0
RoCL 330 Ω 270 Ω
CMRR 80 dB 84 dB
Input CM Range ± 1.8 V ± 1.7 V
SR (CL=5nF) ± 0.9 V/µs ± 1.0 V/µs

Tsettling (to 1%) 3.9 µs 4 µs

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Input Noise Density
F = 1 kHz NA
270 V / H Z

F = 50 kHz NA
70 V / H Z

Ref.: IEEE JSSC, vol. sc-21, pp.464-469, June 1986.

§ 8-4 Advanced Design Techniques on Fully differential type CMOS OP AMPs

1. Low-noise chopper-stabilized OP AMP

Techniques for the reduction of 1/f noise:

1) Use large device geometries.

Possibly too large chip area.

2) Use buried channel devices

Not a standard technology.

3) Transform the noise to a higher frequency range

So that it does not contarninate the signal.

a. The correlated double sampling (CDS) method

b. The chopper stabilization method

a. CDS method

Vn 2
Vn2
VIN + VOUT
∑ a
-

S/H
f
V neq12
V neq12
VIN VOUT
a

⇒ Noise reduction

b. Chopper stabilization method

 8 - 24
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SIN Vn2
+1

f f -1

Vn2
+ +
VIN a1 a2 VOUT
- -

Signal

f f

Noise

f f

Vneq 2
+ +
VIN a1 a2 VOUT
- -

Vneq 2

* If the chopper frequency is much higher than the signal bandwidth, the 1/f
noise in the signal band will be greatly reduced.

Example: Fully differential class AB chopper stabilized OP AMP with DCMFB circuit.

Major advantage of fully differential OP AMPs:

1. Improvement of PSRR

2. Improvement of dynamic range

3. double the output swing

4. Reduction on the sensitivity to clock and supply noise.

Disadvantage:
 1. Larger area, mainly due to interconnection

2. Additional design complexity

3. Increase power dissipation.

+ V DD

Vcm+
M29 M13 M9 M10 M14 M30

M17 M25 M21 M22 M26 M18

V+ M43 M5 M6 M44
M1 M2

M45 M46
V-

Vo+ M7 M8 Vo-
M3 M4

M33 M47 M48 M34 M40

M39
M49 M50
M35 M36
M51 M52

V df M53
M54
M55 M56 C2 C4
C3 C1 M19 M27 M28 M20

M23 M24
Vcm-
M31 M15 M11 M12 M16 M32
M41 M37 M38 M42

- VSS

M43-M46, M47-M54: the input chopper and the output chopper.

M29-M42, C1-C4 : DCMFB circuit

Device W(um) L(um) Device W(um) L(um)

M1 25 3 M19 7 3.5
M2 25 3 M20 7 3.5
M3 25 3 M21 17.5 3.5
M4 25 3 M22 17.5 3.5
M5 25 3 M23 7 3.5
M6 25 3 M24 7 3.5

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M7 25 3 M25 3.5 3.5

M8 25 3 M26 3.5 3.5
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M9 10 3.5 M27 3 7
M10 10 3.5 M28 3 7
M11 4 3.5 M29 12 3.5
M12 4 3.5 M30 12 3.5
M13 17.5 3.5 M31 16 3.5
M14 17.5 3.5 M32 18 3.5
M15 7 3.5 M33-M34 7 3
M16 7 3.5 M55 7 3
M17 17.5 3.5 M56 7 3
M18 17.5 3.5
Ref: IEEE JSSC vol.sc-21, pp.57-64 Feb.1986

2. Fully differential folded cascode amplifier(National Semiconductor)

For internal OP AMPs, high output impedance is O.K.

⇒ simple 2-stage or single-stage OP AMP.

+VDD +VDD

IO
IO IO
CC V VBIAS CL
+ O M2
CL CGS
Vin M2 -
M1 Vin
M1 CP

-VSS -VSS

TWO-STAGE SINGLE-STAGE

CASCODE

DOMINANT AND NONDOMINANT POLE LOCATIONS

FOR THE TWO-AND SINGLE-STAGE AMPLIFIERS
Dominant Nondominant
pole location pole location
Two-stage 1 gm
amplifier ro C c g m ro CL
One-stage 1 gm
amplifier ro C L g m ro Cp

In general, the higher the 2nd pole frequency, the faster the settling response.

⇒ Single-stage cascode amp. has a faster settling behavior.

 +VDD

VBIAS
+
Vin -V
CL out +
-
CL CMFB

-V SS

CMFB: Common-mode feedback circuitry

3. High-performance micropower fully differential OP AMP.

Simplified schematic of the class AB amplifier:

A +VDD
M12 M11
M17 M14

BIAS3 BIAS1
M20 M16
M5 M1 M2 M6
Iin(+) I in(-)
OUT(+) OUT(-)
M7 M8

I1 I2
M3 M4
BIAS4 BIAS2
M19 I I M15

M18 M10 M9 M13

A -VSS
 8 - 27
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+V DD

M17 M12

BIAS3 I2
M20 M5
Iin(+) M1 M6 Iin (-)

OUT(+) OUT(-)
I M8
4µA class AB M7 M4
3µA
I2 BIAS2
2µA M15
class A
1µA I I
-400 -200 200mV 400mV
V in M9 M13
− 1µA
− 2µA

-VSS

Active portion of the amplifier for a positive input signal.

Detailed schematic of the entire amplifier without CMFB:

+V DD
M11
M23 M14
M12
M17

M20 M22 M27

M26 M16
M5 M1 M2 M6

Iin(+) Iin(-)
OUT(+) OUT(-)
M7 M8
I2 I1

M3 M4
M19 M24
M30 M15
M 60A
M18 M25
M10
M21 M13
M9
-VSS
 8 - 28
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* NMOS dynamically biased current mirror:

OUT
I30

M30 M 15
10 40
10 10

I9

M9 M 13
40 40
10 10

- VSS

If I 9 = I 30 , VGS 9 = VGS13 = VGS15

V DS13 = VGS 30 − V GS9

Set VDG13 = −VTH ⇒ VGS 30 = 2VGS 9 − VTH

W
Design ( )30 , such that VGS 30 = 2VGS 9 − VTH
L

⇒ M 13 is always sat. at the edge of the linear region.

⇒ Output swing↑
* Dynamic CMFB is used.

AMPLIFIER DEVICE SIZES

DEVICE Z(μm) L(μm)
M1 180 6
M2 180 6
M3 140 6
M4 140 6
M5 150 6
M6 150 6
M7 200 6
M8 200 6
M9 22 10
M10 22 10
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M11 29 7
M12 29 7
M13 22 10
M14 29 7
M15 22 6
M16 29 6
M17 29 7
M18 22 10
M19 22 6
M20 29 6
M21 20 9
M22 6 12
M23 28 6
M24 6 14
M25 20 9
M26 6 12
M27 28 6
M30 6 14

AMPLIFIER SPECIFICATIONS

CORE AMPLIFIER SPECIFICATIONS

(0-5 Volts Supply)
100μW Quiescent Power Dissipation

DIFFERENTIAL GAIN >10.000«

UNITY GAIN FREQUENCY 2 MHz«

NOISE 140 nV/ Hz 1KHz

50 nV/ Hz white
OUTPUT SWING 0.5 Volts from Supply«

AREA 300 mils 2

«inferred from filter measurement

Ref: IEEE JSSC, vol. SC-20, pp.1122-1132, Dec. 1985
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4. Fully differential class AB OP AMP with CMFB circuit

+ VDD

M18 M16 M15 M17

100µA 100µA
BIAS BIAS
M20 M19

MC1 MC2 Vin - M2 M1 Vin+ MC12 MC11

Vout+ M8 M7 Vout-
MC4 MC5 M6 M5 MC15 MC14
M3 M4
BIAS BIAS
M14 M13
BIAS 5µ A 5µ A BIAS

MC6 MC7 MC17 MC16

M10 M9
M11
M12
- VSS

Characteristics:

Technology : 5um, P-well CMOS, double-poly cap.

Open loop gian : 1180 unity-gain freq : 10Mhez

CMRR : 61db power consumption : 2.3mw

Area : 290 mils2 power supply : ± 5V

Ref: IEEE JSSC ,vol.sc-20 , pp.1103-1112 , Ddec,1985
 8 - 31
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§ 8-5 Recent Design Examples of CMOS OP AMPs
§ 8-5.1 Fast-settling CMOS OP AMP for SC Circuit with 90-dB DC Gain
Reference : IEEE JSSC, vol.25, no.6, pp.1379-1384, Dec 1990.

1.Gain boosting
1) Cascode gain stage with gain enhancement
+VDD

Vo
Vref + Cload
Aadd M2
_

M1
Vi

-VSS

Rout = [g m 2 ro2 ( Aadd + 1) + 1]ro1 + ro 2

Atot = g m1ro1 [g m 2 ro 2 ( Aadd + 1) + 1]
Aorig = g m1 g m2 ro1ro 2
2) Repetitive implementation of gain enhancement

+VDD

Vo

M2 M4 M6 M8

M1 M3 M5 M7
Vi

-VSS

2.High-frequency behavior
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CHUNG-YU WU
gain (log)
Atot ω3 : Upper 3-dB frequency of Aorig

gain enhancement ω5 : Unity-gain frequency of Atot

Aadd = Aadd(0) +1 ω2 : Upper 3-dB frequency of Aadd
ω4 : Unity-gain frequency of Aadd
Aorig
ω1 : Upper 3-dB frequency of Atot
ω (log)
ω6 ω5 : Unity-gain frequency of Aorig
ω1 ω2 ω3 ω4 ω5

We want ω5 Aorig = ω5 Atot

ω 2 > ω 1 => The bandwidth is determined by ω 1, i.e. Rout and Cload.

=> ω 4 > ω 3
But ω 4 < ω 5 for easy design of Aadd.
Aadd and M2 forms a close loop with the dominant pole of ω 2 and the second pole at the
source of M2, i.e. ω 6
The stability consideration requires ω 4 < ω 6
=>The safe range of ω 4 is
ω3 < ω4 < ω6
* The repetitive usage of the gain-enhancement techniques yields a decoupling of the
op-amp gain and unity-gain frequency fu. That is:gain↑ without fu↓ .
3.Settling behavior
1. Total output impedance Ztot
Ztot= Z load // Z out Zload: impedance of Cload
Zout: output impedance of the amplifier
Zout ≅ Zorig (Add+1)
Z load Normalized impedance
g −m1 (log)
Z tot
g −m1 Z out
g −m1

Z orig
g −m1
Pole-zero
ω (log)
doublet
ω1 ω2 ω3 ω4 ω5
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CHUNG-YU WU
ω2 : Upper-3dB freq. Of Aadd
èthe same for Z out

ω4 : Unity-gain freq. Of Aadd

For ω > ω4 , Aadd < 1è Z out → Z orig

èA zero is formed at ω4 for Z out

Z total = Z load || Z out èA pole-zero doublet is formed around ω4

èThe same doublet of Atotal
3. Design technique for fast settling
1
The time constant of the doublet, , must be smaller than the main close-loop time
ω PZ
1
constant, . where β is the feedback factor.
βω unity

The safe range for the ω4 .

gain (log)

Aaddd

Aclosed-loop
1/β ω2 ω4 ω5 ω6
βω 5
ω (log)

Safe range for ω 4

βω5 < ω4 < ω6

doublet

4. CMOS OP AMP circuit

 8 - 34
CHUNG-YU WU
+VDD

Vbp1 Vbp1

Vcm
Vin- Vin+

Ib
Vout+ Vout-

Vbn1 Vbn1

-VSS
MAIN CHARACTERISTICS OF THE OP AMP
Gain enh. on Off
DC-gain 90dB 46dB
Unity-gain freq. 116MHz 120MHz
Load cap. 16pF 16pF
Phase margin 64deg. 63deg
Power cons. 52mW 45mW
Output-swing 4.2V 4.2V
Supply voltage 5.0V 5.0V
Settling time 61.5ns -
0.1% , ∆V o = 1V

§ 8-5.2 1V Rail-to-Rail CMOS OP AMPs

Ref.: IEEE JSSC vol.35, no.1, pp.33-44 Jan. 2000
 8 - 35
CHUNG-YU WU
1. Typical input stage for rail-to-rail amplifiers
* Parallel-connected complementary * Operating zones for low VDD/VSS
differential pairs.

* Operating zones for extremely low

VDD/VSS

Dead region.
Both pairs are off.

Vi,n,cm=Vi,cm+IR
2. Dynamic level-shifting current generator Vi,p,cm=Vi,cmi-IR

* The input resistance over the entire voltage range is infinite and no loading effect or
input current over the previous stage.

Usually mismatches cause negligible input current.

* The symmetrical topology ensures very high CMRR
1 ∆ R ∆Gm −1
CMRR = ( + )
RG m R Gm

where Gm = ∆I / ∆ Vi ,cm
 8 - 36
CHUNG-YU WU

Circuit implementation

3. Rail-to-rail very LV CMOS OP AMP with input dynamic level-shifting circuit

MAIN TRANSISTOR ASPECT RATIOS (IN µm) AND ELEMENT VALUES OF THE
AMPLIFIER BASED ON COMPLEMENTARY PAIRS
M1A,M1B 400/5 M15 700/2
M2A,M2B 200/5 R1-R4 30 KΩ
M1,M2 400/2 RM 5 KΩ
M3,M4 200/2 CM 10pF
M5-M8 400/5 I bn = I bp 10µA
M9-M12 500/5 Io 40µA
 8 - 37
4. Input CM adapter CHUNG-YU WU

+
Vx = A[2Vref - (Vi,p + Vi,p )]
-

= 2A(Vref − Vi,p,cm )

I = G m Vx
Vi,cm
=> Vi,p,cm ≅ Vref +
2RGmA

Vi,p,dm = Vi,dm

*Vi ,cm is degraded by A and Vi , p ,cm ≅ V ref

Circuit implementation:

5. Very LV CMOS OP AMP with a single differential pair and the input CM adapter.
 8 - 38
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Main transistor ratios(in µm) and element values of the amplifier based on a single input pair
M1A M1B 1000/6 M6 1600/2
M2A M2B 600/4 M7-M10 300/4
MA1-MA4 50/2 M11 700/2
MA5-MA6 300/4 R1-R2 15KΩ
M2D 150/2 RM 5KΩ
M1,M2 200/2 CM 5pF
M3-M5 400/2 Is=Ir/2 10µA
6.Measured results
Experimental performance of amplifiers(Vsupply=1V,technology:1.2µm CMOS, CL=15pF)
Parameter Dynamic-shifting amp CM adapater amp
Active die area 0.81mm 2 0.26 mm 2
Ido(supply current) 410uA 208uA
DC gain 87dB 70.5dB
unity-gain frequency 1.9Mhz 2.1Mhz
Phase margin 61° 73°
SR+ 0.8V/us 0.9V/us
SR- 1V/us 1.7V/us
THD(0.5Vpp@1kHz) -54dB -77dB
THD(0.5Vpp@40kHz -32dB -57dB
Vni(@1KHz) 267nV/ Hz 359nV/ Hz
Vni(@10KHz) 91nV/ Hz 171nV/ Hz
Vni(@1MHz) 74nV/ Hz 82nV/ Hz
CMRR 62dB 58dB
PSRR+ -54.4dB -56.7dB
PSRR- -52.1dB -51.5dB
§8-5.3 1.5V High Drive Capability CMOS OP AMP
Ref.: IEEE JSSC vol.34, no.2, pp. 248-252, Feb. 1999
 8 - 39
+VDD CHUNG-YU WU
1. Folded-mirror differential input stage
VBIAS2 M3 M4
VCM ≤ VGS 6, 7 + VTHn = 2VTHn + ∆V6, 7 OUT

VCM ≥ VDSsat 5 + VGS 1, 2 = 2VTHn + ∆V5 + ∆V1, 2

IN+ M1 M2
CMR = VTHn − ∆V5 IN-
∆V : overdrive voltage. VBIAS1
M5 M6 M7
CMR is independent of supply voltage.
For VDD=1.5V , CMR=0.6 ~ 0.7V -VSS
CMR of the conventional NMOS-input differential pair is 0.3-0.5V
2. Output Stage

+VDD

M6A M8A M4A IB2

IB1
OUT
A
B

IN
M1A M3A M5A M7A M2A

-VSS

Input section : M1A-M4A , IB1 , IB2

Output section: M5A-M6A and M7A-M8A
M5A, M8A sat
M6A, M7A off.
For low input levels , M6A and M7A off è Class A operation.
For large positive input signals,
ID1A=IB1 è M3A and M5A OFF
è VA → -VSS
è M6A is turned on to supply most of the output current.
But M7A remains cutoff.
The current of M8A is increased.
For large negative input signals, M7A supplies most of the output current.
(W/L) 5A,8A << (W/L) 6A,7A for low dc power dissipation and high drive.
 8 - 40
3. Overall LV CMOS OP AMP. CHUNG-YU WU

+VDD

M15 M3 M6 M7 M18 M6A M8A M4A M11 M12

IBIAS
M8
OUT
CC3A CC3B
M1 M2
IN- IN+ MC CC2 CC1

M14 M4 M5 M9
M16 M1A M5A M7A M2A M13
M3A

-VSS

1
Dominant pole : Wp1≈
ro5,7{(gm8 ro8,9 )2[gm5A,8A(ro5A || ro8A )]}Cc

g m1, 2
Gain-bandwidth product: WGBW ≈
C c1

Hybrid nested Miller compensation: CC1, CC2, CC3A,B

The inner amplifier M8,M9,M1A~M8A contributes the nondominant poles.
g m1, 2
* The two-stage OP AMP M1~M9 has a gain-bandwidth product of
Cc 2
g m1,2
and the gain of at high frequency. The gain of M1-M7 at high frequency is
sCc 2

g m1,2 CC1
. Thus the gain of the gain stage M8 and M9 is approximately equal to .
sCc 1 CC 2

* The open-loop gain of the inner amplifier is

 C  g 
Ain ≅ − C 1  m1 A, 2 A 2 g m 5 A, 8 A (ro 5 A ro8 A )
 CC 2  g m3 A , 4 A 

g m3 A ,4 A
Dominant pole : ωP1in ≅
g m5 A,8 A (ro 5 A || ro8 A )C C 3 A, B

2 g m5 A, 8 A
Second pole : ωP 2in ≅
CL
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CHUNG-YU WU
C g
Gain-bandwidth product : ωGBWin ≅ 2 C1 m1A , 2 A
C C 2 C C 3 A, B
or the second pole of the
whole amplifier
Design consideration :
To obtain a maximally flat Butterworth response without gain peaking, we have the
unity-gain frequency equal to one half of the second-pole frequency.
1
ωGBWin = ωuin = ωP 2 in
2
1 1
ωGBW = ωu = ωuin = ωGBWin
2 2
Reference : IEEE JSSC, vol.27, pp.1709-1716, Dec. 1992.

Setting 2C C 3 A, B = C C 2 , we have

g m1, 2
C C1 = 2 CL
g m5 A,8 A

CL
C C 2 = 2C C 3 A, B = 2 g m1, 2 g m1 A, 2 A ⋅
g m5 A,8 A
Component values :
M1,M2,M3,M9,M1A,M2A,M10 60/2
M4,M5,M11,M12,M13 20/2
M6,M7 15/2
M8 90/2
M3A 5/1.2
M4A 15/1.2
M5A 30/1.2
M7A 120/1.2
M6A 360/1.2
M8A 90/1.2
M14,M16 10/1.2
M15,MC 30/2
CC1 4pF
CC2 6pF
CC3A,CC3B 2pF
IBIAS 5uA
VTH 0.8V
 8 - 42
CHUNG-YU WU

Experimental results:

MEASURED MAIN PERFORMANCE

Open-Loop Gain 68dB
GBW 1MHz
Phase Margin 65o
Gain Margin 16dB
Settling Time(0.1%), ∆V = 200mV 400ns
Slew Rate 1 V/μs
THD@1kHz Vout = 0.5V RL=500Ω -57dB
Closed-Loop Gain=20dB
PSRR+@1kHz 75dB
PSRR- @1kHz 75dB
CMRR @1kHz 95dB
Offset < 8mv
Power Dissipation 280μW
Die Size 0.08 mm 2
Technology 1.2μm CMOS
Loading 50pF || 500Ω