74VHC32 Quad 2-Input OR Gate

November 1992
Revised February 2005

74VHC32
Quad 2-Input OR Gate
General Description Features
The VHC32 is an advanced high speed CMOS 2-Input OR ■ High Speed:
Gate fabricated with silicon gate CMOS technology. It tPD 3.8 ns (typ) at VCC 5V
achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low ■ Low Power Dissipation:
power dissipation. ICC 2 PA (Max) at TA 25qC
The internal circuit is composed of 4 stages including buffer ■ High Noise Immunity: VNIH VNIL 28% VCC (Min)
output, which provide high noise immunity and stable out- ■ Power down protection is provided on all inputs
put. An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt- ■ Low Noise: VOLP 0.8V (Max)
age. This device can be used to interface 5V to 3V systems ■ Pin and Function Compatible with 74HC32
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.

Ordering Code:
Package
Order Number Package Description
Number
74VHC32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC32MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
(Note 1)
74VHC32SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC32MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC32MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
(Note 1) Wide
74VHC32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol Connection Diagram

IEEE/IEC

Truth Table
A B O
Pin Descriptions H H H
Pin Names Description L H H
An, Bn Inputs H L H
On Outputs L L L

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74VHC32
Absolute Maximum Ratings(Note 2) Recommended Operating
Supply Voltage (VCC) 0.5V to 7.0V Conditions (Note 3)
DC Input Voltage (VIN) 0.5V to 7.0V Supply Voltage (VCC) 2.0V to 5.5V
DC Output Voltage (VOUT) 0.5V to VCC  0.5V Input Voltage (VIN) 0V to 5.5V
Input Diode Current (IIK) 20 mA Output Voltage (VOUT) 0V to VCC
Output Diode Current (IOK) r20 mA Operating Temperature (TOPR) 40qC to 85qC
DC Output Current (IOUT ) r25 mA Input Rise and Fall Time (tr, tf)
DC VCC/GND Current (ICC) r50 mA VCC 3.3V r0.3V 0 a 100 ns/V
Storage Temperature (TSTG) 65qC to 150qC VCC 5.0V r0.5V 0 a 20 ns/V
Lead Temperature (TL) Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
(Soldering, 10 seconds) 260qC tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Min Typ Max Min Max
VIH HIGH Level 2.0 1.50 1.50
V
Input Voltage 3.0  5.5 0.7 VCC 0.7 VCC
VIL LOW Level 2.0 0.50 0.50
V
Input Voltage 3.0  5.5 0.3 VCC 0.3 VCC
VOH HIGH Level 2.0 1.9 2.0 1.9 VIN VIH IOH 50 PA
Output Voltage 3.0 2.9 3.0 2.9 V or VIL
4.5 4.4 4.5 4.4
3.0 2.58 2.48 IOH 4 mA
V
4.5 3.94 3.80 IOH 8 mA
VOL LOW Level 2.0 0.0 0.1 0.1 VIN VIH IOL 50 PA
Output Voltage 3.0 0.0 0.1 0.1 V or VIL
4.5 0.0 0.1 0.1
3.0 0.36 0.44 IOL 4 mA
V
4.5 0.36 0.44 IOL 8 mA
IIN Input Leakage 0  5.5 r0.1 r1.0 PA VIN 5.5V or GND
Current
ICC Quiescent Supply Current 5.5 2.0 20.0 PA VIN VCC or GND

Noise Characteristics
VCC TA 25qC
Symbol Parameter Units Conditions
(V) Typ Limit
VOLP Quiet Output Maximum 5.0 0.3 0.8 V CL 50 pF
(Note 4) Dynamic VOL
VOLV Quiet Output Minimum 5.0 0.3 0.8 V CL 50 pF
(Note 4) Dynamic VOL
VIHD Minimum HIGH Level 5.0 3.5 V CL 50 pF
(Note 4) Dynamic Input Voltage
VILD Maximum LOW Level 5.0 1.5 V CL 50 pF
(Note 4) Dynamic Input Voltage
Note 4: Parameter guaranteed by design.

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 74VHC32
AC Electrical Characteristics
VCC TA 25qC TA 40qC to 85qC
Symbol Parameter Units Conditions
(V) Min Typ Max Min Max
tPHL Propagation Delay 3.3 5.5 7.9 1.0 9.5 CL 15 pF
ns
tPLH r0.3 8.0 11.4 1.0 13.0 CL 50 pF
5.0 3.8 5.5 1.0 6.5 CL 15 pF
ns
r0.5 5.3 7.5 1.0 8.5 CL 50 pF
CIN Input Capacitance 4 10 10 pF VCC Open
CPD Power Dissipation 14 pF (Note 5)
Capacitance
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN  I CC/4 (per gate).

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74VHC32
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A

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 74VHC32
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

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74VHC32
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14

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 74VHC32 Quad 2-Input OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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