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VLSI Project Report - Arithmetic Logical Unit using Verilog

(ALU)
Vlsi Design (SRM Institute of Science and Technology)

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ARITHMETIC LOGIC UNIT

AIM: To create an ARITHMETIC LOGIC UNIT Using XILINX
SOFTWARE

SOFTWARE REQUIRED: Xilinx, Modelsim

INTRODUCTION:
Arithmetic Logic Unit is the part of a computer that performs arithmetic operations on
binary numbers. On the contrary, FPU (Floating Point Unit) works on decimal values.
This ALU is comprised of CPU (Central Processing Unit), Floating Point Unit (FPU),
GPU (Graphical Processing Unit. Thus, a single CPU or FPU might contain many
ALU’s. The inputs to an ALU are the data where we have to perform operations.
They are called operands. They perform the necessary operation and the result is the
output of the operation we have performed. Thus, the ALU consists of input or output
or even both. They also contain results of previously performed operations or the
current operation and also registers. Registers are used to store, fetch and process data
and that is being used by the Central Processing Unit. Processor Registers are the
registers that are being used by the CPU for processing. Modern computers contain
very complex Arithmetic Logic Units. In addition to that, they might contain the
Control Unit (CU) as well. Data is moved in between ALU, memory, and registers
and this operation is performed by the Central Processing Unit (CPU).

METHODOLGY OF ARITHMETIC LOGIC UNIT:

ALU performs Arithmetic and Logical Operations.

Arithmetic Operations include Addition, Subtraction, Multiplication, and

Division. Logical Operations include operations using AND, OR, and NOT. It does
comparison of operations. The computer manipulates and stores numbers in terms of
0’s and 1’s. Transistor switches are used to do these operations as they accept values
only in terms of 0’s and 1’s. Open and Closed Switch concept is used. Open switch is
a device in which no current passes through and it represents the value ‘0’. Closed
switch is a device in which current passes through and it represents the value ‘1’.

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Multiple transistors can be connected and the resulted output can be obtained. The
first transistor can be connected to the second one and in turn, control the operation of
the second transistor. The second transistor can be switched ON or OFF depending on
the state if the first processor. This is called ‘GATE’ (logical gates) Gate is the one
that allows the flow of current. Now let us see in detail about Gates. There are 3
gates. AND, OR, and NOT gate.

OR gate:
In this, we give two inputs and get one output. If Input A is 0 and input B is 0, then
output C is 0. If input A is 0 and input B is 1, then output C is 1. If input A is 1 and
input B is 0, then output C is 1. If input A is 1 and input B is 1 then output C is also 1.

AND gate:
This AND gate again have two inputs and gives one output. If Input A is 0 and B is 1,
then output is 0. If input A is 0 and input B is 1, then output C is 0. If input A is 1 and
input B is 0, then output C is 0. If input A is 1 and input B is 1 then output C is also 1.

NOT gate:
NOT gate generally consists of 1 input and 1 output. If input A is 0 then output B is 1.
If input A is 1 then output B is 0.

XOR gate:
The X or is the reverses version of the OR gate. In XOR gate if Input A is 0 and B is 0
then output C is 0. if input A is 0 and B is 1 then output C is 1. If input A is 1 and
input B is 0 then output C is 1. If input A is 1 and B is 1 then output C is 1.

NOR gate:
In the NOR gate if input A is 0 and B is 0 then output C is 1. if input A is 0 and B is 1
then output C is 0. If input A is 1 and input B is 0 then output C is 0. If input A is 1
and B is 1 then output C is 0.

NAND gate:
In the NAND gate, if input A is 0 and B is 0 then output C is 1. If input A is 0 and B is
1 then output C is 1. If input A is 1 and input B is 0 then output C is 1. If input A is 1
and B is 1 then output C is 0.

BIT SHIFTING OPERATIONS:

A bit shifting operation is done to shift the most significant bit either to the right or
left. There are three types of bit-shifting operations:

LEFT ARITHMETIC SHIFT:

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In a left Arithmetic shift, the most significant bit is shifted towards the right. The
zeros are shifted on the right.

RIGHT ARITHMETIC SHIFT:

In a right Arithmetic shift, the most significant bit is shifted towards the left. The
zeros are shifted in the left.

RIGHT LOGICAL SHIFT:

In the Right Local Shift, the zeros are shifted to the left and the point to be noted is the
least significant bit is lost.

CODE:

Testbench:

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RESULTS:

APPLICATIONS:
Multiple-precision arithmetic
In integer arithmetic computations, multiple-precision arithmetic is an algorithm
that operates on integers which are larger than the ALU word size. To do this, the
algorithm treats each operand as an ordered collection of ALU-size fragments,
arranged from most-significant (MS) to least-significant (LS) or vice versa. For
example, in the case of an 8-bit ALU, the 24-bit integer 0x123456 would be treated as
a collection of three 8-bit fragments: 0x12 (MS), 0x34, and 0x56 (LS). Since the size
of a fragment exactly matches the ALU word size, the ALU can directly operate on
this "piece" of operand.

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The algorithm uses the ALU to directly operate on particular operand fragments and
thus generate a corresponding fragment (a "partial") of the multi-precision result. Each
partial, when generated, is written to an associated region of storage that has been
designated for the multiple-precision result. This process is repeated for all operand
fragments so as to generate a complete collection of partials, which is the result of the
multiple-precision operation.
In arithmetic operations (e.g., addition, subtraction), the algorithm starts by invoking
an ALU operation on the operands' LS fragments, thereby producing both a LS partial
and a carry out bit. The algorithm writes the partial to designated storage, whereas the
processor's state machine typically stores the carry out bit to an ALU status register.
The algorithm then advances to the next fragment of each operand's collection and
invokes an ALU operation on these fragments along with the stored carry bit from the
previous ALU operation, thus producing another (more significant) partial and a carry
out bit. As before, the carry bit is stored to the status register and the partial is written
to designated storage. This process repeats until all operand fragments have been
processed, resulting in a complete collection of partials in storage, which comprise the
multi-precision arithmetic result.
In multiple-precision shift operations, the order of operand fragment processing
depends on the shift direction. In left-shift operations, fragments are processed LS first
because the LS bit of each partial—which is conveyed via the stored carry bit—must
be obtained from the MS bit of the previously left-shifted, less-significant operand.
Conversely, operands are processed MS first in right-shift operations because the MS
bit of each partial must be obtained from the LS bit of the previously right-shifted,
more-significant operand.
In bitwise logical operations (e.g., logical AND, logical OR), the operand fragments
may be processed in any arbitrary order because each partial depends only on the
corresponding operand fragments (the stored carry bit from the previous ALU
operation is ignored).
Complex operations
Although an ALU can be designed to perform complex functions, the resulting higher
circuit complexity, cost, power consumption and larger size makes this impractical in
many cases. Consequently, ALUs are often limited to simple functions that can be
executed at very high speeds (i.e., very short propagation delays), and the external
processor circuitry is responsible for performing complex functions by orchestrating a
sequence of simpler ALU operations.
For example, computing the square root of a number might be implemented in various
ways, depending on ALU complexity:

● Calculation in a single clock: a very complex ALU that calculates a square

root in one operation.
● Calculation pipeline: a group of simple ALUs that calculates a square root
in stages, with intermediate results passing through ALUs arranged like a
factory production line. This circuit can accept new operands before

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finishing the previous ones and produces results as fast as the very complex
ALU, though the results are delayed by the sum of the propagation delays
of the ALU stages. For more information, see the article on instruction
pipelining.
● Iterative calculation: a simple ALU that calculates the square root through
several steps under the direction of a control unit.
The implementations above transition from fastest and most expensive to slowest and
least costly. The square root is calculated in all cases, but processors with simple
ALUs will take longer to perform the calculation because multiple ALU operations
must be performed.

CONCLUSION:
We have seen the ARITHMETIC Logic Unit in detail. We have seen how to use it for
arithmetic and logical operations. We have also seen various gates and how to use
them. I hope this would be helpful to learn the concepts of the Arithmetic Logic Unit.
Feel free to comment and leave your suggestions, s that we could discuss more.

REFERENCES:
1. https://en.wikipedia.org/wiki/Arithmetic_logic_unit
2. https://study.com/academy/lesson/arithmetic-logic-unit-alu-definition-
design-function.html
3. https://www.computerhope.com/jargon/a/alu.htm
4. https://www.dictionary.com/browse/alu
5. https://computersciencewiki.org/index.php/Functions_of_the_arithmetic
_logic_unit_(ALU)
6. https://www.webopedia.com/TERM/A/ALU.html

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