Clock Tree Synthesis

CTS :
● The concept of clock tree synthesis (CTS) is the automatic insertion
of buffers/inverters along the clock paths of the ASIC design to
balance the clock delay to all clock inputs.

● After all the standard cells are placed ,the clock nets are buffered.
Clock balancing is important for meeting the design constraints and
CTS is done after placement to achieve the performance goals.

● CTS is performed in order to balance the skew and minimize

insertion delay.
Skew and insertion delay :
Clock Skew: The Difference in the clock arrival time for two flops at two
spatially distinct points.

DATA 1 COMB DATA 2

Q1
Q2
T1 FF1 FF2

T2
Clock

Common path delay

Here, T1 = time required for reach the clock signal at FF1

T2 = time required for reach the clock signal at FF2

Skew ( T) = T1 ~ T2 ; (unit : nano second)

Clock Skew :
The arrival time at different flops at different times are due to-

● Wire length
● Capacitance and resistance of metal
● differences in input capacitance on the clock inputs
● Temperature
● Source clock noise

clock skew can be two types.

1. Positive skew
2. Negative skew
Positive skew = When the transmitting flop receives the clock edge earlier than the receiving flop.
Negative skew = When the receiving flop gets the clock edge earlier than the transmitting flop.

Zero clock skew refers to the arrival of the clock edge simultaneously at transmitting and
receiving flop.
Clock Insertion Delay :
● Clock Insertion Delay or also known as clock latency is defined as the
travelling time for a clock signal to travel its source to the sinks.

Clock latency= Source latency + Network latency

Source latency: Defined as the time taken by the clock signal in traversing from
clock source (Example: PLL, oscillator or some other source) to the clock
definition point.

Network latency: Defined as the time taken by the clock signal in traversing
from clock definition point to the sinks of the clock ( to a flop actually).

The clock tree will balance if sum of source latency and network latency for all
sinks of a clock is equal.
Clock insertion delay :
In the following diagram we can see the both types of delay in clock path.

DATA 1 DATA 2
COMB
Q1
Q2
FF1 FF2

Clock
Source
(Ex : PLL)

Source insertion delay Network insertion delay

Clock definition Point as a port

of the block
Clock Tree :

Clock source

Clock
Tree
Cells

Clock
Buffers
For
balancing

Registers

Clock tree is not balanced here Clock tree is balanced here

CTS Goals:
● Clock Tree is defined such that clock skew is minimized.

● Ideal clocks are converted to propagated clocks (i.e. clocks with

delay).

● Timing constraints are added/relaxed to achieve desired effect.

● Clock Tree Optimization (CTO) is performed to improve slack.

● Clock buffers are added in this stage.

Checklists :
Before CTS
● Placement - Completed
● Power/Ground nets - Pre Routed
● Estimated Congestion - Acceptable
● Estimated Timing - Acceptable (~ 0 ns slack)
● Estimated Max Tran/Cap - No Violations
● High Fanout Nets - Zero
Checklists :

Inputs required for CTS:

● Optimized netlist
● Constraint in SDC format
● Clock Tree Specification file (*.ctstch or *.ckSpec)
● Logical Timing Library in .lib format
● Physical Libraries in LEF format
● Clock Constraints and commands in TCL
Checklists :
Output of CTS:

➔ Post CTS Design with Clock tree inserted in the netlist and Design
Exchange Format(DEF).
Checklist after CTS:
➔ Setup time report
➔ Hold time report
➔ Skew report
➔ Latency report
➔ DRV (Design Rule Verification) report
➔ Max Transition
➔ Max Capacitance
➔ Max Fanout
➔ Minimum pulse width
Clock tree spec file:
After we do the placement of the cells where flops are also placed, then we
have to build a clock tree for the flops.

When we build the clock tree for the flops ,we need to tell the tools that how
the clock tree has to be build. This is a specification file. It contains

● What is the clock

● What are the different clocks we have to built

A design can contains multiple clocks. One domain is running very high speed
and one domain is running very low speed depending on different applications.

In the same chip there can be multiple clock domains.

Clock tree spec file:
So we have to tell the tool,

1. What is the name of the clock.

2. What is the transition.
3. What is the frequency of the clock.
4. What is the expected latency of the clock.
5. Is there any Non Default Rules to route the clock tree for robustness.
6. Fanout (How many clocks can your flop drive).
7. Which buffers & inverters will be used for balancing and building clock
tree.

We can modify clock tree spec file to add more constraints manually.
Clock tree spec file Example:
Here we can see a clock tree specification file which is made of 2 clock. The cells are used is clock
Buffer.

The normal inverters and buffers are not used for building and balancing because, the clock buffers
provides a better slew and better drive capability when compared to normal buffers and clock
inverters provides a better balance with rise and fall times and hence maintaining the 50% duty cycle.
Clock Tree structure:
There can be several structure for clock tree

1. H-Tree
2. X-Tree
3. Binary-tree
4. Fish-bone tree
H -Tree :
Figure shows a balanced H-tree clock topology. Due to the structural symmetry, a balanced tree
exhibits identical nominal delay and identical buffer and interconnect segments from the root of the
distribution to all branches. If the matching is adhered to, structural skew can be zero. With identical
buffer and interconnect segments, an idealized balanced tree clock distribution will exhibit good
tracking across PVT compared to the unconstrained network.

MACRO

Balanced H-tree network

X-Tree :
The X-tree incorporates non rectilinear clock trunks in the physical
implementation but exhibits the same properties as the H-tree. The trunk
widths in a tapered H-tree increase geometrically toward the root of the
distribution to maintain impedance matching at the T-junctions.

Variations on the balanced tree topology

Binary Tree and Fish Bone Tree:

This two type Clock tree also build as considering process variations and
requirements.

fLOP

BINARY TREE FISH BONE TREE

Automatic clock tree synthesis :
Tools have capability of doing excellent clock tree. Tool just need clock tree
synthesis constraints and guidance.

Advantage:

● Easy to use, no manual routing or placing, flexible.

● All type of targets like max skew,transition & fanouts are honored.
● Low skew can be obtained if clock structure is not that complex.
● Good correlation between pre and post route clock skew.

Disadvantage:

● Sometimes optimization does not work due to complex constraints.

● Quality drops due to large clock structure and cts constraints is not
good enough.
CTS in large and complex designs :
In large and complex design power dissipation is one of the main design concern.
And Clock is the main source of power dissipation because of continuous
switching.

For power saving we do multiple task in CTS. We do

● Multi-level clock gating

● Multi-clock speed domains
END