Scribd
Upload
40 views1 page

CS G553 - Compre - Q

This document contains a comprehensive examination for a reconfigurable computing course. It includes 4 questions. Question 1 involves writing a truth table and drawing a ROBDD for a combinational logic problem, and implementing the logic using LUTs. Question 2 involves drawing data flow graphs for arithmetic operations using ASAP and ALAP scheduling, and applying list scheduling. Question 3 applies the Chortle-crf LUT mapping algorithm to a logic expression. Question 4 describes implementing a 4-bit adder in a Xilinx CLB.

Uploaded by

Pavan kalyan Gedela
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
40 views1 page

CS G553 - Compre - Q

This document contains a comprehensive examination for a reconfigurable computing course. It includes 4 questions. Question 1 involves writing a truth table and drawing a ROBDD for a combinational logic problem, and implementing the logic using LUTs. Question 2 involves drawing data flow graphs for arithmetic operations using ASAP and ALAP scheduling, and applying list scheduling. Question 3 applies the Chortle-crf LUT mapping algorithm to a logic expression. Question 4 describes implementing a 4-bit adder in a Xilinx CLB.

Uploaded by

Pavan kalyan Gedela
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Birla Institute of Technology and Science – Pilani

K.K. Birla Goa Campus


First Semester 2020-2021
CS G553-Reconfigurable Computing
Component: Regular (Open Book)
Duration: 120 min Comprehensive Examination Max. Marks: 40

Q1. Four chairs A, B, C and D (with sensors) are placed in a row as shown below.

Each chair may be occupied (indicated by sensor as logic 1) or empty (indicated by sensor as
logic 0). The output Z is logic 1 if three or more chairs are full; otherwise it is logic 0.
(a) Write the truth table for Z. Draw the ROBDD with variable ordering (A, B, C, D) for the
combinational block. Will there be any effect on the ROBDD, if there is a change in the variable
ordering?
(b) Implement the combinational block using the least number of LUTs. Assume only 3-input, 2-
output LUTs are available for your design and one of the LUT’s input variables a2 a1 a0 should be
B C D respectively and both the output of this LUT must be used. [6+6=12]

Q2. For the following operations


A = p + (q × r)
B = (q × r) – (s × t)
C = (t – u) × (u + v)
D = (v × w) + (t – u)
E = (A – B) + C
F = (D × C) + B
Assume that multiplication requires 50 clock cycle delay, add/sub requires 25 clock cycle delay,
data transmission delay is negligible.
(a) Draw the Data flow graph for the above function.
(b) Apply ASAP algorithm and draw the resulting graph showing the start time for each node.
(c) Apply ALAP algorithm and draw the resulting graph showing the computation delay and start
time for each node. (The maximum computation delay is same as that of ASAP algorithm)
(d) The priority for the nodes is based on the number of successors. With these priorities,
schedule the operations using list scheduling with a restriction on resources. Assume only two
multipliers, one adder and one subtractor blocks are available.
(e) For a FPGA with 150 LUTs multiplication, addition, and subtraction requires 100, 30, and 40
LUTs respectively. Use list scheduling for temporal partitioning the above function and also find
the quality of partitioning. [1+2+2+5+5=15]

Q3. Apply Chortle-crf LUT-mapping algorithm for the expression below with K=4: (show all the
steps of the algorithm) [8]
Y = AB + CD + EFGHI + JK

Q4. Show how to implement the fastest 4-bit adder in Xilinx CLB. Clearly give the speed in terms
of the delay of components used [05]

You might also like