INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY

ELECTRICAL ENGINEERING DEPARTMENT

Solution to End Semester Examination
PART-2
Q–1 In a carry look ahead adder, we express the output carry from a bit not as a function of the
input carry to the same bit but as a function of carry input to a previous bit. Carry output
of a 2 bit look ahead adder stage is given as:
c2 = a1 · b1 + a0 · b0 · (a1 + b1 ) + c0 · (a0 + b0 ) · (a1 + b1 )
We want to implement this function using four phase dynamic logic. a0 , b0 , c0 , a1 and b1 are
available in phase 1 only. (Complements of these signals are not provided and these will not
be available in phase 1 of the next clock).

Give a logic diagram for the 4 phase dynamic logic implementation of this function, specify-
ing the type of each gate, subject to the constraint that no more than 2 inputs are permitted
for each gate. The design should minimize delay, complexity and input loading (in that or-
der of preference).
The diagram should be neatly drawn.
Soln. 1)

c2 = a1 b1 + a0 b0 (a1 + b1) + c0 (a0 + b0) . (a1 + b1)

a0
1
a0.b0
b0 a0.b0.(a1+b1)
2
a1
1 a1+b1
b1 3
a1 a1.b1 a1.b1 G c2
1 2 4
b1 P.c0
b0 a1+b1 P
2
a0 1 3
a0+b0 c0
c0 c0
1 2

– [3]
Q–2 We want to design a 3-4 fork to drive a large output driver using logical effort based con-
siderations to equalize and optimize the delays through the two inverter chains.

VDD
Datain
Out

(The unit of time is τ , the delay of a unit inverter driving another without including the
parasitic delay. The unit of width is the width of the nMOS transistor in the unit inverter
and the unit of capacitance is the input capacitance of the unit inverter).
You are given that the width of the final nMOS transistor is 512 units. The mobility
correction factor γ is 2, and therefore the width of the final pMOS load is 1024 units. The
parasitic delay of an inverter is 2.25 units. The total load presented by the two branches at
the input should be 4.5 units.
1
 a) Find the input capacitances of the first inverters in the two branches such that the
total load presented by the input is 4.5 units and delay through the inverter chains is
equal and optimum. (Iterative solution may be needed. All intermediate results for
the iterative solution should be reported in your written answer. Your answer should
be accurate at least to two places of decimal).
Soln. 2-a) Let the input capacitance of the first inverter in the upper branch be 4.5r, while
that of the first inverter in the lower branch is 4.5(1 − r). This ensures that the total
capacitive load at the input is 4.5.

In the upper branch, the size of pMOS load is 1024.

Since a transistor width of (1 + γ) = 1 + 2 = 3 represents a unit capacitive load, this
represents a load equivalent to 1024/3.

1024/3
G = 1, B = 1, H = = 75.85185/r F = GBH = 75.85185/r
4.5r

Since there are three stages, fˆ1 = (75.85185)1/3 r −1/3 = 4.233069r −1/3
Delay in the upper branch = 3fˆ1 + 3pinv = 12.69921r −1/3 + 6.75

In the lower branch, the nMOS load is a width of 512, which is equivalent to 512/3
inverters.
512/3
G = 1, B = 1, H = = 37.92593/(1 − r) F = GBH = 37.92593/(1 − r)
4.5(1 − r)

Since there are four inverters in the lower branch,

fˆ2 = (37.92593)( 1/4)(1 − r)−1/4 = 2.481613(1 − r)−1/4
Delay in the lower branch is = 4fˆ2 + 4pinv = 9.926452(1 − r)−1/4 + 9
Equating the two delays, we get

12.69921r −1/3 − 9.926452(1 − r)−1/4 − 2.25 = 0

Define f (r) ≡ 12.69921r −1/3 − 9.926452(1 − r)−1/4 − 2.25

Then f ′ (r) = −(12.69921/3)r −4/3 − (9.926452/4)(1− r)−5/4
Or f ′ (r) = − 4.233069r −4/3 + 2.481613(1 − r)−5/4
Let us start with a guess value of 0.5 for r.
g f f’ next g
0.5 1.945393 -16.56897 0.6174118
0.6174118 .0421812 -16.29917 0.6199997
0.6199997 −3.265671 × 10−5 16.32466 0.6199977
0.6199977 −2.029370 × 10−11 16.32464 0.6199977
This gives r ≈ 0.62. Input capacitances for first inverters in the upper and lower
branches are 4.5r and 4.5(1 − r).
So input capacitance for the first inverter in the upper branch = 2.79
and input capacitance for the first inverter in the lower branch = 1.71
– [4]
b) Find the size factors for all the inverters.
Soln. 2-b) r = 0.6199977 ≈ 0.62
fˆ1 = 4.233069r −1/3 = 4.964308
Since these are inverters, size factor is the same as Cin .
In the upper branch,
Size factor for first inverter = 2.79
Size factor for second inverter = 2.79 × fˆ1 = 13.85
Size factor for third inverter = 13.85 × fˆ1 = 68.76
2
 Just for verification, we can see that the output capcitance of the third inverter is
68.76 × fˆ1 = 341.333 which is 1024/3.

In the lower branch, fˆ2 = 2.481613(1 − r)−1/4 = 3.160731

Size factor for first inverter = 4.5(1 − r) = 1.71
Size factor for second inverter = 1.71 × fˆ2 = 5.4049 ≈ 5.40
Size factor for third inverter = 5.4049 × fˆ2 = 17.08338 ≈ 17.08
Size factor for fourth inverter = 17.08338 × fˆ2 = 53.99595 ≈ 54.00
For verification, we can see that the output capacitance of the fourth inverter is
53.99595 × fˆ2 = 170.667, which is 512/3. – [2]
c) Find the total delay through the inverter chains and the mismatch in delays if the
actual load presented by nMOS and pMOS transistors is 20% higher (without any
change in the designed inverter chains).
Soln. 2-c) Delay in the upper chain for given load is 3fˆ1+3pinv = 3×4.964308+6.75 = 21.643
Delay in the lower chain for given load is 4fˆ3 = 4pinv = 4 × 3.160731 + 9 = 21.643,
which matches nicely.
If the loads are 20% higher in both branches, only the last inverters see the changed
load. other inverters are loaded with the same inverter sizes.
Changed delay for the final inverter in the upper branch is:
gbh + pinv = 1 × 1 × 1.2 × 1024/(3 × 68.76) + 2.25 = 8.2072
So the total delay in the upper branch with 20% higher load is 2fˆ1 + 2pinv + 8.2072 =
22.6358
Changed delay for the final inverter in the lower branch is:
gbh + pinv = 1 × 1 × 1.2 × 512/(3 × 53.99595) + 2.25 = 6.042877
Total delay for the lower branch with 20% higher load is 3fˆ2 + 3pinv + 6.042877 =
22.27507
The mismatch is therefore 22.27507 − 22.6358 ≈ 0.36 which is approximately 1.67% of
the delay with correct load. – [1]

– [Q2: 4 + 2 + 1 = 7 marks]

Q–3 In a Brent Kung logarithmic adder, Generate and Pass signals are successively computed
over groups of 1 bit, 2bits, 4bits, . . . in a tree structure. Assume that logic functions AND,
XOR, A + B.C as well as A.B + C.(A+B) take the same amount of time, which will define
1 slot of time for this question.
Internal carry signals are required for computing the sum outputs and are generated from
the input carry with P and G signals, using the logic functions listed above. We map G00 to
a0 · b0 + c0 · (a0 + b0 ) (which is actually c1 ) instead of just a0 · b0 .

a) For a 32 bit Brent Kung adder, list which of the P and G signals and internal carries
will be generated from which inputs in each slot of time.
Soln. 3-a) The single Bit G and P values are given by

Pi0 = ai ⊕ bi , G0i = ai · bi , except G00 = ai · bi + c0 · (a0 + b0 )

All these functions can be computed in one unit of time from ai , bi and input carry
c0 . So these are all ready at the end of the first time slot.
c1 = G00 . Therefore c1 is ready at the end of first slot.

All higher order G and P values are computed as

G = Gu + Pu · Gl , P = Pu · Pl

where u and l stand for upper half range and lower half range for a range of bit indices.
These also can be computed within one time slot. Thus a higher order of G and P
values, (successively covering twice the range of indices for the previous order) will be
3
available in each time slot.
Computation of internal carries can be carried out using the function

C = G + P · Cin

This also takes one time slot, but can be performed only after the needed Cin , P and
G values are available.
G and P values for single bits are available at the end of first slot.
G and P values spanning groups of 2 bits are available at the end of second slot.
G and P values spanning groups of 4 bits are available at the end of third slot.
G and P values spanning groups of 8 bits are available at the end of fourth slot.
G and P values spanning groups of 16 bits are available at the end of fifth slot.
Finally, G and P values spanning the full word of 32 bits are available at the end of
sixth slot.
The lowest index G value for any order i is automatically the carry value for bit index
2i . Given this information, we can show the sequence of generation of carry values by
the following diagram:
32 Cout

00 Cin
Carry input to bit number:
31
30
29
28
27
26
25
24
23
22
21
20

09
08
07
06
05
04
03
02
01
19
18
17
16
15
14
13
12
11
10
0
1 G0 P0
2 G1 P1
3 G2 P2
4 G3 P3
Time slot

5 G4 P4
6 G5
7
8
9

• at time =0, all ai , bi and c0 are available.

• at time =1, all Pi0 and G0i are available. c1 = G00 is available.
• at time =2, all 2 bit P and G values (P..1 and G1.. ) are available. c2 = G11−0 .
• at time =3, all 4 bit P and G values (P..2 and G2.. ) are available. c4 = G23−0 .
c3 ← c2 using G03 , P30 and c2 .
• at time =4, all 8 bit P and G values (P..3 and G3.. ) are available. c8 = G37−0 .
c5 ← c4 using G04 , P40 and c4 .
1
c6 ← c4 using G15−4 , P5−4 and c4 .
• at time =5, all 16 bit P and G values (P..4 and G4.. ) are available. c16 = G415−0 .
c7 ← c6 using G06 , P60 and c6 .
c9 ← c8 using G8 0, P80 and c8 .
c10 ← c8 using G19−8 , P9−81 and c8 .
2
c12 ← c8 using G11−8 , P11−82 and c8 .
5
• at time =6, G31−0 is generated. This is the value of c32 = Cout . P31−0 5 is not
required.
c11 ← c10 using G010 , P100 and c .
10
0 0
c13 ← c12 using G12 , P12 and c12 .
1
c14 ← c12 using G113−12 , P13−12 and c12 .
0 0
c17 ← c16 using G16 , P16 and c16 .
1
c18 ← c16 using G117−16 , P17−16 and c16 .
2 2
c20 ← c16 using G19−16 , P19−16 and c16 .
3
c24 ← c16 using G323−16 , P23−16 and c16 .

• at time =7, all G and P values for groups of 1, 2, 4, 8 and 16 bits are already
available.
0 and c .
c15 ← c14 using G014 , P14 14
0 0
c19 ← c18 using G18 , P18 and c18 .
4
 c21 ← c20 using 0 and c .
G020 , P20 20
c22 ← c20 using 1
G121−20 , P21−20 and c20 .
c25 ← c24 using 0 and c .
G024 , P24 24
c26 ← c24 using 1
G125−24 , P25−24 and c24 .
c28 ← c24 using 2 2
G27−24 , P27−24 and c24 .

• at time =8, we have computed:

0 and c .
c23 ← c22 using G022 , P22 22
0 and c .
c27 ← c26 using G026 , P26 26
0 and c .
c29 ← c28 using G028 , P28 28
1 1
c30 ← c28 using G29−28 , P29−28 and c28 .

• at time =9, we have computed:

0 and c .
c31 ← c30 using G030 , P30 30

– [3]
b) Taking the example of adding B7A56893H to 506A980CH with an input carry of ‘1’,
list the P, G, carry and sum bits generated in each time slot.
Soln. 3-b) This answer is very detailed and such detail is not expected in student solutions.
It is adequate if just a list of bit values generated are provided in each slot.
1. In the first slot, we generate the single bit P and G values.
a 1011 0111 1010 0101 0110 1000 1001 0011
b 0101 0000 0110 1010 1001 1000 0000 1100
P 0 1110 0111 1100 1111 1111 0000 1001 1111
G0 0001 0000 0010 0000 0000 1000 0000 0001†
Pi0 = ai ⊕ bi , G0i = ai · bi †G00 is generated as a0 · b0 + c0 · (a0 + b0 )
c1 = G00 = 1

2. In the second slot, we generate P and G values spanning two bits each.
m+1 = P m · P m ,
From now on, Prange Gm+1 m m m
u l range = Gu + Pu · Gl ,
where u represents the upper half range and l represents the lower half range.
P 0 1110 0111 1100 1111 1111 0000 1001 1111
G0 0001 0000 0010 0000 0000 1000 0000 0001
P1 1 0 01 10 11 11 00 00 11
G1 0 1 00 01 00 00 10 00 01
c2 = G11−0 = 1
s0 = P00 ⊕ c0 = 1 ⊕ 1 = 0, s1 = P10 ⊕ c1 = 1 ⊕ 1 = 0.

3. In the third slot, we calculate P and G values spanning 4 bits each.

P1 1 0 0 1 1 0 1 1 1 1 0 0 00 11
G1 0 1 0 0 0 1 0 0 0 0 1 0 00 01
P2 0 0 0 1 1 0 0 1
G 2 1 0 1 0 0 1 0 1
2
c4 = G3−0 = 1. We can also compute
c3 = G02 + P20 · c2 = 0 + 1 · 1 = 1,
s2 = P20 ⊕ c2 = 1 ⊕ 1 = 0

4. In the fourth slot, we calculate P and G values spanning 8 bits each.

P2 0 0 0 1 1 0 0 1
G2 1 0 1 0 0 1 0 1
P3 0 0 0 0
G3 1 1 1 0
5
 c8 = G37−0 = 0. We can also compute
1
c5 = G04 + P40 · c4 = 0 + 1 · 1 = 1, c6 = G15−4 + P5−4 · c4 = 0 + 0 · 1 = 0.
0 0
s3 = P3 ⊕ c3 = 1 ⊕ 1 = 0, s4 = P4 ⊕ c4 = 1 ⊕ 1 = 0.

5. In the fifth slot, we calculate P and G values spanning 16 bits each.

P3 0 0 0 0
G3 1 1 1 0
P4 0 0
G4 1 1
c16 = G415−0 = 1. We can also compute
c7 = G06 + P60 · c6 = 0 + 1 · 0 = 0, c9 = G08 + P80 · c8 = 0 + 0 · 0 = 0,
c10 = G19−8 + P9−81 2
· c8 = 0 + 0 · 0 = 0, c12 = G211−8 + P11−8 · c8 = 1 + 0 · 0 = 1.
0 0
s5 = P5 ⊕ c5 = 0 ⊕ 1 = 1. s6 = P6 ⊕ c6 = 0 ⊕ 0 = 0.
s8 = P80 ⊕ c8 = 0 ⊕ 0 = 0.

4
6. In the sixth slot, we compute G531−0 = G431−16 + P31−16 5
· G415−0 . P31−0 is not re-
quired.

This gives Cout = c32 = G531−0 = 1. We can further compute:

0 ·c
c11 = G010 + P10 0 0
10 = 0 + 0 · 0 = 0, c13 = G12 + P12 · c12 = 0 + 1 · 1 = 1,
1 1 0
c14 = G13−12 + P13−12 · c12 = 0 + 1 · 1 = 1, c17 = G16 + P16 0 ·c
16 = 0 + 1 · 1 = 1,
1 1 2 2
c18 = G17−16 +P17−16 ·c16 = 1+1·1 = 1, c20 = G19−16 +P19−16 ·c16 = 1+1·1 = 1,
3
c24 = G323−16 + P23−16 · c16 = 0 + 1 · 1 = 1,
s7 = P7 ⊕ c7 = 0 ⊕ 0 = 0, s9 = P90 ⊕ c9 = 0 ⊕ 0 = 0,
0

s10 = P100 ⊕c 0
10 = 0 ⊕ 0 = 0, s12 = P12 ⊕ c12 = 1 ⊕ 1 = 0,
0
s16 = P16 ⊕ c16 = 1 ⊕ 1 = 0,

7. In the seventh slot, All the required values of P and G are already available. We
can compute:
0 ·c
c15 = G014 + P14 0 0
14 = 0 + 1 · 1 = 1 c19 = G18 + P18 · c18 = 0 + 1 · 1 = 1
c21 = G020 + P20
0 ·c 1 1
20 = 0 + 0 · 1 = 0 c22 = G21−20 + P21−20 · c20 = 1 + 0 · 0 = 1
0 0 1 1
c25 = G24 + P24 · c24 = 0 + 1 · 1 = 1 c26 = G25−24 + P25−24 · c24 = 0 + 1 · 1 = 1
c28 = G227−24 + P27−24
2 · c24 = 0 + 0 · 1 = 0
0
s11 = P11 ⊕ c11 = 0 ⊕ 0 = 0, s13 = P13 0 ⊕c
13 = 1 ⊕ 1 = 0,
0 0
s14 = P14 ⊕ c14 = 1 ⊕ 1 = 0, s17 = P17 ⊕ c17 = 1 ⊕ 1 = 0,
0 ⊕c
s18 = P18 0
18 = 1 ⊕ 1 = 0, s20 = P20 ⊕ c20 = 0 ⊕ 1 = 1,
0
s24 = P10 ⊕ c24 = 1 ⊕ 1 = 0,

8. In the eighth slot, we can compute:

0 ·c
c23 = G022 + P22 0 0
22 = 0 + 1 · 1 = 1, c27 = G26 + P26 · c26 = 0 + 1 · 1 = 1,
0 0 1 1
c29 = G28 + P28 · c28 = 1 + 0 · 1 = 1, c30 = G29−28 + P29−28 · c28 = 1 + 0 · 1 = 1.
Sums corresponding to carries computed in the previous slot can also be evaluated
as:
0 ⊕c
s15 = P15 15 = 1 ⊕ 1 = 0,
0
s19 = P19 ⊕ c19 = 1 ⊕ 1 = 0,
0 ⊕c
s21 = P21 21 = 0 ⊕ 0 = 0,
0
s22 = P22 ⊕ c22 = 1 ⊕ 1 = 0,
0 ⊕c
s25 = P25 25 = 1 ⊕ 1 = 0,
0
s26 = P26 ⊕ c26 = 1 ⊕ 1 = 0,
0 ⊕c
s28 = P28 28 = 0 ⊕ 0 = 0,

0 ·c
9. In the ninth slot, we can compute c31 = G030 + P30 30 = 0 + 1 · 1 = 1,
and the sum values
6
 s23 0 ⊕c
= P23 = 1 ⊕ 1 = 0,
23
s27 0 ⊕c
= P29 = 0 ⊕ 1 = 1,
29
s29 0 ⊕c
= P29 = 1 ⊕ 1 = 0,
29
s30 0
= P30 ⊕ c30 = 1 ⊕ 1 = 0,

0 ⊕c
10. Finally in the tenth slot, we can evaluate s31 as s31 = P31 31 = 1 ⊕ 1 = 0.
– [3]

– [Q3: 3 + 3 = 6 marks]

Q–4 The Bit and Bit lines of a static RAM using a six transistor storage cell are pulled up using
nMOS transistors, so they will pre-charge only to VDD − VT n . Assume that the word line
of a selected row is raised all the way to VDD
Bit Bit

Word Select
VDD
VDD = 1.8V, VT n = |VT p | = 0.4V, µn /µp = 2.3
M3 M4 W/L = 1 for M1 and M2.
M5 M6

M1 M2
Gnd

a) Both Bit and Bit lines are pre-charged to VDD − VT n during a read operation. Assume
that a ‘0’ is stored in the cell, so that the drain of M1 is at 0V while the drain of
M2 is high. When the word line goes high, drains of M1 and M2 are connected to
the pre-charged Bit and Bit lines through M5 and M6. As a worst case condition, as-
sume that the drain of M2 remains at VDD −VT n during the entire read cycle due to this.

To prevent read upset, we want to ensure that the drain of M1 rises no higher than
VT n . Find the maximum W/L ratio for M5 which will ensure this.
Soln. 4-a) VDD − VT n = 1.8 − 0.4 = 1.4V
During the read operation, M2 and M3 are OFF.
Drain of M5 is at VDD − VT n = 1.4V , the gate is at VDD = 1.8V while its source is
at VT n = 0.4V. Thus VDS = 1.0V and VGS = 1.4V for M5 and therefore it is just in
saturation.

Drain of M1 is at VT n = 0.4V, its gate is at VDD − VT n = 1.4V, while the source is

grounded. So, VDS = 0.4V and VGS = 1.4V. Hence M1 is in linear mode.

1
 
2
Equating currents, Kn5 (1.4 − 0.4) /2 = Kn1 (1.4 − 0.4) × 0.4 − 0.42
2

Kn5 2(1.0 × 0.4 − 0.08)

So = = 0.64
Kn1 1.0
Since both are n channel transistors, Kn5 /Kn1 = (W5 /L5 )/(W1 /L1 )
Therefore
W5 W1
= 0.64 = 0.64
L5 L1
– [3]
7
 b) During a write operation, the Bit line is charged to Data value, while the Bit line is
taken to Data. Take the case where initially, the cell has a ‘1’ stored in it, so that the
drain of M1 is at VDD , while the drain of M2 is at 0V. We want to write a ‘0’ to this
cell. For this, the Bit line will be driven to 0V, while the Bit line will go to VDD − VT n .

Assume that the W/L values for M5 and M6 are as calculated in the part above.
Therefore the drain of M2 will rise no higher than VT n . Thus M1 will remain OFF
during the entire write cycle. Find the maximum W/L value for the pMOS transistor
M3, such that the drain of M1 can be pulled below VDD /2 through M5.
Soln. 4-b) In this case, M1 and M4 are OFF, while M2 and M3 are ON in the beginning.
When M5, is turned ON, we want the voltage at the drain of M1 to drop below VDD /2.
Drain of M5 is then at VDD /2 = 0.9V, its gate is at 1.8V, while its source is at 0V.
Thus VDS = 0.9V, VGS = 1.8V for M5. Therefore it is in linear mode.
Source of M3 is at 1.8V while its gate is at 0.4V and the drain is at 0.9V. Thus
|VDS | = 0.9V, |VGS | = 1.4V for M3. So it is also in linear mode. Equation currents,
we get
1 2 1 2
   
Kn5 (1.8 − 0.4)0.9 − 0.9 = Kp3 (1.4 − 0.4)0.9 − 0.9
2 2
Kp3 (1.4 × 0.9 − 0.81/2)
=
Kn5 (1.0 × 0.9 − 0.81/2)
We have W5 /L5 = 0.64 for M5. So

µp W 3/L3 1.26 − 0.405 0.855

= = = 1.7273
µn 0.64 0.9 − 0.405 0.495
W3
= 0.64 × 2.3 × 1.7273 ≈ 2.54
L3
– [3]