D epartment of Computer Science & Information Technology

University of Engineering & Technology, Peshawar

Final term Examination

4t h
Semester, Section A, B
Course Title: Computer Architecture & Assembly Language
Time Allowed: 2hrs
Total Marks: 50

Note: Attempt All questions Draw the diagram where necessary.

QNo1. What are the basic functions of computer Architecture?

■ Ans: There are four basic functions that a computer can perform:
■ Data processing
■ Data may take a wide variety of forms and the rangeof processing
requirements is broad
■ Data storage
■ Short-term
■ Long-term
■ Data movement
■ Input-output (I/O) - when data are received from or delivere
d to a device (peripheral) that is directly connected to the computer
■ Data communications – when data are moved over longer distances, to
or from a remote device
■ Control
■ A control unit manages the computer’s resources and orchestrates the
performance of its functional parts in response to instructions

QNo2. What are the multicore computer structure? Draw the diagram of multicore
computer structure.
■ Ans: Central processing unit (CPU)
■ Portion of the computer that fetches and executes instructions
■ Consists of an ALU, a control unit, and registers
■ Referred to as a processor in a system with a single processing unit
■ Core
■ An individual processing unit on a processor chip
■ May be equivalent in functionality to a CPU on a single-CPUsystem
■ Specialized processing units are also referred to as cores
■ Processor
■ A physical piece of silicon containing one or more cores
■ Is the computer component that interprets and executes instructions
■ Referred to as a multicore processor if it contains multiple cores
QNo3. What are the embedded system? Draw the diagram of embedded system.

Ans: The use of electronics and software within a product

• Billions of computer systems are produced each year that are embedded within
larger devices
• Today many devices that use electric power have an embedded computing system
• Often embedded systems are tightly coupled to the environment
• This can give rise to real-time constraints imposed by the need to interact with the
environment
Constraints such as required speeds of motion, required precision of measurement, and
required time durations dictate the timing of software operations
• If multiple activities must be managed simultaneously it imposes more
complex real-time constraints
QNo4. What is the difference between application processors and dedicated processors?
■ Application processors
■ Defined by the processor’s ability to execute complex operating systems
■ General-purpose in nature
■ An example is the smartphone – the embedded system is designed to support
numerous apps and perform a wide variety of functions
■ Dedicated processor
■ Is dedicated to one or a small number of specific tasks required by the host
device
■ Because such an embedded system is dedicated to a specific task or tasks, the
processor and associated components can be engineered to reduce size and
cost

QNo5. Explain in details about deeply embedded systems.

Ans:

• Subset of embedded systems

• Has a processor whose behavior is difficult to observe both by the programmer and
the user
• Uses a microcontroller rather than a microprocessor
• Is not programmable once the program logic for the device has been burned into
ROM
• Has no interaction with a user
• Dedicated, single-purpose devices that detect something in the environment,
perform a basic level of processing, and then do something with the results
• Often have wireless capability and appear in networked configurations such as
networks of sensors deployed over a large area
• Typically have extreme resource constraints in terms of memory, processor size,
time, and power consumption

QNo6. What is the instruction cycle, instruction cycle state also draw the diagram of
instruction cycle.

The instruction cycle (also known as the fetch–decode–execute cycle, or simply the
fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from
boot-up until the computer has shut down in order to process instructions. It is
composed of three main stages: the fetch stage, the decode stage, and the execute
stage.

• Two steps:
▫ Fetch
▫ Execute

Instruction States;

• Instruction address calculation (iac): Determine the address of the next instruction to
be executed. Usually, this involves adding a fixed number to the address of the
previous instruction.
• Instruction fetch (if): Read instruction from its memory location into the processor.
• Instruction operation decoding (iod): Analyze instruction to determine type of
operation to be performed and operand(s) to be used.
• Operand address calculation (oac): If the operation involves reference to an operand
in memory or available via I/O, then determine the address of the operand.
• Operand fetch (of): Fetch the operand from memory or read it in from I/O.
• Data operation (do): Perform the operation indicated in the instruction.
• Operand store (os): Write the result into memory or out to I/O.
QNo7. What are the interrupts, interrupts cycle. . Also draw the diagram of interrupts with
instruction cycle.
Ans:

• Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of
processing.
Classes of Interrupts:
• Program: generated by some condition that occurs as a result of an instruction
execution e.g. arithmetic overflow, division by zero.
• Timer: generated by a timer within the processor. This allows the operating system
to perform certain functions on a regular basis.
• I/O: generated by an I/O controller, to signal normal completion of an operation or
to signal a variety of error conditions.
• Hardware failure: generated by a failure such as power failure or memory parity
error.
• Interrupts are provided primarily as a way to improve processing efficiency since
most external devices are much slower than the processor.
• Of the next figure, The user program performs a series of WRITE calls interleaved
with processing. Code segments 1, 2, and 3 refer to sequences of instructions that do
not involve I/O.
QNo8. Write assembly language program that display the contents of the array of n size
array size of array can be input by the user.

Ans:

dosseg
.MODEL small
.STACK 4096
.data
arr db 10 dup ('$')
.code
main PROC
; access the value of variable
mov ax,@data
mov ds,ax
;take length of user input
mov ah,1 ;saved in al 4
int 21h
sub al,48
mov cl,al
;line break
mov ah,2
mov dl,10
int 21h
mov dl,13
int 21h
;take user input
mov ah,1
lea si,arr ;arr=0000345
loopo:
int 21h
mov [si],al
inc si ;0000346
loop loopo
;line break
mov ah,2
mov dl,10
int 21h
mov dl,13
int 21h
;print output
lea dx,arr
mov ah,9
int 21h

mov ah,4ch
int 21h
main ENDP
END main
Output:
4
1234
1234

QNo9. Write a program in assembly language that input string from user and to print a
string in reverse order.
Ans:

dosseg
.MODEL small
.STACK 4096
.data
.code
main PROC
mov cl,5
;input string
lab1:
mov ah,1
int 21h
mov ah,0
push ax ; push ax value to stack
loop lab1
;line break
mov ah,2
mov dl,10
int 21h
mov dl,13
int 21h
mov cl,5
;output reverse string code
lab2:
pop dx ; stack top value to dx register
mov ah,2
int 21h
loop lab2
mov ah,4ch
int 21h
main ENDP
END main

Output
Hello
olleh

QNo10. What is a BUS.? Name and explain the different type of BUS.

A communication pathway connecting two or more devices

Usually broadcast.
Often grouped.
A number of channels in one bus.
e.g. 32 bit data bus is 32 separate single bit channels.
Power lines may not be shown.
There are many different bus designs, on any bus the lines can be classified
into three functional groups: data, address, and control lines.
Data Bus
• Carries data.
▫ Remember that there is no difference between “data” and
“instruction” at this level.
 • Data lines provide a path for moving data among system modules.
These lines are called the data bus.
• The number of lines being referred to as the width of the data bus.
• Width is a key determinant of performance.
▫ 8, 16, 32, 64 bit.
• Address bus
• Identify the source or destination of data.
• e.g. CPU needs to read an instruction (data) from a given location in
memory.
• Bus width determines maximum memory capacity of system.
• e.g. 8080 has 16 bit address bus giving 64k address space.
Control Bus
• Used to control the access to and the use of the data and address lines.
• Control signals transmit both command and timing information among
system modules.
• Timing signals indicate the validity of data and address information.
• Command signals specify operations to be performed.
• Control and timing information.
▫ Memory read/write signal.
▫ Interrupt request.
▫ Clock signals.