32-Bit Power Architecture MCU For Automotive General Purpose Applications - Chorus Family

SPC584Gx, SPC58EGx,
SPC58NGx
32-bit Power Architecture microcontroller for automotive ASIL-D
applications
Datasheet - production data
– Logic BIST
– FCCU for collection and reaction to failure
notifications
eTQFP144 (20 x 20 x 1.0 mm) – Memory BIST
eLQFP176 (24 x 24 x 1.4 mm)
– Cyclic redundancy check (CRC) unit
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
FPBGA292 (17 x 17 x 1.8 mm) in memories
• Crossbar switch architecture for concurrent
Features access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
• AEC-Q100 qualified • Body cross triggering unit (BCTU)
• High performance e200z4 triple core: – Triggers ADC conversions from any eMIOS
– 32-bit Power Architecture technology CPU channel
– Core frequency as high as 180 MHz – Triggers ADC conversions from up to 2
– Variable Length Encoding (VLE) dedicated PIT_RTIs
– Floating Point, End-to-End Error Correction • Enhanced modular IO subsystem (eMIOS): up
• 6582 KB (6144 KB code flash+ 256 KB data to 64 timed IO channels with 16-bit counter
flash) on-chip flash memory: resolution
– supports read during program and erase • Enhanced analog-to-digital converter system
operations, and multiple blocks allowing with:
EEPROM emulation – 4 independent fast 12-bit SAR analog
– Supports read while read between the two converters
code Flash partitions. – One supervisor 12-bit SAR analog
• 608 KB on-chip general-purpose SRAM (in converter
addition to 160 KB core local data RAM): 64KB – One standby 10-bit SAR analog converter
in CPU_0, 64 KB in CPU_1 and 32 KB in • Communication interfaces:
CPU_2 – 18 LINFlexD modules
• 182 KB HSM dedicated flash memory (144 KB – 10 deserial serial peripheral interface
code + 32 KB data) (DSPI) modules
• Multi-channel direct memory access controller – 8 MCAN interfaces with advanced shared
(eDMA) memory scheme and ISO CAN-FD support
– one eDMA with 64 channels – Dual-channel FlexRay controller
– one eDMA with 32 channels – Two independent Ethernet controllers
• 1 interrupt controller (INTC) 10/100Mbps compliant IEEE 802.3-2008
• Comprehensive new generation ASIL-D safety • Low power capabilities
concept: – Versatile low power modes
– ASIL-D of ISO 26262 – Ultra low power standby with RTC
– One CPU channel in lockstep – Smart Wake-up Unit for contact monitoring
July 2019 DS11758 Rev 6 1/139

This is information on a product in full production. www.st.com
SPC584Gx, SPC58EGx and SPC58NGx
– Fast wakeup schemes

• Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
• Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some
support for 2010 standard
• Boot assist Flash (BAF) supports factory programming using a serial bootload through the
asynchronous CAN or LIN/UART
• Junction temperature range -40 °C to 150 °C
Table 1. Device summary

Part number
Package 4 MB 6 MB
Single core Dual core Triple core Single core Dual core Triple core
eTQFP144 SPC584G80E5 SPC58EG80E5 SPC58NG80E5 SPC584G84E5 SPC58EG84E5 SPC58NG84E5

eLQFP176 SPC584G80E7 SPC58EG80E7 SPC58NG80E7 SPC584G84E7 SPC58EG84E7 SPC58NG84E7
FPBGA292 SPC584G80C3 SPC58EG80C3 SPC58NG80C3 SPC584G84C3 SPC58EG84C3 SPC58NG84C3
2/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Table of contents
Table of contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 14
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 21
4.4 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 23
4.6 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8.3 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.9 Reset pad (PORST, ESR0) electrical characteristics . . . . . . . . . . . . . . . . 39
4.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.11.2 Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.11.3 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.11.4 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.12 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DS11758 Rev 6 3/139

5
Table of contents SPC584Gx, SPC58EGx, SPC58NGx
4.12.2 SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.12.3 SAR ADC 10 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.13 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.14 LFAST pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.14.1 LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.14.2 LFAST and MSC/DSPILVDS interface electrical characteristics . . . . . . 60
4.14.3 LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.15 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.15.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.15.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.15.3 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.16 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.17 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.17.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.17.2 DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.17.3 Ethernet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.17.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.17.5 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.17.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.17.7 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.1 eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.1.1 Package mechanical drawings and data information . . . . . . . . . . . . . 111
5.2 eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.3 FPBGA292 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
5.4 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.4.1 eTQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.4.2 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.4.3 FPBGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.4.4 General notes for specifications at maximum junction temperature . . 122
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Table of contents
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
DS11758 Rev 6 5/139

5
Introduction SPC584Gx, SPC58EGx, SPC58NGx
1 Introduction
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.
6/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Description
2 Description
The SPC584Gx, SPC58EGx, SPC58NGx microcontroller belongs to a family of devices

superseding the SPC56x family. SPC584Gx, SPC58EGx, SPC58NGx build on the legacy of
the SPC5x family, while introducing new features coupled with higher throughput to provide
substantial reduction of cost per feature and significant power and performance
improvement (MIPS per mW).
2.1 Device feature summary

Table 2 lists a summary of major features for the SPC584Gx, SPC58EGx, SPC58NGx
device. The feature column represents a combination of module names and capabilities of
certain modules. A detailed description of the functionality provided by each on-chip module
is given later in this document.
Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary

Feature Description
SPC58 family 40 nm
Computing Shell 0
Number of cores up to 2
Number of checker cores up to 1
16 KB instruction
Local RAM
64 KB data
Single precision floating point Yes
SIMD (LSP) No
VLE Yes
8 KB instruction
Cache
4 KB data
Computing Shell 1
Number of cores 1
Number of checker cores 0
16 KB instruction
Local RAM
32 KB data
Single precision floating point Yes
SIMD (LSP) Yes
VLE Yes
Cache 8 KB instruction
DS11758 Rev 6 7/139

13
Description SPC584Gx, SPC58EGx, SPC58NGx
Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary (continued)

Feature Description
Other
Core MPU: 24 per CPU

MPU
System MPU: 24 per XBAR
Semaphores Yes
CRC channels 2x4
Software Watchdog Timer (SWT) 4
Core Nexus class 3+
4 x SCU
Event processor
4 x PMC
Run control module Yes
System SRAM 608 KB (including 256 KB of standby RAM)
Flash 6144 KB code / 256 KB data
Flash fetch accelerator 2 x 2 x 4 x 256-bit
Flash overlay RAM 2 x 16 KB
DMA channels 96
DMA Nexus class 3
LINFlexD 18
M_CAN supporting CAN-FD
8
according to ISO 11898-1 2015
DSPI 10
I2C 1
FlexRay 1 x dual channel
Ethernet 2 MAC with time stamping, AVB and VLAN support
SIPI / LFAST interprocessor bus High speed
8 PIT channels
System timers 4 AUTOSAR® (STM)
RTC/API
eMIOS 2 x 32 channels
BCTU 64 channels
Interrupt controller > 710 sources
ADC (SAR) 6
Temperature sensor Yes
Self test controller Yes
PLL Dual PLL with FM
Integrated linear voltage regulator Yes
8/139 DS11758 Rev 6

Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary (continued)

Feature Description
External power supplies 3.3 V - 5 V

Stop mode
Halt mode
Low power modes
Smart standby with output controller, analog and digital inputs
Standby mode
DS11758 Rev 6 9/139

13
2.2 Block diagram

The figures below show the top-level block diagrams.
Figure 1. Block diagram
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10/139 DS11758 Rev 6

Figure 2. Periphery allocation
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DS11758 Rev 6 11/139

13
2.3 Features
On-chip modules within SPC584Gx, SPC58EGx, SPC58NGx include the following features:
• Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), one paired in
lock-step
– Power architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight signal processing auxiliary processing unit (LSP APU) instruction
support for digital signal processing (DSP) on Core_2
– 16 KB local instruction RAM and 64 KB local data RAM for Core_0 and Core_1,
16 KB local instruction RAM and 32 KB local data RAM for Core_2
– 8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_1, 8kB I-Cache for Core_2
• 6400 KB (6144 KB code flash + 256 KB data flash) on-chip Flash memory
– Supports read during program and erase operations, and multiple blocks allowing
EEPROM emulation
– Supports read while read between the two code Flash partitions
• 608 KB on-chip general-purpose SRAM (+ 160 KB data RAM included in the CPUs)
• 182 KB HSM dedicated flash memory (144 KB code + 32 KB data)
• Multi channel direct memory access controllers (eDMA paired in lock-step)
– One eDMA with 64 channels
– One eDMA with 32 channels
• One interrupt controller (INTC) in lock-step
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
• Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM
from multiple bus masters with end-to-end ECC
• Hardware security module (HSM) to provide robust integrity checking of Flash memory
• System integration unit lite (SIUL)
• Boot assist Flash (BAF) supports factory programming using a serial bootload through
the asynchronous CAN or LIN/UART
• Hardware support for motor control and safety related applications
• Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with
16-bit counter resolution
– Buffered updates
– Support for shifted PWM outputs to minimize occurrence of concurrent edges
– Supports configurable trigger outputs for ADC conversion for synchronization to
channel output waveforms
– Shared or independent time bases
– DMA transfer support available
12/139 DS11758 Rev 6

• Body cross triggering unit (BCTU)

– Triggers ADC conversions from any eMIOS channel
– Triggers ADC conversions from up to 2 dedicated PIT_RTIs
– One event configuration register dedicated to each timer event allows to define the
corresponding ADC channel
– Synchronization with ADC to avoid collision
• Enhanced analog-to-digital converter system with:
– Four independent fast 12-bit SAR analog converters
– One supervisor 12-bit SAR analog converter
– One 10-bit SAR analog converter with STDBY mode support
• Ten deserial serial peripheral interface (DSPI) modules
• Eighteen LIN and UART communication interface (LINFlexD) modules
– LINFlexD_0 is a master/slave
– All others are masters
• Eight modular controller area network (MCAN) modules, all supporting flexible data
rate (CAN-FD)
• Dual-channel FlexRay controller
• Two ethernet controllers 10/100 Mbps, compliant IEEE 802.3-2008
– IEEE 1588-2008 Time stamping (internal 64-bit time stamp)
– IEEE 802.1AS and IEEE 802.1Qav (AVB-Feature)
– IEEE 802.1Q VLAN tag detection
– IPv4 and IPv6 checksum modules
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some
support for 2010 standard
• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
• Standby power domain with smart wake-up sequence
DS11758 Rev 6 13/139

13
Package pinouts and signal descriptions SPC584Gx, SPC58EGx, SPC58NGx
3 Package pinouts and signal descriptions
Refer to the SPC584Gx, SPC58EGx, SPC58NGx IO_ Definition document.

It includes the following sections:
1. Package pinouts
2. Pin descriptions
a) Power supply and reference voltage pins
b) System pins
c) LVDS pins
d) Generic pins
14/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics
4 Electrical characteristics
4.1 Introduction
The present document contains the target Electrical Specification for the 40 nm family 32-bit
MCU SPC584Gx, SPC58EGx, SPC58NGx products.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol”
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” (System Requirement) is included in the
“Symbol” column.
The electrical parameters shown in this document are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 3 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 3. Parameter classifications

Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
C Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T Those parameters are achieved by design validation on a small sample size from typical
devices.
D Those parameters are derived mainly from simulations.
DS11758 Rev 6 15/139

15
Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx
4.2 Absolute maximum ratings

Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Stress beyond the listed maxima, even momentarily, may affect device reliability or cause
permanent damage to the device.
Table 4. Absolute maximum ratings

Value
Symbol C Parameter Conditions Unit
Min Typ Max
Core voltage
VDD_LV SR D operating life — –0.3 — 1.4 V
range(1)
Buddy device
voltage
VDD_LV_BD SR D — –0.3 — 1.5 V
operating life
range(2)
VDD_HV_IO_MAIN
VDD_HV_IO_FLEX I/O supply
SR D — –0.3 — 6.0 V
VDD_HV_OSC voltage(3)
VDD_HV_FLA
ADC ground Reference to
VSS_HV_ADV SR D –0.3 — 0.3 V
voltage digital ground
ADC Supply Reference to
VDD_HV_ADV SR D –0.3 — 6.0 V
voltage(3) VSS_HV_ADV
SAR ADC
VSS_HV_ADR_S SR D ground — –0.3 — 0.3 V
reference
SAR ADC
Reference to
VDD_HV_ADR_S SR D voltage –0.3 — 6.0 V
VSS_HV_ADR_S
reference(3)
VSS_HV_ADR_S
VSS-VSS_HV_ADR_S SR D differential — –0.3 — 0.3 V
voltage
VSS_HV_ADV
VSS-VSS_HV_ADV SR D differential — –0.3 — 0.3 V
voltage
— –0.3 — 6.0
Relative to Vss –0.3 — —
I/O input voltage
VIN SR D V
range(3)(4) (5) Relative to
VDD_HV_IO and — — 0.3
VDD_HV_ADV
Digital Input pad
TTRIN SR D — — — 1 ms
transition time(6)
16/139 DS11758 Rev 6

Table 4. Absolute maximum ratings (continued)

Value
Min Typ Max
Maximum DC
injection current
IINJ SR T for each — –5 — 5 mA
analog/digital
PAD(7)
Maximum non-
operating
TSTG SR T Storage — –55 — 125 °C
temperature
range
Maximum
nonoperating
TPAS SR C temperature — –55 — 150(8) °C
during passive
lifetime
Maximum
No supply; storage
storage time,
temperature in
TSTORAGE SR — assembled part — — 20 years
range –40 °C to
programmed in
60 °C
ECU
Maximum solder
TSDR SR T temperature Pb- — — — 260 °C
free packaged(9)
Moisture
MSL SR T sensitivity — — — 3 —
level(10)
Typical range for
X-rays source
Maximum
during
TXRAY dose SR T cumulated — — 1 grey
inspection:80 ÷
XRAY dose
130 KV; 20 ÷
50 μA
1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed
1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3:
Operating conditions.
2. VDD_LV_BD: allowed 1.450 V - 1.500 V for 60 seconds cumulative time at the given temperature profile. Remaining time
allowed 1.375 V - 1.450 V for 10 hours cumulative time at maximum TJ = 125 °C. Remaining time as defined in Section 4.3:
Operating conditions.
3. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative
time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating
conditions.
4. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin
to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal
calculations.
5. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
DS11758 Rev 6 17/139

18
6. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum
limits to the transition time.
7. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
8. 175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to
confirm that are granted by product qualification.
9. Solder profile per IPC/JEDEC J-STD-020D.
10. Moisture sensitivity per JDEC test method A112.
18/139 DS11758 Rev 6

4.3 Operating conditions

Table 5 describes the operating conditions for the device, and for which all the specifications
in the data sheet are valid, except where explicitly noted. The device operating conditions
must not be exceeded or the functionality of the device is not guaranteed.
Table 5. Operating conditions

Value(1)
Min Typ Max
Operating
FSYS SR P system clock — — — 180 MHz
frequency(2)
Operating
TA_125 Grade(3) SR D Ambient — –40 — 125 °C
temperature
Junction
TJ_125 Grade(3) SR P temperature TA = 125 °C –40 — 150 °C
under bias
Ambient
TA_105 Grade(3) SR D temperature — –40 — 105 °C
under bias
Operating
TJ_105 Grade(3) SR D Junction TA = 105 °C –40 — 130 °C
temperature
Core supply
VDD_LV SR P — 1.14(5) 1.20 1.26(6) (7) V
voltage(4)
VDD_HV_IO_MAIN
VDD_HV_IO_FLEX IO supply
SR P — 3.0 — 5.5 V
VDD_HV_FLA voltage
VDD_HV_OSC
ADC supply
VDD_HV_ADV SR P — 3.0 — 5.5 V
voltage
VSS_HV_ADV- ADC ground

SR D differential — –25 — 25 mV
VSS
voltage
SAR ADC
VDD_HV_ADR_S SR P reference — 3.0 — 5.5 V
voltage
SAR ADC
VDD_HV_ADR_S- reference
SR D — — — 25 mV
VDD_HV_ADV differential
voltage
SAR ADC
ground
VSS_HV_ADR_S SR P — VSS_HV_ADV V
reference
voltage
DS11758 Rev 6 19/139

21
Table 5. Operating conditions (continued)

Value(1)
Min Typ Max
VSS_HV_ADR_S
VSS_HV_ADR_S-
SR D differential — –25 — 25 mV
VSS_HV_ADV
voltage
Slew rate on
VRAMP_HV SR D HV power — — — 100 V/ms
supply
I/O input
VIN SR P — 0 — 5.5 V
voltage range
Injection
current (per
pin) without Digital pins and
IINJ1 SR T –3.0 — 3.0 mA
performance analog pins
degradation(8)
(9) (10)
Dynamic
Injection
current (per
Digital pins and
IINJ2 SR D pin) with –10 — 10 mA
analog pins
performance
degradation(10)
(11)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the
Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.
3. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to
Section 5.4: Package thermal characteristics.
4. Core voltage as measured on device pin to guarantee published silicon performance.
5. In the range [1.14-1.08]V, the device functionality and specifications are granted and the device is expected to receive a
flag by the internal LVD100 monitors to warn that the regulator (internal or external), providing the VDD_LV supply, exited the
expected operating conditions. If the internal LVD100 monitors are disabled by the application, then an external voltage
monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented. Refer to
Section 4.15.3: Voltage monitors for the list of available internal monitors and to the Reference Manual for the
configurability of the monitors.
6. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that
HVD134_C monitor reset is disabled.
7. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to
1.236 V at the given temperature profile.
8. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these
limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements.
9. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is
above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
10. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
11. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not
granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for
maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011),
Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).
20/139 DS11758 Rev 6

Table 6. PRAM wait states configuration

PRAMC WS Clock Frequency (MHz)
1 < 180
0 < 120
4.3.1 Power domains and power up/down sequencing

The following table shows the constraints and relationships for the different power domains.
Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and
column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as
well as during normal device operation.
Table 7. Device supply relation during power-up/power-down sequence

Supply2
VDD_HV_IO_MAIN
VDD_LV VDD_HV_IO_FLEX VDD_HV_FLA VDD_HV_ADV VDD_HV_ADR
VDD_HV_OSC
VDD_HV_IO_FLEX ok not allowed ok ok

VDD_LV(1) ok ok ok ok
VDD_HV_IO_MAIN
Supply1
VDD_HV_FLA ok ok ok ok
VDD_HV_OSC
VDD_HV_ADV ok ok not allowed ok
VDD_HV_ADR ok ok not allowed not allowed
1. VDD_LV can be higher than VDD_HV supplies only during power-up/down transient ramps, in case of external LV regulator
and if VDD_HV supply voltage level is lower than VDD_LV allowed max operating condition.
During power-up, all functional terminals are maintained in a known state as described in
the device pinout Microsoft Excel file attached to the IO_Definition document.
DS11758 Rev 6 21/139

21
4.4 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device:
• All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits,
• Device failure is defined as: “If after exposure to ESD pulses, the device does not meet
the device specification requirements, which include the complete DC parametric and
functional testing at room temperature and hot temperature, maximum DC parametric
variation within 10% of maximum specification”.
Table 8. ESD ratings

Parameter C Conditions Value Unit
ESD for Human Body Model (HBM)(1) T All pins 2000 V

T All pins 500 V
ESD for field induced Charged Device Model (CDM)(2)
T Corner Pins 750 V
1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.
2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.
22/139 DS11758 Rev 6

4.5 Electromagnetic compatibility characteristics

EMC measurements at IC-level IEC standards are available from STMicroelectronics on
request.
DS11758 Rev 6 23/139

23
4.6 Temperature profile

The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL
1,000 h and HTDR 1,000 hrs, TJ = 150 °C.
24/139 DS11758 Rev 6

4.7 Device consumption

Table 9. Device consumption
Value(1)
Min Typ Max
C TJ = 40 °C — — 26
D TJ = 25 °C — — 18
D Leakage current on the TJ = 55 °C — — 36
IDD_LKG(2),(3) CC mA
D VDD_LV supply TJ = 95 °C — — 90
D TJ = 120 °C — — 160
P TJ = 150 °C — — 320
Dynamic current on
the VDD_LV supply,
IDD_LV(3) CC P — — — 400 mA
very high consumption
profile(4)
Total current on the
IDD_HV CC P fMAX — — 85 mA
VDD_HV supply(4)
Dynamic current on
IDD_LV_GW CC T the VDD_LV supply, — — — 310 mA
gateway profile(5)
Dynamic current on
IDD_HV_GW CC T the VDD_HV supply, — — — 46 mA
gateway profile(5)
Dynamic current on
IDD_LV_BCM CC T the VDD_LV supply, — — — 280 mA
body profile(6)
Dynamic current on
IDD_HV_BCM CC T the VDD_HV supply, — — — 49 mA
body profile(6)
Main Core dynamic
IDD_MAIN_CORE_AC CC T fMAX — — 50 mA
current(7)
Checker Core dynamic
IDD_CHKR_CORE_AC CC T fMAX — — 30 mA
operating current
HSM platform dynamic
IDD_HSM_AC CC T fMAX/2 — — 20 mA
operating current(8)
Dynamic current on
(9) the VDD_LV supply
IDDHALT CC T — — 110 180 mA
+Total current on the
VDD_HV supply
Dynamic current on
the VDD_LV supply
IDDSTOP(10) CC T — — 21 40 mA
+Total current on the
VDD_HV supply
DS11758 Rev 6 25/139

27
Table 9. Device consumption (continued)

Value(1)
Min Typ Max
D TJ = 25 °C — 145 380
C Total standby mode TJ = 40 °C — — 550 µA
current on VDD_LV and
IDDSTBY8 CC D TJ = 55 °C — — 820
VDD_HV supply, 8 KB
D RAM(11) TJ = 120 °C — — 4
mA
P TJ = 150 °C — — 8
D TJ = 25 °C — 170 530 µA
C Total standby mode TJ = 40 °C — — 790 µA
IDDSTBY128 CC D TJ = 55 °C — — 1.2
VDD_HV supply,
D 128 KB RAM(11) TJ = 120 °C — — 5.5 mA
P TJ = 150 °C — — 11
D TJ = 25 °C — 200 680 µA
C Total standby mode TJ = 40 °C — — 1.0 mA
IDDSTBY256 CC D TJ = 55 °C — — 1.5
VDD_HV supply,
D 256 KB RAM(11) TJ = 120 °C — — 7 mA
P TJ = 150 °C — — 14
SSWU running over all
STANDBY period with
IDDSSWU1 CC D OPC/TU commands TJ = 40 °C — 1.0 3.5 mA
execution and keeping
ADC off(12)
SSWU running over all
STANDBY period with
OPC/TU/ADC
IDDSSWU2 CC D TJ = 40 °C — 3.5 5.0 mA
commands execution
and keeping ADC
on(13)
Buddy Device
IDD_LV_BD CC P Consumption on TJ = 150 °C — — 500 mA
VDD_LV supply(14)
Buddy Device
IDD_HV_BD CC T Consumption on — — — 130 mA
VDD_HV supply(14)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered,
and they are computed in the dynamic IDD_LV and IDD_HV parameters.
3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the
consumption contributors. The tests used in validation, characterization and production are verifying that the total
consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The two
parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and
the software profile used.
26/139 DS11758 Rev 6

4. Use case: 3 x e200Z4 @180 MHz with all locksteps on (main core + dma + irq), HSM @90 MHz, all IPs clock enabled,
Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, 1xSARADC in
continuous conversion, DMA continuously triggered by ADC conversion, 5xDSPI / 7xCAN / 12xLINFlex / FlexRay,
1xEMIOS running (5 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated
for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the
software configuration are available separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected
temperature.
5. Gateway use case: Two cores running at 160 MHz, no lockstep, DMA, PLL, FLASH read only 25%, 8xCAN, 1xEthernet,
HSM, 4xSARADC.
6. BCM use case: One Core running at 160 MHz, no lockstep, DMA, PLL, FLASH read only 25%, 2xCAN, HSM, 5xSARADC.
7. Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution.
8. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code
Book crypto algorithm on 1 block of 16 byte of shared RAM.
9. Flash in Low Power. Sysclk at 160 MHz, PLL0_PHI at 160 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off.
MCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON (configured but no
reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.
10. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power
down mode.
11. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.
12. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total
standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size
and temperature.
13. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous
conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the
selected memory size and temperature.
14. Worst case usage (data trace, data overlay, full Aurora utilization). If Aurora and JTAGM/LFAST not used, VDD_LV_BD
current is reduced by ~20mA.
DS11758 Rev 6 27/139

27
4.8 I/O pad specification

The following table describes the different pad type configurations.
Table 10. I/O pad specification descriptions

Pad type Description
Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Provides transition fast enough for the serial communication channels with controlled
Medium configuration
current to reduce electromagnetic emission.
Strong configuration Provides fast transition speed; used for fast interface.
Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Very strong
Used for fast interface including Ethernet and FlexRay interfaces requiring fine control of
configuration
rising/falling edge jitter.
Differential A few pads provide differential capability providing very fast interface together with good
configuration EMC performances.
Input only pads These low input leakage pads are associated with the ADC channels.
Some pads are active during Standby. Low Power Pads input buffer can only be
configured in TTL mode. When the pads are in Standby mode, the Pad-Keeper feature is
Standby pads
activated: if the pad status is high, the weak pull-up resistor is automatically enabled; if
the pad status is low, the weak pull-down resistor is automatically enabled.
Note: Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for
each IO segment.
Logic level is configurable in running mode while it is TTL not-configurable in STANDBY for
LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be
configured as TTL also in running mode in order to prevent device wrong behavior in
STANDBY.
4.8.1 I/O input DC characteristics

The following table provides input DC electrical characteristics, as described in Figure 3.
28/139 DS11758 Rev 6

Figure 3. I/O input electrical characteristics
VIN
VDD
VIH
VHYS
VIL
VINTERNAL
(SIUL register)
Table 11. I/O input electrical characteristics

Value
Min Typ Max
TTL
Input high level VDD_HV_IO

Vihttl SR P — 2 — V
TTL + 0.3
Input low level
Vilttl SR P — –0.3 — 0.8 V
TTL
Input hysteresis
Vhysttl CC C — 0.3 — — V
TTL
CMOS
Input high level VDD_HV_IO

Vihcmos SR P — 0.65 * VDD — V
CMOS + 0.3
Input low level
Vilcmos SR P — –0.3 — 0.35 * VDD V
CMOS
Input hysteresis
Vhyscmos CC C — 0.10 * VDD — — V
CMOS
COMMON
Pad input INPUT-ONLY pads

ILKG CC P — — 200 nA
leakage TJ = 150 °C
Pad input MEDIUM pads
ILKG CC P — — 360 nA
Pad input STRONG pads
ILKG CC P — — 1,000 nA
DS11758 Rev 6 29/139

38
Table 11. I/O input electrical characteristics (continued)

Value
Min Typ Max
Pad input VERY STRONG pads,

ILKG CC P — — 1,000 nA
Pad
CP1 CC D — — — 10 pF
capacitance
Input Vil/Vih In a 1 ms period, with a
Vdrift CC D temperature temperature variation — — 100 mV
drift <30 °C
Wakeup input
WFI SR C — — — 20 ns
filtered pulse(1)
Wakeup input
WNFI SR C not filtered — 400 — — ns
pulse(1)
1. In the range from WFI (max) to WNFI (min), pulses can be filtered or not filtered, according to operating temperature and
voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature.
Table 12. I/O pull-up/pull-down electrical characteristics

Value
Min Typ Max
T Weak pull-up VIN = 1.1 V(1) — — 130

IWPU CC current VIN = 0.69 * μA
P absolute value 15 — —
VDD_HV_IO(2)
Weak Pull-up VDD_HV_IO = 5.0 V ±
RWPU CC D 33 — 93 KΩ
resistance 10%
Weak Pull-up VDD_HV_IO = 3.3 V ±
RWPU CC D 19 — 62 KΩ
resistance 10%
VIN = 0.69 *
T — — 130 μA
Weak pull- VDD_HV_IO(1)
IWPD CC down current
absolute value VIN = 0.9 V(2)
P 15 — —
Weak Pull-
VDD_HV_IO = 5.0 V ±
RWPD CC D down 29 — 60 KΩ
10%
resistance
Weak Pull-
VDD_HV_IO = 3.3 V ±
RWPD CC D down 19 — 60 KΩ
10%
resistance
1. Maximum current when forcing a change in the pin level opposite to the pull configuration.
2. Minimum current when keeping the same pin level state than the pull configuration.
Note: When the device enters into standby mode, the LP pads have the input buffer switched-on.
As a consequence, if the pad input voltage VIN is VSS<VIN<VDD_HV, an additional
consumption can be measured in the VDD_HV domain. The highest consumption can be
30/139 DS11758 Rev 6

seen around mid-range (VIN ~=VDD_HV/2), 2-3mA depending on process, voltage and
temperature.
This situation may occur if the PAD is used as a ADC input channel, and VSS<VIN<VDD_HV.
The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid
the extra consumption. Please refer to the device pinout IO definition excel file to identify the
low-power pads which also have an ADC function.
4.8.2 I/O output DC characteristics

Figure 4 provides description of output DC electrical characteristics.
Figure 4. I/O output DC electrical characteristics definition
VINTERNAL
(SIUL register)
VHYS
Vout tSKEW20-80
90%
80%
20%
10%
tR20-80
tF20-80
tR10-90
tF10-90
tTR(max) = MAX(tR10-90; tF10-90) tTR20-80(max) = MAX(tR20-80; tF20-80)

tTR(min) = MIN(tR10-90; tF10-90) tTR20-80(min) = MIN(tR20-80; tF20-80)
tSKEW20-80 = |tR20-80-tF20-80|
tSKEW10-90 = |tR10-90-tF10-90|
The following tables provide DC characteristics for bidirectional pads:

• Table 13 provides output driver characteristics for I/O pads when in WEAK/SLOW
configuration.
• Table 14 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
• Table 15 provides output driver characteristics for I/O pads when in STRONG/FAST
configuration.
• Table 16 provides output driver characteristics for I/O pads when in VERY
STRONG/VERY FAST configuration.
Note: 10%/90% is the default condition for any parameter if not explicitly mentioned differently.
DS11758 Rev 6 31/139

38
Table 13. WEAK/SLOW I/O output characteristics

Value
Min Typ Max
Output low Iol = 0.5 mA

Vol_W CC D voltage for Weak VDD = 5.0 V ± 10% — — 0.1*VDD V
type PADs VDD = 3.3 V ± 10%
Output high Ioh = 0.5 mA
Voh_W CC D voltage for Weak VDD = 5.0 V ± 10% 0.9*VDD — — V
type PADs VDD = 3.3 V ± 10%
Output VDD = 5.0 V ± 10% 380 — 1040
R_W CC P impedance for Ω
Weak type PADs VDD = 3.3 V ± 10% 250 — 700
CL = 25 pF
VDD = 5.0 V ± 10% — — 2 MHz
Maximum output V = 3.3 V ± 10%
DD
Fmax_W CC T frequency for
Weak type PADs CL = 50 pF
VDD = 5.0 V ± 10% — — 1 MHz
VDD = 3.3 V ± 10 %
CL = 25 pF
Transition time VDD = 5.0 V + 10% 25 — 120 ns
output pin VDD = 3.3 V + 10%
tTR_W CC T weak
configuration, CL = 50 pF
10%-90% VDD = 5.0 V ± 10 % 50 — 240 ns
VDD = 3.3 V ± 10 %
Difference
between rise
|tSKEW_W| CC T — — — 25 %
and fall time,
90%-10%
Maximum DC VDD = 5.0 V ± 10%
IDCMAX_W CC D — — 0.5 mA
current VDD = 3.3 V ± 10%
Table 14. MEDIUM I/O output characteristics

Value
Min Typ Max

voltage for VDD =5.0 V ± 10 %
Vol_M CC D — — 0.1*VDD V
Medium type
VDD =3.3 V ± 10 %
PADs
Output high Ioh=2.0 mA
voltage for VDD = 5.0 V ± 10%
Voh_M CC D 0.9*VDD — — V
Medium type
VDD = 3.3 V ± 10%
PADs
32/139 DS11758 Rev 6

Table 14. MEDIUM I/O output characteristics (continued)

Value
Min Typ Max
Output VDD = 5.0 V ± 10% 90 — 260

impedance for
R_M CC P Ω
Medium type VDD = 3.3 V ± 10% 60 — 170
PADs
CL = 25 pF
VDD = 5.0 V ± 10% — — 12 MHz
Maximum output
frequency for VDD = 3.3 V ± 10%
Fmax_M CC T
Medium type CL = 50 pF
PADs
VDD = 5.0 V ± 10 % — — 6 MHz
VDD = 3.3 V ± 10 %
CL = 25 pF
Transition time VDD = 5.0 V ± 10% 8 — 30 ns
output pin VDD = 3.3 V ± 10%
tTR_M CC T MEDIUM
10%-90% VDD = 5.0 V ± 10% 12 — 60 ns
VDD = 3.3 V ± 10%
Difference
between rise
|tSKEW_M| CC T — — — 25 %
and fall time,
90%-10%
Maximum DC VDD = 5.0 V ± 10%
IDCMAX_M CC D — — 2 mA
Table 15. STRONG/FAST I/O output characteristics

Value
Min Typ Max

— — 0.1*VDD V
Vol_S CC D
Strong type Iol = 5.5 mA
PADs — — 0.15*VDD V
VDD =3 .3 V ± 10%

0.9*VDD — — V
Voh_S CC D
Strong type Ioh = 5.5 mA
PADs 0.85*VDD — — V
VDD = 3.3 V ± 10%
Output VDD = 5.0 V ± 10% 20 — 65
impedance for
R_S CC P Ω
Strong type VDD = 3.3 V ± 10% 28 — 90
PADs
DS11758 Rev 6 33/139

38
Table 15. STRONG/FAST I/O output characteristics (continued)

Value
Min Typ Max
CL = 25 pF
— — 50 MHz
VDD=5.0 V ± 10%
CL = 50 pF
Maximum output — — 25 MHz
frequency for VDD=5.0 V ± 10%
Fmax_S CC T
Strong type CL = 25 pF
PADs — — 25 MHz
VDD = 3.3 V ± 10%
CL = 50 pF
— — 12.5 MHz
VDD = 3.3 V ± 10%
CL = 25 pF ns
3 — 10
VDD = 5.0 V ± 10%
Transition time CL = 50 pF
output pin 5 — 16
VDD = 5.0 V ± 10%
tTR_S CC T STRONG
1.5 — 15
10%-90% VDD = 3.3 V ± 10%
CL = 50 pF
2.5 — 26
VDD = 3.3 V ± 10%
Maximum DC VDD = 5 V ± 10% — — 8 mA

IDCMAX_S CC D
current VDD = 3.3 V ± 10% — — 5.5
Difference %
between rise
|tSKEW_S| CC T — — — 25
and fall time,
90%-10%
Table 16. VERY STRONG/VERY FAST I/O output characteristics

Value
Min Typ Max

— — 0.1*VDD V
voltage for Very VDD =5.0 V ± 10%
Vol_V CC D
Strong type Iol = 9.0 mA
PADs — — 0.15*VDD V
VDD =3.3 V ± 10%

0.9*VDD — — V
voltage for Very VDD = 5.0 V ± 10%
Voh_V CC D
Strong type Ioh = 9.0 mA
PADs 0.85*VDD — — V
VDD = 3.3 V ± 10%
Output VDD = 5.0 V ± 10% 20 — 60
impedance for
R_V CC P Ω
Very Strong type VDD = 3.3 V ± 10% 18 — 50
PADs
34/139 DS11758 Rev 6

Table 16. VERY STRONG/VERY FAST I/O output characteristics (continued)

Value
Min Typ Max
CL = 25 pF
— — 50 MHz
VDD = 5.0 V ± 10%
CL = 50 pF
Maximum output — — 25 MHz
frequency for VDD = 5.0 V ± 10%
Fmax_V CC T
Very Strong type CL = 25 pF
PADs — — 50 MHz
VDD = 3.3 V ± 10%
CL = 50 pF
— — 25 MHz
VDD = 3.3 V ± 10%
CL = 25 pF
1 — 6
VDD = 5.0 V ± 10%
10–90%
CL = 50 pF
threshold 3 — 12
transition time VDD = 5.0 V ± 10%
tTR_V CC T ns
output pin VERY CL = 25 pF
STRONG 1.5 — 6
VDD = 3.3 V ± 10%
configuration
CL = 50 pF
3 — 11
VDD = 3.3 V ± 10%
20–80% CL = 25 pF
0.8 — 4.5
threshold VDD = 5.0 V ± 10%
transition time
output pin VERY
tTR20-80_V CC T ns
STRONG CL = 15 pF
configuration 1 — 4.5
VDD = 3.3 V ± 10%
(Flexray
Standard)
TTL threshold
transition time
for output pin in CL = 25 pF
tTRTTL_V CC T VERY STRONG 0.88 — 5 ns
VDD = 3.3 V ± 10%
configuration
(Ethernet
standard)
Sum of CL = 25 pF
— — 9
transition time VDD = 5.0 V ± 10%
20–80% output
ΣtTR20-80_V CC T ns
pin VERY CL = 15 pF
STRONG — — 9
VDD = 3.3 V ± 10%
configuration
Difference CL = 25 pF
|tSKEW_V| CC T between rise 0 — 1.2 ns
VDD = 5.0 V ± 10%
and fall delay
Maximum DC VDD = 5.0 V±10%

IDCMAX_V CC D — — 9 mA
DS11758 Rev 6 35/139

38
4.8.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in the device pinout Microsoft Excel file
attached to the IO_Definition document.
Table 17 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IRMSSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O
on a single segment should remain below the IDYNSEG maximum value.
Pad mapping on each segment can be optimized using the pad usage information provided
on the I/O Signal Description table.
Table 17. I/O consumption

Value(1)
Min Typ Max
Average consumption(2)
Sum of all the DC I/O current

IRMSSEG SR D — — — 80 mA
within a supply segment
CL = 25 pF, 2 MHz,
— — 1.1
VDD = 5.0 V ± 10 %
CL = 50 pF, 1 MHz,
— — 1.1
RMS I/O current for WEAK VDD = 5.0 V ± 10 %
IRMS_W CC D mA
configuration CL = 25 pF, 2 MHz,
— — 1.0
VDD = 3.3 V ± 10 %
CL = 25 pF, 1 MHz,
— — 1.0
VDD = 3.3 V ± 10%
CL = 25 pF, 12 MHz,
— — 5.5
VDD = 5.0 V ± 10%
CL = 50 pF, 6 MHz,
— — 5.5
RMS I/O current for MEDIUM VDD = 5.0 V ± 10%
IRMS_M CC D mA
— — 4.2
VDD = 3.3 V ± 10%
CL = 25 pF, 6 MHz,
— — 4.2
VDD = 3.3 V ± 10%
CL = 25 pF, 50 MHz,
— — 21
VDD = 5.0 V ± 10%
CL = 50 pF, 25 MHz,
— — 21
RMS I/O current for STRONG VDD = 5.0 V ± 10%
IRMS_S CC D mA
— — 10
VDD = 3.3 V ± 10%
CL = 25 pF, 12.5 MHz,
— — 10
VDD = 3.3 V ± 10%
36/139 DS11758 Rev 6

Table 17. I/O consumption (continued)

Value(1)
Min Typ Max
CL = 25 pF, 50 MHz,
— — 23
VDD = 5.0 V ± 10%
CL = 50 pF, 25 MHz,
— — 23
RMS I/O current for VERY VDD = 5.0 V ± 10%
IRMS_V CC D mA
STRONG configuration CL = 25 pF, 50 MHz,
— — 16
VDD = 3.3 V ± 10%
CL = 25 pF, 25 MHz,
— — 16
VDD = 3.3 V ± 10%
Dynamic consumption(3)
Sum of all the dynamic and DC VDD = 5.0 V ± 10% — — 195

IDYN_SEG SR D I/O current within a supply mA
segment VDD = 3.3 V ± 10% — — 150
CL = 25 pF, VDD = 5.0 V ±

— — 16.7
10%
CL = 50 pF, VDD = 5.0 V ±
— — 16.8
Dynamic I/O current for WEAK 10%
IDYN_W CC D mA
configuration CL = 25 pF, VDD = 3.3 V ±
— — 12.9
10%
CL = 50 pF, VDD = 3.3 V ±
— — 12.9
10%
CL = 25 pF, VDD = 5.0 V ±
— — 18.2
10%
CL = 50 pF, VDD = 5.0 V ±
— — 18.4
Dynamic I/O current for 10%
IDYN_M CC D mA
MEDIUM configuration CL = 25 pF, VDD = 3.3 V ±
— — 14.3
10%
CL = 50 pF, VDD = 3.3 V ±
— — 16.4
10%
CL = 25 pF, VDD = 5.0 V ±
— — 57
10%
CL = 50 pF, VDD = 5.0 V ±
— — 63.5
Dynamic I/O current for 10%
IDYN_S CC D mA
STRONG configuration CL = 25 pF, VDD = 3.3 V ±
— — 31
10%
CL = 50 pF, VDD = 3.3 V ±
— — 33.5
10%
DS11758 Rev 6 37/139

38
Table 17. I/O consumption (continued)

Value(1)
Min Typ Max
CL = 25 pF, VDD = 5.0 V ±

— — 62
10%
CL = 50 pF, VDD = 5.0 V ±
— — 70
Dynamic I/O current for VERY 10%
IDYN_V CC D mA
STRONG configuration CL = 25 pF, VDD = 3.3 V ±
— — 52
10%
CL = 50 pF, VDD = 3.3 V ±
— — 55
10%
1. I/O current consumption specifications for the 4.5 V ≤ VDD_HV_IO ≤ 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and
VSIO[VSIO_xx] = 0 for 3.0 V ≤ VDD_HV_IO ≤ 3.6 V.
2. Average consumption in one pad toggling cycle.
3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed
output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.
38/139 DS11758 Rev 6

4.9 Reset pad (PORST, ESR0) electrical characteristics

The device implements dedicated bidirectional reset pins as below specified. PORST pin
does not require active control. It is possible to implement an external pull-up to ensure
correct reset exit sequence. Recommended value is 4.7 KΩ.
Figure 5. Startup Reset requirements
VDD
VDD_POR
PORST
VIH
VIL
device start-up phase

PORST undriven device reset
PORST driven low by
device reset by internal power-on reset forced by external circuitry
internal power-on reset
Figure 6 describes device behavior depending on supply signal on PORST:

1. PORST low pulse has too low amplitude: it is filtered by input buffer hysteresis. Device
remains in current state.
2. PORST low pulse has too short duration: it is filtered by low pass filter. Device remains
in current state.
3. PORST low pulse is generating a reset:
a) PORST low but initially filtered during at least WFRST. Device remains initially in
current state.
b) PORST potentially filtered until WNFRST. Device state is unknown. It may either
be reset or remains in current state depending on extra condition (temperature,
voltage, device).
c) PORST asserted for longer than WNFRST. Device is under reset.
DS11758 Rev 6 39/139

41
Figure 6. Noise filtering on reset signal
VPORST, VESR0
VDD
VIH
VHYS
VIL
internal
reset
filtered by
filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset
WFRST WFRST
WNFRST
1 2 3a 3b 3c
Table 18. Reset PAD electrical characteristics

Value
Min Typ Max
VIHRES SR P Input high level VDD_HV = 5.0 V ± 10% 2 — VDD_HV_IO V

TTL VDD_HV = 3.3 V ± 10% +0.3
VILRES SR P Input low level VDD_HV = 5.0 V ± 10% -0.3 — 0.8 V

TTL
VDD_HV = 3.3 V ± 10% -0.3 — 0.6
VHYSRES CC C Input hysteresis VDD_HV = 5.0 V ± 10% 0.3 — — V
TTL
VDD_HV = 3.3 V ± 10% 0.2 — —
VDD_POR CC D Minimum supply VDD_HV = 5.0 V ± 10% — — 1.6 V
for strong pull-
VDD_HV = 3.3 V ± 10% — — 1.05
down activation
40/139 DS11758 Rev 6

Table 18. Reset PAD electrical characteristics (continued)

Value
Min Typ Max
IOL_R CC P Strong pull-down VDD_HV = 5.0 V ± 10% 12 — — mA

current (1)
VDD_HV = 3.3 V ± 10% 8 — —
(2) μA
IWPU CC P Weak pull-up VIN = 1.1 V — — 130
current absolute VDD_HV = 5.0 V ± 10%
value
P VIN = 1.1 V — — 70
VDD_HV = 3.3 V ± 10%
P VIN = 0.69 * 15 — —
VDD_HV_IO(3)
VDD_HV = 5.0 V ± 10%
P VIN = 0.69 * VDD_HV_IO 15 — —
VDD_HV = 3.3 V ± 10%
IWPD CC P Weak pull-down VIN = 0.69 * — — 130 μA
current absolute VDD_HV_IO(2)
value VDD_HV = 5.0 V ± 10%
P VIN = 0.69 * — — 80
VDD_HV_IO(2)
VDD_HV = 3.3 V ± 10%
P VIN = 0.9 V 15 — —
VDD_HV = 5.0 V ± 10%
P VIN = 0.9 V 15 — —
VDD_HVDD_HV = 3.3 V
± 10%
WFRST CC P Input filtered VDD_HV = 5.0 V ± 10% — — 500 ns
pulse
P VDD_HV = 3.3 V ± 10% — — 600
WNFRST CC P Input not filtered VDD_HV = 5.0 V ± 10% 2000 — — ns
pulse
P VDD_HV = 3.3 V ± 10% 3000 — —
1. Iol_r applies to PORST: Strong Pull-down is active on PHASE0 for PORST. A dedicated Reset Pad for ESR0, with the
specifications reported in this table, is implemented. Refer to the device pinout IO definition excel file for details regarding
pin usage.
2. Maximum current when forcing a change in the pin level opposite to the pull configuration.
3. Minimum current when keeping the same pin level state than the pull configuration.
Table 19. Reset Pad state during power-up and reset

PAD POWER-UP State RESET state DEFAULT state(1) STANDBY state
PORST Strong pull-down Weak pull-down Weak pull-down Weak pull-up

ESR0 Strong pull-down Strong pull-down Weak pull-up Weak pull-up
1. Before SW Configuration. Please refer to the Device Reference Manual, Reset Generation Module (MC_RGM) Functional
Description chapter for the details of the power-up phases.
DS11758 Rev 6 41/139

41
4.10 PLLs
Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary
clocks on the device.
Figure 7 depicts the integration of the two PLLs. Please, refer to device Reference Manual
for more detailed schematic.
Figure 7. PLLs integration
IRCOSC PLL0_PHI
PLL0 PLL0_PHI1
XOSC
PLL1_PHI
PLL1
4.10.1 PLL0
Table 20. PLL0 electrical characteristics
Value
Min Typ Max
fPLL0IN SR — PLL0 input clock(1) — 8 — 44 MHz

PLL0 input clock duty
ΔPLL0IN SR — — 40 — 60 %
cycle(1)
PLL0 PFD (Phase
fINFIN SR — Frequency Detector) input — 8 — 20 MHz
clock frequency
fPLL0VCO CC P PLL0 VCO frequency — 600 — 1400 MHz
fPLL0PHI0 CC D PLL0 output frequency — 4.762 — 400 MHz
fPLL0PHI1 CC D PLL0 output clock PHI1 — 20 — 175(2) MHz
tPLL0LOCK CC P PLL0 lock time — — — 100 µs
PLL0_PHI0 single period
jitter fPLL0PHI0 = 400 MHz,
|ΔPLL0PHI0SPJ |(3) CC T — — 200 ps
fPLL0IN = 20 MHz 6-sigma pk-pk
(resonator)
42/139 DS11758 Rev 6

Table 20. PLL0 electrical characteristics (continued)

Value
Min Typ Max
PLL0_PHI1 single period

(3) jitter fPLL0PHI1 = 40 MHz,
|ΔPLL0PHI1SPJ| CC D — — 300(4) ps
fPLL0IN = 20 MHz 6-sigma pk-pk
(resonator)
10 periods
accumulated jitter
(80 MHz equivalent — — ±250 ps
frequency), 6-sigma
pk-pk
PLL0 output long term
16 periods
jitter(4)
(3) accumulated jitter
ΔPLL0LTJ CC D fPLL0IN = 20 MHz (50 MHz equivalent — — ±300 ps
(resonator), VCO frequency), 6-sigma
frequency = 800 MHz pk-pk
long term jitter
(< 1 MHz equivalent
— — ±500 ps
frequency), 6-sigma
pk-pk)
IPLL0 CC D PLL0 consumption FINE LOCK state — — 6 mA
1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted
when using internal RCOSC or external oscillator is used in functional mode.
2. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency
limit set for PLL1 (87.5 MHz, according to Table 21).
3. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to
the output CLKOUT pin.
4. VDD_LV noise due to application in the range VDD_LV = 1.20 V±5%, with frequency below PLL bandwidth (40 kHz) will be
filtered.
DS11758 Rev 6 43/139

44
4.10.2 PLL1
PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG)
support.
Table 21. PLL1 electrical characteristics

Value
Min Typ Max
fPLL1IN SR — PLL1 input clock(1) — 37.5 — 87.5 MHz

PLL1 input clock duty
ΔPLL1IN SR — — 35 — 65 %
cycle(1)
PLL1 PFD (Phase
fINFIN SR — Frequency Detector) — 37.5 87.5 MHz
input clock frequency
fPLL1VCO CC P PLL1 VCO frequency — 600 — 1400 MHz
fPLL1PHI0 CC D PLL1 output clock PHI0 — 4.762 — FSYS(2) MHz
tPLL1LOCK CC P PLL1 lock time — — — 50 µs
PLL1 modulation
fPLL1MOD CC T — — — 250 kHz
frequency
PLL1 modulation depth Center spread(3) 0.25 — 2 %

|δPLL1MOD| CC T
(when enabled) Down spread 0.5 — 4 %
|ΔPLL1PHI0SPJ| PLL1_PHI0 single period fPLL1PHI0 =
(4) CC T — — 500(5) ps
peak to peak jitter 200 MHz, 6-sigma
IPLL1 CC D PLL1 consumption FINE LOCK state — — 5 mA
1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when
using internal PPL0 or external oscillator is used in functional mode.
2. Please refer to Section 4.3: Operating conditions for the maximum operating frequency.
3. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected,
the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD%).
Please refer to the Reference Manual for the PLL programming details.
4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to
the output CLKOUT pin.
5. 1.25 V±5%, application noise below 40 kHz at VDD_LV pin - no frequency modulation.
44/139 DS11758 Rev 6

4.11 Oscillators
4.11.1 Crystal oscillator 40 MHz
Table 22. External 40 MHz oscillator electrical specifications

Value
Min Max
fXTAL CC D Crystal Frequency — 4(2) 8 MHz

Range(1)
>8 20
>20 40
(3),(4)
tcst CC T Crystal start-up time TJ = 150 °C — 5 ms
trec CC D Crystal recovery time(5) — — 0.5 ms
VIHEXT CC D EXTAL input high VREF = 0.29 * VDD_HV_IO_JTAG VREF + — V
voltage(6) (External 0.75
Reference)
VILEXT CC D EXTAL input low VREF = 0.29 * VDD_HV_IO_JTAG — VREF - V
voltage(6) (External 0.75
Reference)
CS_EXTAL CC D Total on-chip stray — 3 7 pF
capacitance on EXTAL
pin(7)
CS_XTAL CC D Total on-chip stray — 3 7 pF
capacitance on XTAL
pin(7)
gm CC P Oscillator fXTAL = 4 − 8 MHz 3.9 13.6 mA/V
Transconductance freq_sel[2:0] = 000
D fXTAL = 5 - 10 MHz 5 17.5
freq_sel[2:0] = 001
D fXTAL = 10 − 15 MHz 8.6 29.3
freq_sel[2:0] = 010
P fXTAL = 15 - 20 MHz 14.4 48
freq_sel[2:0] = 011
D fXTAL = 20 - 25 MHz 21.2 69
freq_sel[2:0] = 100
D fXTAL = 25 − 30 MHz 27 86
freq_sel[2:0] = 101
D fXTAL = 30 - 35 MHz 33.5 115
freq_sel[2:0] = 110
P fXTAL = 35 - 40 MHz 33.5 115
freq_sel[2:0] = 111
VEXTAL CC D Oscillation Amplitude on TJ = –40 °C to 150 °C 0.5 1.8 V
the EXTAL pin after
startup(8)
DS11758 Rev 6 45/139

48
Table 22. External 40 MHz oscillator electrical specifications (continued)

Value
Min Max
VHYS CC D Comparator Hysteresis TJ = –40 °C to 150 °C 0.1 1.0 V

IXTAL (8),(9)
CC D XTAL current TJ = –40 °C to 150 °C — 14 mA
1. The range is selectable by UTEST miscellaneous DCF client XOSC_FREQ_SEL.
2. The XTAL frequency, if used to feed the PPL0 (or PLL1), shall obey the minimum input frequency limit set for PLL0 (or
PLL1).
3. This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum
provided.
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
6. Applies to an external clock input and not to crystal mode.
7. See crystal manufacturer’s specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL)
and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB
capacitance.
8. Amplitude on the EXTAL pin after startup is determined by the ALC block, that is the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.
9. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum
current during startup of the oscillator.
4.11.2 Crystal Oscillator 32 kHz
Table 23. 32 kHz External Slow Oscillator electrical specifications

Value
Min Typ Max
fsxosc SR T Slow external — — 32768 — Hz

crystal oscillator
frequency
gmsxosc CC P Slow external — 9.5 — 32 µA/V
crystal oscillator
transconductance
Vsxosc CC T Oscillation — 0.5 — 1.7 V
Amplitude
Isxoosc CC D Oscillator — — — 9 µA
consumption
Tsxosc CC T Start up time — — — 2 s
46/139 DS11758 Rev 6

4.11.3 RC oscillator 16 MHz

Table 24. Internal RC oscillator electrical specifications
Value
Min Typ Max
fTarget CC D IRC target frequency — — 16 — MHz

δfvar_noT CC P IRC frequency variation T < 150 °C –5 — 5 %
without temperature
compensation
δfvar_T CC T IRC frequency variation T < 150 °C –3 — 3 %
with temperature
compensation
δfvar_SW T IRC software trimming Trimming –0.5 +0.3 0.5 %
accuracy temperature
Tstart_noT CC T Startup time to reach within Factory — — 5 µs
fvar_noT trimming
already
applied
Tstart_T CC T Startup time to reach within Factory — — 120 µs
fvar_T trimming
already
applied
IFIRC CC T Current consumption on HV After Tstart_T — — 1200 µA
power supply(1)
1. The consumption reported considers the sum of the RC oscillator 16 MHz IP, and the core logic clocked by the IP during
Standby mode.
DS11758 Rev 6 47/139

48
4.11.4 Low power RC oscillator
Table 25. 1024 kHz internal RC oscillator electrical characteristics

Value
Min Typ Max
Fsirc CC T Slow Internal — — 1024 — kHz

RC oscillator
frequency
δfvar_T CC P Frequency –40 °C < T < –9 — +9 %
variation across 150 °C
temperature
δfvar_V CC P Frequency –40 °C < T < –5 — +5 %
variation across 150 °C
voltage
Isirc CC T Slow Internal T = 55 °C — — 6 µA
RC oscillator
current
Tsirc CC T Start up time, — — — 12 µS
after switching
ON the internal
regulator.
48/139 DS11758 Rev 6

4.12 ADC system
4.12.1 ADC input description

Figure 8 shows the input equivalent circuit for SARn and SARB channels.
Figure 8. Input equivalent circuit (Fast SARn and SARB channels)

INTERNAL CIRCUIT SCHEME
VDD
Channel
Sampling
Selection
RSW1 RAD
CEXT CP1 CP2 CS
VSS_HV_ADR
RCMSW Common mode
RSW1: Channel Selection Switch Impedance switch
RAD: Sampling Switch Impedance

CP: Pin Capacitance (two contributions, CP1 and CP2) RCMRL Common mode
resistive ladder
CS: Sampling Capacitance
RCMSW: Common mode switch VCM
RCMRL: Common mode resistive ladder
VCM: Common mode voltage (~0.5 VDD)
CEXT: External capacitance
The above scheme can be used as approximation circuitry for external filtering definition.
All specifications in the following table valid for the full input voltage range for the analog
inputs.
Table 26. ADC pin specification

Value
Min Max
Internal voltage reference source

R20KΩ CC D — 16 30 KΩ
impedance.
Input leakage current, two ADC See IO chapter Table 11: I/O input electrical
ILKG CC —
channels on input-only pin. characteristics, parameter ILKG.
Injection current on analog input
See Operating Conditions chapter Table 5:
IINJ1,2 SR — preserving functionality at full or
Operating conditions, IINJ1 and IINJ2 parameter.
degraded performances.
See Power Management chapter Table 34: External
CHV_ADC SR D VDD_HV_ADV external capacitance.
components integration, CADC parameter.
See IO chapter Table 11: I/O input electrical
CP1 CC D Pad capacitance
characteristics, parameter CP1.
DS11758 Rev 6 49/139

57
Table 26. ADC pin specification (continued)

Value
Min Max
SARB channels — 2
CP2 CC D Internal routing capacitance SARn 10bit channels — 0.5 pF
SARn 12bit channels — 1
SARn 12bit — 5
CS CC D SAR ADC sampling capacitance pF
SARn 10bit — 2
SARB channels 0 1.8
RSWn CC D Analog switches resistance SARn 10bit channels 0 0.8 kΩ
SARn 12bit channels 0 1.8
ADC input analog switches SARn 12bit — 0.8

RAD CC D kΩ
resistance SARn 10bit — 3.2
RCMSW CC D Common mode switch resistance Sum of the two kΩ
— 9
RCMRL CC D Common mode resistive ladder resistances kΩ
Discharge resistance for ADC VDD_HV_IO = 5.0 V ± 10% — 300 W
RSAFEPD(1) CC D input-only pins (strong pull-down
for safety) VDD_HV_IO = 3.3 V ± 10% — 500 W
ABGAP CC D ADC digital bandgap accuracy -1.5 +1.5 %

To preserve the accuracy of the ADC, it is necessary
that analog input pins have low AC impedance.
Placing a capacitor with good high frequency
characteristics at the input pin of the device can be
External capacitance at the pad
CEXT SR — effective: the capacitor should be as large as
input pin
possible. This capacitor contributes to attenuating
the noise present on the input pin. The impedance
relative to the signal source can limit the ADC’s
sample rate.
1. It enables discharge of up to 100 nF from 5 V every 300 ms. Refer to the device pinout Microsoft Excel file attached to the
IO_Definition document for the pads supporting it.
4.12.2 SAR ADC 12 bit electrical specification

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters
with full capacitive DAC. The SARn architecture allows input channel multiplexing.
Note: The functional operating conditions are given in the DC electrical specifications. Absolute
maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the listed maximum may affect device reliability or cause
50/139 DS11758 Rev 6

Table 27. SARn ADC electrical specification

Value
Min Max
P Standard frequency mode 7.5 13.33

fADCK SR Clock frequency MHz
T High frequency mode >13.33 16.0
tADCINIT SR — ADC initialization time — 1.5 — µs
ADC BIAS
tADCBIASINIT SR — — 5 — µs
initialization time
Fast SAR 1/fADCK —
tADCPRECH SR T ADC decharge time µs
Slow SAR (SARDAC_B) 2/fADCK —
Decharge voltage
ΔVPRECH SR D TJ < 150 °C 0 0.25 V
precision
Internal voltage
R20KΩ CC D reference source — 16 30 KΩ
impedance
Applies to all internal
reference points
Internal reference (VSS_HV_ADR,
ΔVINTREF CC P −0.20 0.20 V
voltage precision 1/3 * VDD_HV_ADR,
2/3 * VDD_HV_ADR,
VDD_HV_ADR)
DS11758 Rev 6 51/139

57
Table 27. SARn ADC electrical specification (continued)

Value
Min Max
Fast SAR – 12-bit

P 6/fADCK
configuration
Fast SAR – 10-bit
configuration mode 1(2)
6/fADCK
(Standard frequency mode
only)
Fast SAR – 10-bit
configuration mode 2(3)
5/fADCK
only)
Fast SAR – 10-bit
configuration mode 3(4) 6/fADCK
(High frequency mode only)
Slow SAR (SARADC_B) –
12/fADCK
12-bit configuration
tADCSAMPLE SR ADC sample time(1) Slow SAR (SARADC_B) – — µs
D 10-bit configuration mode
1(2) 12/fADCK
only)
10-bit configuration mode
2(3) 10/fADCK
only)
10-bit configuration mode
12/fADCK
3(4)
(High frequency mode only)
Conversion of BIAS test
channels through 20 kΩ 40/fADCK
input.
P 12-bit configuration 12/fADCK —
tADCEVAL SR ADC evaluation time µs
D 10-bit configuration 10/fADCK —
Run mode
ADC high reference — 7
IADCREFH(5),(6) CC T (average across all codes) µA
current
Power Down mode — 1
Run mode
— 15
ADC low reference VDD_HV_ADR_S ≤ 5.5 V
IADCREFL (6)
CC D µA
current Power Down mode
— 1
VDD_HV_ADR_S ≤ 5.5 V
P VDD_HV_ADV power Run mode — 4.0
IADV_S(6) CC mA
D supply current Power Down mode — 0.04
52/139 DS11758 Rev 6


Value
Min Max
TJ < 150 °C,

T VDD_HV_ADV > 3 V, –4 4
VDD_HV_ADR_S > 3 V
TJ < 150 °C,
P VDD_HV_ADV > 3 V, –6 6
Total unadjusted error VDD_HV_ADR_S > 3 V
LSB
TUE12 CC in 12-bit TJ < 150 °C,
T configuration(7) V > 3 V, –6 6
(12b)
DD_HV_ADV
3 V > VDD_HV_ADR_S > 2 V
High frequency mode,
TJ < 150 °C,
D –12 12
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
Mode 1, TJ < 150 °C,
D VDD_HV_ADV > 3 V –1.5 1.5
VDD_HV_ADR_S > 3 V
Mode 1, TJ < 150 °C,
D VDD_HV_ADV > 3 V, –2.0 2.0
Total unadjusted error 3 V > V
DD_HV_ADR_S > 2 V LSB
TUE10 CC in 10-bit
configuration(7) Mode 2, TJ < 150 °C, (10b)
C VDD_HV_ADV > 3 V –3.0 3.0
VDD_HV_ADR_S > 3 V
Mode 3, TJ < 150 °C,
C VDD_HV_ADV > 3 V –4.0 4.0
VDD_HV_ADR_S > 3 V
DS11758 Rev 6 53/139

57

Value
Min Max
VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV –1 1
∈ [0:25 mV]
VIN < VDD_HV_ADV
∈ [25:50 mV]
VIN < VDD_HV_ADV
∈ [50:75 mV]
VIN < VDD_HV_ADV
∈ [75:100 mV]
TUE degradation due V
DD_HV_ADV < VIN <
to VDD_HV_ADR offset V LSB
ΔTUE12 CC D DD_HV_ADR
–2.5 2.5
with respect to (12b)
VDD_HV_ADR − VDD_HV_ADV
VDD_HV_ADV
∈ [0:25 mV]
VDD_HV_ADV < VIN <
VDD_HV_ADR
–4 4
∈ [25:50 mV]
VDD_HV_ADV < VIN <
VDD_HV_ADR
–7 7
∈ [50:75 mV]
VDD_HV_ADV < VIN <
VDD_HV_ADR
–12 12
∈ [75:100 mV]
Standard frequency mode,
P VDD_HV_ADV > 4 V –1 2
Differential non- VDD_HV_ADR_S > 4 V LSB
DNL(8) CC
linearity High frequency mode, (12b)
T VDD_HV_ADV > 4 V –1 2
VDD_HV_ADR_S > 4 V
1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing
and calculating the sampling window duration.
2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.
3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.
4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.
5. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven
by the transfer of charge between internal capacitances during the conversion.
6. Current parameter values are for a single ADC.
54/139 DS11758 Rev 6

7. TUE is granted with injection current within the range defined in Table 26, for parameters classified as T and D.
8. DNL is granted with injection current within the range defined in Table 26, for parameters classified as T and D.
4.12.3 SAR ADC 10 bit electrical specification

The ADC comparators are 10-bit Successive Approximation Register analog-to-digital
converters with full capacitive DAC. The SARn architecture allows input channel
multiplexing.
Note: The functional operating conditions are given in the DC electrical specifications. Absolute
maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the listed maximum may affect device reliability or cause
Table 28. ADC-Comparator electrical specification

Value
Min Max
P Standard frequency mode 7.5 13.33

fADCK SR Clock frequency MHz
T High frequency mode >13.33 16.0
tADCINIT SR — ADC initialization time — 1.5 — µs
ADC BIAS initialization
tADCBIASINIT SR — — 5 — µs
time
ADC initialization time
tADCINITSBY SR — Standby Mode 8 — µs
in standby
tADCPRECH SR T ADC precharge time — 1/fADCK — µs
Precharge voltage
ΔVPRECH SR D TJ < 150 °C 0 0.25 V
precision
10-bit ADC mode 5/fADCK — µs
tADCSAMPLE SR P ADC sample time(1)
ADC comparator mode 2/fADCK — µs
P 10-bit ADC mode 10/fADCK —
tADCEVAL SR ADC evaluation time µs
D ADC comparator mode 2/fADCK —
Run mode
— 7
(average across all codes)
ADC high reference
IADCREFH(2),(3) CC T µA
current Power Down mode — 1
ADC comparator mode — 19.5
Run mode
— 15
ADC low reference
IADCREFL(4) CC D Power Down mode µA
current — 1
ADC comparator mode — 20.5
P V Run mode — 4
IADV_S(4) CC DD_HV_ADV power mA
D supply current Power Down mode — 0.04
DS11758 Rev 6 55/139

57
Table 28. ADC-Comparator electrical specification (continued)

Value
Min Max
TJ < 150 °C,

VDD_HV_ADR_S > 3 V
TJ < 150 °C,
P VDD_HV_ADV > 3 V, –3 3
VDD_HV_ADR_S > 3 V
Total unadjusted error LSB
TUE10 CC
in 10-bit configuration(5) TJ < 150 °C, (10b)
3 V > VDD_HV_ADR_S > 2 V
High frequency mode,
TJ < 150 °C,
D –3 3
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
VIN < VDD_HV_ADV
VDD_HV_ADR − VDD_HV_ADV ∈ –1.0 1.0
[0:25 mV]
VIN < VDD_HV_ADV
[25:50 mV]
VIN < VDD_HV_ADV
[50:75 mV]
VIN < VDD_HV_ADV
[75:100 mV]
TUE degradation due VDD_HV_ADV < VIN <
to VDD_HV_ADR offset VDD_HV_ADR LSB
ΔTUE10 CC D –2.5 2.5
with respect to (10b)
VDD_HV_ADR − VDD_HV_ADV ∈
VDD_HV_ADV
[0:25 mV]
VDD_HV_ADV < VIN <
VDD_HV_ADR
–4.0 4.0
[25:50 mV]
VDD_HV_ADV < VIN <
VDD_HV_ADR
–7.0 7.0
[50:75 mV]
VDD_HV_ADV < VIN <
VDD_HV_ADR
–12.0 12.0
[75:100 mV]
56/139 DS11758 Rev 6

Table 28. ADC-Comparator electrical specification (continued)

Value
Min Max
Standard frequency mode,

P VDD_HV_ADV > 4 V –1 2
Differential non-linearity VDD_HV_ADR_S > 4 V LSB
DNL(6) CC
std. mode High frequency mode, (10b)
T VDD_HV_ADV > 4 V –1 2
VDD_HV_ADR_S > 4 V
1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing
and calculating the sampling window duration.
2. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven
by the transfer of charge between internal capacitances during the conversion.
3. Current parameter values are for a single ADC.
4. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC
and the channel subject to current injection.
5. TUE is granted with injection current within the range defined in Table 26, for parameters classified as T and D.
6. DNL is granted with injection current within the range defined in Table 26, for parameters classified as T and D.
DS11758 Rev 6 57/139

57
4.13 Temperature Sensor

The following table describes the temperature sensor electrical characteristics.
Table 29. Temperature sensor electrical characteristics

Value
Min Typ Max
— CC — Temperature monitoring range — –40 — 150 °C

TSENS CC T Sensitivity — — 5.18 — mV/°C
TACC CC P Accuracy TJ < 150 °C –3 — 3 °C
58/139 DS11758 Rev 6

4.14 LFAST pad electrical characteristics

The LFAST(LVDS Fast Asynchronous Serial Transmission) pad electrical characteristics
apply to high-speed debug serial interfaces on the device.
4.14.1 LFAST interface timing diagrams
Figure 9. LFAST and MSC/DSPI LVDS timing definition
Signal excursions above this level NOT allowed

1743 mV
Max. common mode input at RX

1600 mV
|ΔVOD|
Max Differential Voltage =
285 mV (LFAST)
400 mV (MSC/DSPI)
PAD_P
Minimum Data Bit Time
Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)
|ΔVOD|
Min Differential
Voltage =
100 mV (LFAST)
“No-Go” VOS = 1.2 V +/- 10%
(MSC/DSPI)
TX common mode
VICOM
PAD_N
ΔPEREYE ΔPEREYE
Data Bit Period
T = 1 /FDATA
Min. common mode input at RX

150 mV
0V
Signal excursions below this level NOT allowed
DS11758 Rev 6 59/139

64
Figure 10. Power-down exit time
lfast_pwr_down
tPD2NM_TX
Differential TX
Data Lines pad_p/pad_n Data Valid
Figure 11. Rise/fall time
VIH
Differential TX |ΔVOD(min)|
Data Lines
|ΔVOD(min)|
pad_p/pad_n VIL
tTR
tTR
4.14.2 LFAST and MSC/DSPILVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.
Table 30. LVDS pad startup and receiver electrical characteristics(1),(2)

Value
Min Typ Max
STARTUP(3),(4)
Bias current reference startup
tSTRT_BIAS CC T — — 0.5 4 μs
time(5)
Transmitter startup time (power
tPD2NM_TX CC T — — 0.4 2.75 μs
down to normal mode)(6)
60/139 DS11758 Rev 6

Table 30. LVDS pad startup and receiver electrical characteristics(1),(2) (continued)
Value
Min Typ Max
Transmitter startup time (sleep Not applicable to the

tSM2NM_TX CC T — 0.4 0.6 µs
mode to normal mode)(7) MSC/DSPI LVDS pad
Receiver startup time (power
tPD2NM_RX CC T — — 20 40 ns
down to normal mode)(8)
Receiver startup time (power Not applicable to the
tPD2SM_RX CC T — 20 50 ns
down to sleep mode)(9) MSC/DSPI LVDS pad
ILVDS_BIAS CC D LVDS bias current consumption Tx or Rx enabled — — 0.95 mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Transmission line characteristic
Z0 SR D — 47.5 50 52.5 Ω
impedance
Transmission line differential
ZDIFF SR D — 95 100 105 Ω
impedance
RECEIVER
0.15
VICOM SR T Common mode voltage — (10) — 1.6(11) V
|ΔVI| SR T Differential input voltage(12) — 100 — — mV

VHYS CC T Input hysteresis — 25 — — mV
RIN CC D Terminating resistance VDD_HV_IO = Ω
5.0 V ± 10% 80 — 150
-40 °C < TJ< 150 °C
VDD_HV_IO =
3.3 V ± 10% 80 — 175
-40 °C < TJ < 150 °C
CIN CC D Differential input capacitance(13) — — 3.5 6.0 pF
Receiver DC current
ILVDS_RX CC C Enabled — — 1.6 mA
consumption
Maximum consumption on ΔVI = 400 mV,
IPIN_RX CC D — — 5 mA
receiver input pin RIN = 80 Ω
1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug
(HSD) LVDS pad.
2. All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.
3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS
control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD
modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for
MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding
SIUL2 MSCR ODC field.
4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter
electrical characteristic tables.
5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being en-
abled.
6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock peri-
ods.
7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode.
DS11758 Rev 6 61/139

64
8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.
9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block re-
mains enabled in sleep mode.
10. Absolute min = 0.15 V – (285 mV/2) = 0 V
11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V
12. Value valid for LFAST mode. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure
proper LFAST receive timing.
13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.
Table 31. LFAST transmitter electrical characteristics(1),(2),(3)

Value
Min Typ Max
fDATA SR D Data rate — — — 320 Mbps

VOS CC P Common mode voltage — 1.08 — 1.32 V
Differential output voltage swing
|ΔVOD| CC P — 110 — 285 mV
(terminated)(4),(5)
Rise time from -|ΔVOD(min)| to
tTR CC T +|ΔVOD(min)|. Fall time from — 0.26 — 1.25 ns
+|ΔVOD(min)| to -|ΔVOD(min)|
External lumped differential load VDD_HV_IO = 4.5 V — — 6.0

CL SR D pF
capacitance(4) VDD_HV_IO = 3.0 V — — 4.0
ILVDS_TX CC C Transmitter DC current consumption Enabled — — 3.6 mA
Transmitter DC current sourced through
IPIN_TX CC D — 1.1 2.85 mA
output pin
1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101).
2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
values shown in Figure 12.
3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.
4. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 12.
5. Valid for maximum external load CL.
62/139 DS11758 Rev 6

Figure 12. LVDS pad external load diagram
Die Package PCB
GPIO Driver
1pF CL
2.5pF
100 Ω
LVDS Driver terminator
GPIO Driver
1pF CL
2.5pF
4.14.3 LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.
Table 32. LFAST PLL electrical characteristics(1)

Value
Min Typ Max
fRF_REF SR D PLL reference clock frequency (CLKIN) — 10(2) — 30 MHz

ERRREF CC D PLL reference clock frequency error — -1 — 1 %
DCREF CC D PLL reference clock duty cycle (CLKIN) — 30 — 70 %
Integrated phase noise (single side
PN CC D fRF_REF = 20 MHz — — -58 dBc
band)
fVCO CC P PLL VCO frequency — 312 — 320(3) MHz
tLOCK CC D PLL phase lock — — — 150(4) µs
DS11758 Rev 6 63/139

64
Table 32. LFAST PLL electrical characteristics(1) (continued)

Value
Min Typ Max
Single period,
T — — 350 ps
fRF_REF = 20 MHz
ΔPERREF SR Input reference clock jitter (peak to peak)
Long term,
T -500 — 500 ps
fRF_REF = 20 MHz
ΔPEREYE CC T Output Eye Jitter (peak to peak)(5) — — — 400 ps
1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.
3. The 320 MHz frequency is achieved with a 20 MHz reference clock.
4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device (to set the PLL enable bit).
5. Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board. See Figure 12.
64/139 DS11758 Rev 6

4.15 Power management

The power management module monitors the different power supplies as well as it
generates the required internal supplies. The device can operate in the following
configurations:
Table 33. Power management regulators

Internal Internal
Internal linear linear Internal
External Auxiliary Clamp
Device SMPS regulator regulator standby
regulator regulator regulator
regulator external internal regulator(1)
ballast ballast
SPC584Gx
SPC58EGx — — X — X X X(2)
SPC58NGx
1. Standby regulator is automatically activated when the device enters standby mode. Standby mode is not supported if the
device operates in External regulator mode. Emulation Device calibration and trace features are not supported in standby
mode.
2. Emulation Device calibration and trace features are not supported in standby mode.
4.15.1 Power management integration

Use the integration schemes provided below to ensure the proper device function,
according to the selected regulator configuration.
The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate
VDD_LV supply.
Place capacitances on the board as near as possible to the associated pins and limit the
serial inductance of the board to less than 5 nH.
It is recommended to use the internal regulators only to supply the device itself.
DS11758 Rev 6 65/139

73
Figure 13. Internal regulator with external ballast mode
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9''B+9 966
&%9
4(;7
&%
9''B+9B)/$
(;75(*B6(/
9''B+9B,2
%&75/
966
&( 9''B+9B,2
&+9Q
0DLQ5HJ
966
9''B/9
$X[5HJ
&/9Q
966
&ODPS5HJ
966B+9B$'9 9''B+9B$'9
&$'&
66/139 DS11758 Rev 6

Figure 14. Standby regulator with external ballast mode
&)/$
9''B+9 966
&%9
4(;7
9''B+9B)/$
(;75(*B6(/
%&75/
966
9''B+9B,2
&%
&( 9''B+9B,2
&+9Q
6WDQGE\UHJ
966
9''B/9
&/9Q
966
966B+9B$'9 9''B+9B$'9
&$'&
Table 34. External components integration

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max
Common Components
Internal voltage regulator stability

CE SR D — 2× 2.2 — µF
external capacitance.(2) (3)
Stability capacitor equivalent Total resistance including
RE SR D — — 50 mΩ
serial resistance board track
Internal voltage regulator
CLVn SR D decoupling external Each VDD_LV/VSS pair — 47 — nF
capacitance(2) (4) (5)
Stability capacitor equivalent
RLVn SR D — — — 50 mΩ
serial resistance
on one VDD_HV_IO_MAIN/
CBV SR D Bulk capacitance for HV supply(2) — 4.7 — µF
VSS pair
DS11758 Rev 6 67/139

73
Table 34. External components integration (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max
Decoupling capacitance for on all VDD_HV_IO/VSS and

CHVn SR D — 100 — nF
ballast and IOs(2) VDD_HV_ADR/VSS pairs
Decoupling capacitance for Flash
CFLA SR D — — 10 — nF
supply(6)
ADC supply external VDD_HV_ADV/VSS_HV_ADV
CADC SR D — 2.2 — µF
capacitance(2) pair.
Internal Linear Regulator with External Ballast Mode
Recommended external NPN

QEXT SR D NJD2873T4, BCP68, 2SCR574D
transistors
VDD_
External NPN transistor collector
VQ SR D — 2.0 — HV_IO V
voltage
_MAIN
Internal voltage regulator stability

CB SR D external capacitance on ballast — — 2.2 — µF
base(4) (7)
Stability capacitor equivalent Total resistance including
RB SR D — — 50 mΩ
serial resistance board track
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TJ = –40 / 150 °C, unless otherwise specified.
2. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging.
3. CE capacitance is required both in internal and external regulator mode.
4. For noise filtering, add a high frequency bypass capacitance of 10 nF.
5. For applications it is recommended to implement at least 5 CLV capacitances.
6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF.
7. CB capacitance is required if only the external ballast is implemented.
68/139 DS11758 Rev 6

4.15.2 Voltage regulators
Table 35. Linear regulator specifications

Value
Min Typ Max
Power-up, before
CC P 1.12 1.20 1.28
trimming, no load
VMREG Main regulator output voltage V
After trimming,
CC P 1.08 1.18 1.23
maximum load
Main regulator current provided to
VDD_LV domain
The maximum current required by

IDDMREG CC T the device (IDD_LV) may exceed — — — 700 mA
the maximum current which can
be provided by the internal linear
regulator. In this case, the internal
regulator mode cannot be used.
Main regulator rush current
sinked from VDD_HV_IO_MAIN
IDDCLAMP CC D Power-up condition — — 400 mA
domain during VDD_LV domain
loading
Main regulator output current 20 µs observation
ΔIDDMREG CC T -100 — 100 mA
variation window
D Main regulator current IMREG = max — — 22
IMREGINT CC mA
D consumption IMREG = 0 mA — — —
Table 36. Auxiliary regulator specifications

Value
Min Typ Max
After trimming, internal

CC P 1.08 1.18 1.21
regulator mode
VAUX Aux regulator output voltage V
After trimming, external
CC P 1.03 1.12 1.16
regulator mode
Aux regulator current provided to
IDDAUX CC T — — — 250 mA
VDD_LV domain
20 µs observation
ΔIDDAUX CC T Aux regulator current variation -100 — 100 mA
window
D Aux regulator current IMREG = max — — 1.1
IAUXINT CC mA
D consumption IMREG = 0 mA — — 1.1
DS11758 Rev 6 69/139

73
Table 37. Clamp regulator specifications

Value
Min Typ Max
After trimming, internal

CC P 1.17 1.21 1.32
regulator mode
VCLAMP Clamp regulator output voltage V
After trimming, external
CC P 1.24 1.28 1.39
regulator mode
20 µs observation
ΔIDDCLAMP CC T Clamp regulator current variation -100 — 100 mA
window
Clamp regulator current
ICLAMPINT CC D IMREG = 0 mA — — 0.7 mA
consumption
Table 38. Standby regulator specifications

Value
Min Typ Max
After trimming,
VSBY CC P Standby regulator output voltage 1.02 1.06 1.26 V
maximum load
Standby regulator current
IDDSBY CC T — — — 50 mA
provided to VDD_LV domain
4.15.3 Voltage monitors

The monitors and their associated levels for the device are given in Table 39. Figure 15
illustrates the workings of voltage monitoring threshold.
70/139 DS11758 Rev 6

Figure 15. Voltage monitor threshold definition
VDD_xxx
VHVD
VLVD
TVMFILTER TVMFILTER
HVD TRIGGER
(INTERNAL)
TVMFILTER TVMFILTER
LVD TRIGGER
(INTERNAL)
Table 39. Voltage monitor electrical characteristics

Value(2)
Symbol C Supply/Parameter(1) Conditions Unit
Min Typ Max
PowerOn Reset HV
VPOR200_C CC P VDD_HV_IO_MAIN — 1.80 2.18 2.40 V
Minimum Voltage Detectors HV
VMVD270_C CC P VDD_HV_IO_MAIN — 2.71 2.76 2.80 V
VMVD270_F CC P VDD_HV_FLA — 2.71 2.76 2.80 V
VMVD270_SBY CC P VDD_HV_IO_MAIN (in Standby) — 2.71 2.76 2.80 V
Low Voltage Detectors HV
VLVD290_C CC P VDD_HV_IO_MAIN — 2.89 2.94 2.99 V
VLVD290_F CC P VDD_HV_FLA — 2.89 2.94 2.99 V
VLVD290_AD CC P VDD_HV_ADV (ADCSD pad) — 2.89 2.94 2.99 V
VLVD290_AS CC P VDD_HV_ADV (ADCSAR pad) — 2.89 2.94 2.99 V
VLVD290_IJ CC P VDD_HV_IO_JTAG — 2.89 2.94 2.99 V
DS11758 Rev 6 71/139

73
Table 39. Voltage monitor electrical characteristics (continued)

Value(2)
Min Typ Max
VLVD290_IF CC P VDD_HV_IO_FLEX — 2.89 2.94 2.99 V

VLVD400_AD CC P VDD_HV_ADV (ADCSD pad) — 4.15 4.23 4.31 V
VLVD400_AS CC P VDD_HV_ADV (ADCSAR pad) — 4.15 4.23 4.31 V
VLVD400_IM CC P VDD_HV_IO_MAIN — 4.15 4.23 4.31 V
VLVD400_IJ CC P VDD_HV_IO_JTAG 4.15 4.23 4.31 V
VLVD400_IF CC P VDD_HV_IO_FLEX — 4.15 4.23 4.31 V
High Voltage Detectors HV
VHVD400_C CC P VDD_HV_IO_MAIN 3.68 3.75 3.82 V
VHVD400_IJ CC P VDD_HV_IO_JTAG 3.68 3.75 3.82 V
VHVD400_IF CC P VDD_HV_IO_FLEX — 3.68 3.75 3.82 V
Upper Voltage Detectors HV
VUVD600_C CC P VDD_HV_IO_MAIN 5.72 5.82 5.92 V
VUVD600_F CC P VDD_HV_FLA — 5.72 5.82 5.92 V
VUVD600_IJ CC P VDD_HV_IO_JTAG — 5.72 5.82 5.92 V
VUVD600_IF CC P VDD_HV_IO_FLEX — 5.72 5.82 5.92 V
PowerOn Reset LV
VPOR031_C CC P VDD_LV — 0.29 0.60 0.97 V
Minimum Voltage Detectors LV
VMVD082_C CC P VDD_LV — 0.85 0.88 0.91 V
VMVD082_B CC P VDD_LV_BD — 0.85 0.88 0.91 V
VMVD094_C CC P VDD_LV — 0.98 1.00 1.02 V
VMVD094_FA CC P VDD_LV (Flash) — 1.00 1.02 1.04 V
VMVD094_FB CC P VDD_LV (Flash) — 1.00 1.02 1.04 V
Low Voltage Detectors LV
VLVD100_C CC P VDD_LV — 1.06 1.08 1.11 V
VLVD100_SB CC P VDD_LV (In Standby) — 0.99 1.01 1.03 V
VLVD100_F CC P VDD_LV (Flash) — 1.08 1.10 1.12 V
High Voltage Detectors LV
VHVD134_C CC P VDD_LV — 1.28 1.31 1.33 V
Upper Voltage Detectors LV
VUVD140_C CC P VDD_LV — 1.34 1.37 1.39 V
VUVD140_F CC P VDD_LV (Flash) — 1.34 1.37 1.39 V
72/139 DS11758 Rev 6

Table 39. Voltage monitor electrical characteristics (continued)

Value(2)
Min Typ Max
Common
(3)
TVMFILTER CC D Voltage monitor filter — 5 — 25 μs
1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative
condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with
minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented.
For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing
the limitations provided in Section 4.2: Absolute maximum ratings.
2. The values reported are Trimmed values, where applicable.
3. See Figure 15. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be
delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to
temperature, process and voltage variations.
DS11758 Rev 6 73/139

73
4.16 Flash memory

The following table shows the Wait state configuration.
Table 40. Wait state configuration

APC RWSC Frequency range (MHz)
0 f<30
1 f<60
2 f<90
000(1)
3 f<120
4 f<150
5 f<180
0 f<30
1 f<60
2 f<90
100(2)
3 f<120
4 f<150
5 f<180
2 55<f<80
3 55<f<120
001(3)
4 55<f<160
5 55<f<180
1. STD pipelined.
2. No pipeline.
3. Pipeline with 1 Tck address anticipation.
The following table shows the Program/Erase Characteristics.
Table 41. Flash memory program and erase specifications

Value
Lifetime
Initial max
Symbol Characteristics(1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles
Double Word (64 bits)

program time EEPROM
tdwprogram 55 C 130 — — 140 650 C µs
(partitions 2, 3, 4) [Packaged
part]
tpprogram Page (256 bits) program time 76 C 240 — — 255 1000 C µs
74/139 DS11758 Rev 6

Table 41. Flash memory program and erase specifications (continued)

Value
Lifetime
Initial max
Symbol Characteristics (1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles
Page (256 bits) program time

tpprogrameep EEPROM (partitions 2, 3, 4) 90 C 300 — — 315 1300 C µs
[Packaged part]
Quad Page (1024 bits)
tqprogram 220 C 840 1200 P 850 2000 C µs
program time
Quad Page (1024 bits)
program time EEPROM
tqprogrameep 306 C 1200 1800 P 1270 2600 C µs
(partitions 2, 3, 4) [Packaged
part]
16 KB block pre-program and
t16kpperase 190 C 450 500 P 250 1000 — C ms
erase time
t32kpperase 250 C 520 600 P 310 1200 — C ms
erase time
t64kpperase 360 C 700 750 P 420 1600 — C ms
erase time
128 KB block pre-program
t128kpperase 600 C 1300 1600 P 800 4000 — C ms
and erase time
256 KB block pre-program
t256kpperase 1050 C 1800 2400 P 1600 4000 — C ms
and erase time
t16kprogram 16 KB block program time 25 C 45 50 P 40 1000 — C ms
Program 64 KB Data Flash -
t64kprogrameep EEPROM (partition 2,3) 120 C 200 300 P 330 2275 C ms
[Packaged part]
Erase 64 KB Data Flash -
t64keraseeep EEPROM (partition 2,3) 530 C 910 1150 P 1040 4700 C ms
[Packaged part]
Program 16 KB EEPROM
t16kprogrameep 30 C 52 75 P 84 1750 C ms
(partition 4) [KGD]
Erase 16 KB EEPROM
t16keraseeep 225 C 645 715 P 520 3600 C ms
(partition 4) [KGD]
s/M
tprr Program rate(8) 1.7 C 2.8 3.40 C 2.4 — C
B
DS11758 Rev 6 75/139

77
Table 41. Flash memory program and erase specifications (continued)

Value
Lifetime
Initial max
Symbol Characteristics (1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles
s/M
terr Erase rate(8) 4.8 C 7.2 9.6 C 6.4 — C
B
s/M
tprfm Program rate Factory Mode(8) 1.12 C 1.4 1.6 C — — C
B
s/M
terfm Erase rate Factory Mode(8) 4.0 C 5.2 5.8 C — — C
B
tffprogram Full flash programming time(9) 12.0 C 17.8 22.0 P 15.4 — — C s
tfferase Full flash erasing time(9) 25.0 C 40.0 50.0 P 40.0 — — C s
Erase suspend request
tESRT 200 T — — — — — — µs
rate(10)
Program suspend request
tPSRT 30 T — — — — — — µs
rate(10)
Array Integrity Check - Margin
tAMRT 15 T — — — — — — µs
Read suspend request rate
tPSUS Program suspend latency(11) — — — — — — 12 T µs
tESUS Erase suspend latency(11) — — — — — — 22 T µs
Array Integrity Check (6.0 MB,
tAIC0S 40 T — — — — — — — ms
sequential)(12)
Array Integrity Check (256
tAIC256KS 1.5 T — — — — — — — ms
KB, sequential)(12)
Array Integrity Check (6.0 MB,
tAIC0P 4.0 T — — — — — — — s
proprietary)(12)
Margin Read (6.0 MB,
tMR0S 120 T — — — — — — — ms
sequential)(12)
Margin Read (256 KB,
tMR256KS 4.0 T — — — — — — — ms
sequential)(12)
1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.
2. Actual hardware operation times; this does not include software overhead.
3. Typical program and erase times assume nominal supply values and operation at 25 °C.
4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but
not tested.
5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5%) supply
voltages.
7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5%) supply
voltages.
76/139 DS11758 Rev 6

8. Rate computed based on 256 KB sectors.

9. Only code sectors, not including EEPROM.
10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.
11. Timings guaranteed by design.
12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the
table is calculated at max frequency.
All the Flash operations require the presence of the system clock for internal
synchronization. About 50 synchronization cycles are needed: this means that the timings of
the previous table can be longer if a low frequency system clock is used.
Table 42. Flash memory Life Specification

Value
Symbol Characteristics(1) (2) Unit
Min C Typ C
NCER16K 16 KB CODE Flash endurance 10 — 100 — Kcycles

256 KB CODE Flash endurance 1 — 100 — Kcycles
NCER256K
(3)
256 KB CODE Flash endurance 10 — 100 — Kcycles
NDER64K 64 KB DATA EEPROM Flash endurance 250 — — — Kcycles
NDER16K 16 KB HSM DATA EEPROM Flash endurance 100 — — — Kcycles
Minimum data retention Blocks with 0 - 1,000 P/E
tDR1k 25 — — — Years
cycles
Minimum data retention Blocks with 1,001 - 10,000
P/E cycles
Minimum data retention Blocks with 10,001 - 100,000
P/E cycles
Minimum data retention Blocks with 100,001 -
250,000 P/E cycles
1. Program and erase cycles supported across specified temperature specifications.
2. It is recommended that the application enables the core cache memory.
3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time
are possible.
DS11758 Rev 6 77/139

77
4.17 AC Specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
4.17.1 Debug and calibration interface timing
4.17.1.1 JTAG interface timing
Table 43. JTAG pin AC electrical characteristics

Value(1),(2)
# Symbol C Characteristic Unit
Min Max
1 tJCYC CC D TCK cycle time 100 — ns

2 tJDC CC T TCK clock pulse width 40 60 %
3 tTCKRISE CC D TCK rise and fall times (40%–70%) — 3 ns
4 tTMSS, tTDIS CC D TMS, TDI data setup time 5 — ns
5 tTMSH, tTDIH CC D TMS, TDI data hold time 5 — ns
6 tTDOV CC D TCK low to TDO data valid — 15(3) ns
7 tTDOI CC D TCK low to TDO data invalid 0 — ns
8 tTDOHZ CC D TCK low to TDO high impedance — 15 ns
9 tJCMPPW CC D JCOMP assertion time 100 — ns
10 tJCMPS CC D JCOMP setup time to TCK low 40 — ns
11 tBSDV CC D TCK falling edge to output valid — 600(4) ns
12 tBSDVZ CC D TCK falling edge to output valid out of high impedance — 600 ns
13 tBSDHZ CC D TCK falling edge to output high impedance — 600 ns
14 tBSDST CC D Boundary scan input valid to TCK rising edge 15 — ns
15 tBSDHT CC D TCK rising edge to boundary scan input invalid 15 — ns
1. These specifications apply to JTAG boundary scan only. See Table 44 for functional specifications.
2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the
datasheet.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
78/139 DS11758 Rev 6

Figure 16. JTAG test clock input timing
TCK
2
3 2
1 3
Figure 17. JTAG test access port timing
TCK
TMS, TDI
7 8
TDO
DS11758 Rev 6 79/139

106
Figure 18. JTAG JCOMP timing
TCK
10
JCOMP
Figure 19. JTAG boundary scan timing
TCK
11 13
Output
Signals
12
Output
Signals
14
15
Input
Signals
80/139 DS11758 Rev 6

4.17.1.2 Nexus interface timing
Table 44. Nexus debug port timing

Value(1)
Min Max
7 tEVTIPW CC D EVTI pulse width 4 — tCYC(2)

8 tEVTOPW CC D EVTO pulse width 40 — ns
(3),(4)
TCK cycle time 2 — tCYC(2)
Absolute minimum TCK cycle time(5) (TDO sampled on posedge
40(6) —
9 tTCYC CC D of TCK)
ns
Absolute minimum TCK cycle time(7) (TDO sampled on negedge (6)
20 —
of TCK)
11 tNTDIS CC D TDI data setup time 5 — ns
12 tNTDIH CC D TDI data hold time 5 — ns
13 tNTMSS CC D TMS data setup time 5 — ns
14 tNTMSH CC D TMS data hold time 5 — ns
15 — CC D TDO propagation delay from falling edge of TCK(8) — 16 ns
TDO hold time with respect to TCK falling edge (minimum TDO
16 — CC D 2.25 — ns
propagation delay)
1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.
6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
7. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge.
8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
DS11758 Rev 6 81/139

106
Figure 20. Nexus output timing
MCKO
6
MDO
MSEO Output Data Valid
EVTO
Figure 21. Nexus event trigger and test clock timings
TCK
EVTI
EVTO 9
TCK
EVTI
EVTO 9 7 7
8 8
82/139 DS11758 Rev 6

Figure 22. Nexus TDI, TMS, TDO timing
TCK
11
13
12
14
TMS, TDI
15
16
TDO
4.17.1.3 External interrupt timing (IRQ pin)
Table 45. External interrupt timing

Characteristic Symbol Min Max Unit
IRQ Pulse Width Low tIPWL 3 — tcyc

IRQ Pulse Width High tIPWH 3 — tcyc
IRQ Edge to Edge Time(1) tICYC 6 — tcyc
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
DS11758 Rev 6 83/139

106
Figure 23. External interrupt timing
IRQ
1 2
Figure 24. External interrupt timing
D_CLKOUT
IRQ
1 2
4.17.2 DSPI timing with CMOS pads

DSPI channel frequency support is shown in Table 46.
Timing specifications are shown in the tables below.
84/139 DS11758 Rev 6

Table 46. DSPI channel frequency support

Max usable
DSPI use mode(1) frequency
(MHz)(2),(3)
DSPI_0, DSPI_3,
12
DSPI_5, DSPI_7
DSPI_8 5
Full duplex – Classic timing (Table 47)
DSPI_1, DSPI_2,
DSPI_4, DSPI_6, 17
DSPI_9
DSPI_0, DSPI_3,
CMOS (Master 12
DSPI_5, DSPI_7
mode)
DSPI_8 5
Full duplex – Modified timing (Table 48)
DSPI_1, DSPI_2,
DSPI_4, DSPI_6, 30
DSPI_9
Output only mode (SCK/SOUT/PCS) (Table 47 and
— 30
Table 48)
Output only mode TSB mode (SCK/SOUT/PCS) — 30
CMOS (Slave mode Full duplex) (Table 49) — 16
1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file
attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum
performance with every possible combination of pins.
2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
3. Maximum usable frequency does not take into account external device propagation delay.
4.17.2.1 DSPI master mode full duplex timing with CMOS pads
4.17.2.1.1 DSPI CMOS master mode – classic timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise
and fall times of the output pads.
Table 47. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1
Condition Value(1)
Pad drive(2) Load (CL) Min Max
SCK drive strength

Very strong 25 pF 59.0 —
1 tSCK CC D SCK cycle time
Strong 50 pF 80.0 — ns
Medium 50 pF 200.0 —
DS11758 Rev 6 85/139

106
MTFE = 0, CPHA = 0 or 1 (continued)
Condition Value(1)
SCK and PCS drive strength

(N(3) × tSYS(4)) –
Very strong 25 pF —
16
(N(3) × tSYS(4)) –
Strong 50 pF —
PCS to SCK 16
2 tCSC CC D
delay ns
(N(3) × tSYS(4)) –
Medium 50 pF —
16
PCS medium
PCS = 50 pF (N(3) × tSYS(4)) –
and SCK —
SCK = 50 pF 29
strong
SCK and PCS drive strength
PCS = 0 pF (M(5) × tSYS(4)) –
Very strong —
SCK = 50 pF 35
PCS = 0 pF (M(5) × tSYS(4)) –
Strong —
SCK = 50 pF 35
3 tASC CC D After SCK delay
PCS = 0 pF (M(5) × tSYS(4)) – ns
Medium —
SCK = 50 pF 35
PCS medium
PCS = 0 pF (M(5) × tSYS(4)) –
and SCK —
SCK = 50 pF 35
strong
SCK drive strength
Very strong 0 pF 1/ 1/
SCK duty 2tSCK –2 2tSCK +2
4 tSDC CC D
cycle(6) Strong 0 pF 1/ 1/
2tSCK –2 2tSCK +2 ns
1/ 1/
Medium 0 pF 2tSCK –5 2tSCK +5
PCS strobe timing
PCSx to PCSS PCS and PCSS drive strength

5 tPCSC CC D
time(7) Strong 25 pF 16.0 — ns
PCSS to PCSx PCS and PCSS drive strength

6 tPASC CC D
time(7) Strong 25 pF 16.0 — ns
SIN setup time
SCK drive strength
SIN setup time to Very strong 25 pF 25.0 —

7 tSUI CC D
SCK(8) Strong 50 pF 31.0 — ns
86/139 DS11758 Rev 6

Condition Value(1)
SIN hold time

SCK drive strength
SIN hold time Very strong 0 pF –1.0 —

8 tHI CC D
from SCK(8) Strong 0 pF –1.0 — ns
Medium 0 pF –1.0 —
SOUT data valid time (after SCK edge)
SOUT and SCK drive strength
SOUT data valid Very strong 25 pF — 7.0

9 tSUO CC D
time from SCK(9) Strong 50 pF — 8.0 ns
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
SOUT and SCK drive strength
SOUT data hold Very strong 25 pF –7.7 —

10 tHO CC D
time after SCK(9) Strong 50 pF –11.0 — ns
1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7. PCSx and PCSS using same pad configuration.
8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds.
9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
DS11758 Rev 6 87/139

106
Figure 25. DSPI CMOS master mode — classic timing, CPHA = 0
tCSC tASC
PCSx
tSDC tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tSUI
tHI
SIN First Data Data Last Data
tSUO tHO
SOUT First Data Data Last Data
Figure 26. DSPI CMOS master mode — classic timing, CPHA = 1
3&6[
6&.2XWSXW
&32/
6&.2XWSXW
&3 2/
W68, W+,
6,1 )LUVW'DWD 'DWD /DVW'DWD
W682 W+2
6287 )LUVW'DWD 'DWD /DVW'DWD
88/139 DS11758 Rev 6

Figure 27. DSPI PCS strobe (PCSS) timing (master mode)
tPCSC tPASC
PCSS
PCSx
4.17.2.1.2 DSPI CMOS master mode — modified timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise
and fall times of the output pads.
Table 48. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1
Condition Value(1)
SCK drive strength

Very strong 25 pF 33.0 —
1 tSCK CC D SCK cycle time
SCK and PCS drive
strength
Very strong 25 pF (N(3) × tSYS(4)) – 16 —
PCS to SCK Strong 50 pF (N(3) × tSYS(4)) – 16 —
2 tCSC CC D
delay (3) (4)
Medium 50 pF (N × tSYS ) – 16 — ns
PCS
PCS = 50 pF
medium and (N(3) × tSYS(4)) – 29 —
SCK = 50 pF
SCK strong
SCK and PCS drive
strength
PCS = 0 pF
Very strong (M(5) × tSYS(4)) – 35 —
SCK = 50 pF
PCS = 0 pF
Strong (M(5) × tSYS(4)) – 35 —
3 tASC CC D After SCK delay SCK = 50 pF
PCS = 0 pF ns
Medium (M(5) × tSYS(4)) – 35 —
SCK = 50 pF
PCS
PCS = 0 pF
medium and (M(5) × tSYS(4)) – 35 —
SCK = 50 pF
SCK strong
DS11758 Rev 6 89/139

106
Condition Value(1)
SCK drive strength

Very strong 0 pF 1 1
/2tSCK – 2 /2tSCK + 2
4 tSDC CC D SCK duty cycle(6)
1 1
Strong 0 pF /2tSCK – 2 /2tSCK + 2 ns
1 1
Medium 0 pF /2tSCK – 5 /2tSCK + 5
PCS strobe timing
PCS and PCSS drive
PCSx to PCSS strength
5 tPCSC CC D
time(7)
PCS and PCSS drive
PCSS to PCSx strength
6 tPASC CC D
time(7)
SIN setup time
SCK drive strength
SIN setup time to Very strong 25 pF 25 – (P(9) × tSYS(4)) —
SCK
(9) (4)
CPHA = 0(8) Strong 50 pF 31 – (P × tSYS ) — ns
Medium 50 pF 52 – (P(9) × tSYS(4)) —
7 tSUI CC D
SCK drive strength
SIN setup time to Very strong 25 pF 25.0 —
SCK
CPHA = 1(8) Strong 50 pF 31.0 — ns
SIN hold time
SCK drive strength
SIN hold time Very strong 0 pF –1 + (P(9) × tSYS(3)) —
from SCK
(9) (3)
CPHA = 0(8) Strong 0 pF –1 + (P × tSYS ) — ns
Medium 0 pF –1 + (P(9) × tSYS(3)) —
8 tHI CC D
SCK drive strength
SIN hold time Very strong 0 pF –1.0 —
from SCK
CPHA = 1(8) Strong 0 pF –1.0 — ns
90/139 DS11758 Rev 6

Condition Value(1)
SOUT data valid time (after SCK edge)

SOUT and SCK drive
strength
SOUT data valid
time from SCK Very strong 25 pF — 7.0 + tSYS(4)
CPHA = 0, (10) Strong 50 pF — 8.0 + tSYS(4) ns
Medium 50 pF — 16.0 + tSYS(4)
9 tSUO CC D
SOUT and SCK drive
strength
SOUT data valid
time from SCK Very strong 25 pF — 7.0
CPHA = 1(10) Strong 50 pF — 8.0 ns
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
SOUT and SCK drive
strength
SOUT data hold
time after SCK Very strong 25 pF –7.7 + tSYS(4) —
CPHA = 0(10) Strong 50 pF –11.0 + tSYS(4) — ns
Medium 50 pF –15.0 + tSYS(4) —
10 tHO CC D
SOUT and SCK drive
strength
SOUT data hold
time after SCK Very strong 25 pF –7.7 —
CPHA = 1(10) Strong 50 pF –11.0 — ns
1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
4. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
6. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7. PCSx and PCSS using same pad configuration.
8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL voltage thresholds.
9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_
MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1.
DS11758 Rev 6 91/139

106
10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
Figure 28. DSPI CMOS master mode — modified timing, CPHA = 0
tCSC tASC
PCSx
tSDC tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tSUI
tHI
tSUO tHO
Figure 29. DSPI CMOS master mode — modified timing, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI tHI tHI
tSUO tHO
92/139 DS11758 Rev 6

Figure 30. DSPI PCS strobe (PCSS) timing (master mode)
tPCSC tPASC
PCSS
PCSx
4.17.2.2 Slave mode timing
Table 49. DSPI CMOS slave timing — full duplex — normal and modified transfer formats
(MTFE = 0/1)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load
1 tSCK CC D SCK Cycle Time(1) — — 62 — ns

2 tCSC SR D SS to SCK Delay(1) — — 16 — ns
3 tASC SR D SCK to SS Delay(1) — — 16 — ns
4 tSDC CC D SCK Duty Cycle(1) — — 30 — ns
Very
25 pF — 50 ns
(1) (2) (3) strong
Slave Access Time
5 tA CC D
(SS active to SOUT driven) Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
Very
Slave SOUT Disable Time(1) 25 pF — 5 ns
(2) (3) strong
6 tDIS CC D
(SS inactive to SOUT High- Strong 50 pF — 5 ns
Z or invalid)
Data Setup Time for
9 tSUI CC D — — 10 — ns
Inputs(1)
10 tHI CC D Data Hold Time for Inputs(1) — — 10 — ns
Very
25 pF — 30 ns
strong
SOUT Valid Time(1) (2) (3)
11 tSUO CC D
(after SCK edge) Strong 50 pF — 30 ns
Very
25 pF 2.5 — ns
(1) (2) (3) strong
SOUT Hold Time
12 tHO CC D
(after SCK edge) Strong 50 pF 2.5 — ns
Medium 50 pF 2.5 — ns
1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds.
2. All timing values for output signals in this table, are measured to 50% of the output voltage.
3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
DS11758 Rev 6 93/139

106
Figure 31. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0
tASC
tCSC
SS
tSCK
SCK Input tSDC

(CPOL = 0)
tSDC
SCK Input
(CPOL = 1)
tA tSUO tHO
tDIS
tSUI tHI
Figure 32. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
tSUO
tA
tHO tDIS
tSUI
tHI
4.17.3 Ethernet timing

The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be
configured for either CMOS or TTL signal levels compatible with devices operating at either
5.0 V or 3.3 V. Please check the device pinout details to review the packages supporting MII
and RMII.
94/139 DS11758 Rev 6

4.17.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the RX_CLK frequency.
Note: In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the
valid input levels, 0.8 V and 2.0 V.
Table 50. MII receive signal timing

Value
Symbol C Characteristic Unit
Min Max
M1 CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 — ns

M2 CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 — ns
M3 CC D RX_CLK pulse width high 35% 65% RX_CLK period
M4 CC D RX_CLK pulse width low 35% 65% RX_CLK period
Figure 33. MII receive signal timing diagram
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1 M2
4.17.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.
equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
option allows the use of non-compliant MII PHYs.
Refer to the SPC584Gx, SPC58EGx, SPC58NGx 32-bit Power Architecture microcontroller
reference manual’s Ethernet chapter for details of this option and how to enable it.
Note: In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the
valid output levels, 0.8 V and 2.0 V.
DS11758 Rev 6 95/139

106
Table 51. MII transmit signal timing

Value(1)
Min Max
M5 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns

M6 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns
M7 CC D TX_CLK pulse width high 35% 65% TX_CLK period
M8 CC D TX_CLK pulse width low 35% 65% TX_CLK period
1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance
is accounted for, and does not need to be subtracted from the 25 pF value
Figure 34. MII transmit signal timing diagram
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
4.17.3.3 MII async inputs signal timing (CRS and COL)
Table 52. MII async inputs signal timing

Value
Min Max
M9 CC D CRS, COL minimum pulse width 1.5 — TX_CLK period
Figure 35. MII async inputs timing diagram
CRS, COL
M9
96/139 DS11758 Rev 6

4.17.3.4 MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.
Figure 36. MII serial management channel timing diagram
M14 M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
4.17.3.5 MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.
Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)
to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is
referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
Table 53. MII serial management channel timing

Value
Min Max
MDC falling edge to MDIO output invalid

M10 CC D 0 — ns
(minimum propagation delay)
MDC falling edge to MDIO output valid (max
M11 CC D — 25 ns
prop delay)
M12 CC D MDIO (input) to MDC rising edge setup 10 — ns
M13 CC D MDIO (input) to MDC rising edge hold 0 — ns
M14 CC D MDC pulse width high 40% 60% MDC period
M15 CC D MDC pulse width low 40% 60% MDC period
DS11758 Rev 6 97/139

106
Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)
to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is
referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
Table 54. RMII serial management channel timing

Value
Min Max
MDC falling edge to MDIO output invalid

M10 CC D 0 — ns
(minimum propagation delay)
MDC falling edge to MDIO output valid (max
M11 CC D — 25 ns
prop delay)
M12 CC D MDIO (input) to MDC rising edge setup 10 — ns
M13 CC D MDIO (input) to MDC rising edge hold 0 — ns
M14 CC D MDC pulse width high 40% 60% MDC period
M15 CC D MDC pulse width low 40% 60% MDC period
Figure 37. MII serial management channel timing diagram
M14 M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
4.17.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.
98/139 DS11758 Rev 6

Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the
valid input levels, 0.8 V and 2.0 V.
Table 55. RMII receive signal timing

Value
Min Max
R1 CC D RXD[1:0], CRS_DV to REF_CLK setup 4 — ns

R2 CC D REF_CLK to RXD[1:0], CRS_DV hold 2 — ns
R3 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R4 CC D REF_CLK pulse width low 35% 65% REF_CLK period
Figure 38. RMII receive signal timing diagram
R3
REF_CLK (input)
R4
RXD[1:0] (inputs)
CRS_DV
R1 R2
4.17.3.7 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.
equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK
frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the
rising or falling edge of REF_CLK, and the timing is the same in either case. This option
allows the use of non-compliant RMII PHYs.
Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the
valid output levels, 0.8 V and 2.0 V.
RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on
the pad as 1ns.
DS11758 Rev 6 99/139

106
Table 56. RMII transmit signal timing

Value
Min Max
R5 CC D REF_CLK to TXD[1:0], TX_EN invalid 2 — ns

R6 CC D REF_CLK to TXD[1:0], TX_EN valid — 14 ns
R7 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R8 CC D REF_CLK pulse width low 35% 65% REF_CLK period
Figure 39. RMII transmit signal timing diagram
R7
REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN
R6
4.17.4 FlexRay timing

This section provides the FlexRay Interface timing characteristics for the input and output
signals.
These are recommended numbers as per the FlexRay EPL v3.0 specification, and subject
to change per the final timing analysis of the device.
100/139 DS11758 Rev 6

4.17.4.1 TxEN
Figure 40. TxEN signal
TxEN
80 %
20 %
dCCTxENFALL dCCTxENRISE
Table 57. TxEN output characteristics

Value
Symbol C Characteristic(1) (2) Unit
Min Max
dCCTxENRISE25 CC D Rise time of TxEN signal at CC — 9 ns

dCCTxENFALL25 CC D Fall time of TxEN signal at CC — 9 ns
Sum of delay between Clk to Q of the last FF and the final
dCCTxEN01 CC D — 25 ns
output buffer, rising edge
Sum of delay between Clk to Q of the last FF and the final
dCCTxEN10 CC D — 25 ns
output buffer, falling edge
1. TxEN pin load maximum 25 pF.
2. Pad configured as VERY STRONG.
DS11758 Rev 6 101/139

106
Figure 41. TxEN signal propagation delays
PE_Clk
TxEN
dCCTxEN10 dCCTxEN01
4.17.4.2 TxD
Figure 42. TxD signal
TxD
dCCTxD50%
80 %
50 %
20 %
dCCTxDFALL dCCTxDRISE
Note: In the following table, specifications valid according to FlexRay EPL 3.0.1 standard with
20%–80% levels and a 10 pF load at the end of a 50 Ohm, 1 ns stripline. Please refer to the
Very Strong I/O pad specifications.
102/139 DS11758 Rev 6

Table 58. TxD output characteristics

Value
Symbol C Characteristic(1),(2) Unit
Min Max
Asymmetry of sending CC at 25 pF load

dCCTxAsym CC D –2.45 2.45 ns
(= dCCTxD50% − 100 ns)
D Sum of Rise and Fall time of TxD signal at the — 9(4)
dCCTxDRISE25+dCCTxDFALL25 CC (3) ns
D output pin — 9(5)
Sum of delay between Clk to Q of the last FF
dCCTxD01 CC D — 25 ns
and the final output buffer, rising edge
Sum of delay between Clk to Q of the last FF
dCCTxD10 CC D — 25 ns
and the final output buffer, falling edge
1. TxD pin load maximum 25 pF.
2. Pad configured as VERY STRONG.
3. Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire
temperature range of the device has been taken into account.
4. VDD_HV_IO = 5.0 V ± 10%, Transmission line Z = 50 ohms, tdelay = 1 ns, CL = 10 pF.
5. VDD_HV_IO = 3.3 V ± 10%, Transmission line Z = 50 ohms, tdelay = 0.6 ns, CL = 10 pF.
Figure 43. TxD Signal propagation delays
PE_Clk*
TxD
dCCTxD10 dCCTxD01
* FlexRay Protocol Engine Clock
4.17.4.3 RxD
Table 59. RxD input characteristics

Value
Min Max
C_CCRxD CC D Input capacitance on RxD pin — 7 pF

uCCLogic_1 CC D Threshold for detecting logic high 35 70 %
DS11758 Rev 6 103/139

106
Table 59. RxD input characteristics (continued)

Value
Min Max
uCCLogic_0 CC D Threshold for detecting logic low 30 65 %

Sum of delay from actual input to the D input of the
dCCRxD01 CC D — 10 ns
first FF, rising edge
Sum of delay from actual input to the D input of the
dCCRxD10 CC D — 10 ns
first FF, falling edge
Acceptance of asymmetry at receiving CC with
dCCRxAsymAccept15 CC D –31.5 44 ns
15 pF load
Acceptance of asymmetry at receiving CC with
dCCRxAsymAccept25 CC D –30.5 43 ns
25 pF load
4.17.5 CAN timing

The following table describes the CAN timing.
Table 60. CAN timing

Value
Symbol C Parameter Condition Unit
Min Typ Max
CC D Medium type pads 25pF load — — 70

CAN
CC D controller Medium type pads 50pF load — — 80
propagation STRONG, VERY STRONG type pads
tP(RX:TX) CC D — — 60 ns
delay time 25pF load
standard
pads STRONG, VERY STRONG type pads
CC D — — 65
50pF load
CC D Medium type pads 25pF load — — 90
CAN
CC D controller Medium type pads 50pF load — — 100
propagation STRONG, VERY STRONG type pads
tPLP(RX:TX) CC D — — 80 ns
delay time 25pF load
low power
pads STRONG, VERY STRONG type pads
CC D — — 85
50pF load
4.17.6 UART timing

UART channel frequency support is shown in the following table.
104/139 DS11758 Rev 6

Table 61. UART frequency support

LINFlexD clock
Max usable frequency
frequency LIN_CLK Oversampling rate Voting scheme
(Mbaud)
(MHz)
16 5
3:1 majority voting
8 10
80 6 13.33
Limited voting on one
5 sample with configurable 16
sampling point
4 20
16 6.25
3:1 majority voting
8 12.5
100 6 16.67
Limited voting on one
5 sample with configurable 20
sampling point
4 25
4.17.7 I2C timing

The I2C AC timing specifications are provided in the following tables.
Note: In the following table, I2C input timing is valid for Automotive and TTL inputs levels,
hysteresis enabled, and an input edge rate no slower than 1 ns (10% – 90%).
Table 62. I2C input timing specifications – SCL and SDA

Value
No. Symbol C Parameter Unit
Min Max
PER_CLK
1 — CC D Start condition hold time 2 —
Cycle(1)
2 — CC D Clock low time 8 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 0.0 — ns
5 — CC D Clock high time 4 — PER_CLK Cycle
6 — CC D Data setup time 0.0 — ns
7 — CC D Start condition setup time (for repeated start condition only) 2 — PER_CLK Cycle
8 — CC D Stop condition setup time 2 — PER_CLK Cycle
1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.
Note: In the following table:

• All output timing is worst case and includes the mismatching of rise and fall times of the
output pads.
DS11758 Rev 6 105/139

106
• Output parameters are valid for CL = 25 pF, where CL is the external load to the device
(lumped). The internal package capacitance is accounted for, and does not need to be
subtracted from the 25 pF value.
• Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may
reduce operating speeds and may cause incorrect operation.
• Programming the IBFD register (I2C bus Frequency Divider) with the maximum
frequency results in the minimum output timings listed. The I2C interface is designed to scale
the data transition time, moving it to the middle of the SCL low period. The actual position is
affected by the pre-scale and division values programmed in the IBC field of the IBFD
register.
Table 63. I2C output timing specifications — SCL and SDA

Value
No. Symbol C Parameter Unit
Min Max
PER_CLK
1 — CC D Start condition hold time 6 —
Cycle(1)
2 — CC D Clock low time 10 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 7 — PER_CLK Cycle
5 — CC D Clock high time 10 — PER_CLK Cycle
6 — CC D Data setup time 2 — PER_CLK Cycle
7 — CC D Start condition setup time (for repeated start condition only) 20 — PER_CLK Cycle
8 — CC D Stop condition setup time 10 — PER_CLK Cycle
1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.
Figure 44. I2C input/output timing
2 5
SCL
6 8
4
1 3
7
SDA
106/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Package information
5 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
The following table lists the case numbers for SPC584Gx, SPC58EGx, SPC58NGx.
Table 64. Package case numbers

Package type Device type
eLQFP176 Production
eTQFP144 Production
FPBGA292 Production
5.1 eLQFP176 package information

Refer to Section 5.1.1: Package mechanical drawings and data information for full
description of below figures and table notes.
DS11758 Rev 6 107/139

120
Package information SPC584Gx, SPC58EGx, SPC58NGx
Figure 45. eLQFP176 package outline
OLIHDXJPHQWHG
108/139 DS11758 Rev 6

Figure 46. eLQFP176 section A-A
ș ș
ș
Figure 47. eLQFP176 section B-B
DS11758 Rev 6 109/139

120
Table 65. eLQFP176 package mechanical data

Dimensions(7),(17)
Symbol
Min. Nom. Max.
Ө 0° 3.5° 7°
Ө1 0° — —
Ө2 10° 12° 14°
Ө3 10° 12° 14°
(15)
A — — 1.60
(12)
A1 0.05 — 0.15
A2(15) 1.35 1.40 1.45
(8),(9),(11)
b 0.17 0.22 0.27
(11)
b1 0.17 0.20 0.23
c(11) 0.09 — 0.20
c1(11) 0.09 — 0.16
D(4) 26.00 BSC
(2),(5)
D1 24.00 BSC
(13)
D2 — — 8.97
D3(14) 7.30 — —
e 0.50 BSC
(4)
E 26.00 BSC
E1(2),(5) 24.00 BSC
E2(13) — — 8.97
(14)
E3 7.30 — —
L 0.45 0.60 0.75
L1 1.00 REF
N(16) 176
R1 0.08 — —
R2 0.08 — 0.20
S 0.20 —
aaa(1),(18) 0.20
(1),(18)
bbb 0.20
(1),(18)
ccc 0.08
ddd(1),(18) 0.08
110/139 DS11758 Rev 6

5.1.1 Package mechanical drawings and data information

The following notes are related to Figure 45, Figure 46, Figure 47 and Table 65:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeter except where explicitly noted.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself. Type of exposed pad on SPC584Gx, SPC58EGx, SPC58NGx
is as Figure 48. End user should verify D2 and E2 dimensions according to the specific
device application.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the max number of terminal positions for the specified body size.
17. Critical dimensions:
a) Stand-Off
b) Overall Width
c) Lead Coplanarity
18. For symbols, recommended values and tolerances, see Table 66.
DS11758 Rev 6 111/139

120
Figure 48. eLQFP176 leadframe pad design
Note: number, dimensions and positions of grooves are for reference only.
Table 66. eLQFP176 symbol definitions

Symbol Definition Notes
The tolerance that controls the position of For flange-molded packages, this tolerance
the terminal pattern with respect to Datum A also applies for basic dimensions D1 and
aaa and B. The center of the tolerance zone for E1. For packages tooled with intentional
each terminal is defined by basic dimension terminal tip protrusions, aaa does not apply
e as related to Datum A and B. to those protrusions.
The bilateral profile tolerance that controls
the position of the plastic body sides. The
bbb —
centers of the profile zones are defined by
the basic dimensions D and E.
The unilateral tolerance located above the
This tolerance is commonly know as the
ccc seating plane where in the bottom surface of
“coplanarity” of the package terminals.
all terminals must be located.
The tolerance that controls the position of
the terminals to each other. The centers of This tolerance is normally compounded with
ddd
the profile zones are defined by basic tolerance zone defined by “b”.
dimension e.
5.2 eTQFP144 package information

112/139 DS11758 Rev 6

Figure 49. eTQFP144 package outline
OLIHDXJPHQWHG
DS11758 Rev 6 113/139

120
Figure 50. eTQFP144 section A-A
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Figure 51. eTQFP144 section B-B
114/139 DS11758 Rev 6

Table 67. eTQFP144 package mechanical data

Dimensions(7),(17)
Symbol
Min. Typ. Max.
θ 0.0° 3.5° 7.0°

θ1 0.0° — —
θ2 10.0° 12.0° 14.0°
θ3 10.0° 12.0° 14.0°
(15)
A — — 1.20
(12)
A1 0.05 — 0.15
A2(15) 0.95 1.00 1.05
(8),(9),(11)
b 0.17 0.22 0.27
(11)
b1 0.17 0.20 0.23
c(11) 0.09 — 0.20
c1(11) 0.09 — 0.16
D(4) — 22.00 BSC —
(2),(5)
D1 — 20.00 BSC —
(13)
D2 — — 8.96
D3(14) 7.30 — —
(4)
E — 22.00 BSC —
(2),(5)
E1 — 20.00 BSC —
E2(13) — — 8.96
E3(14) 7.30 — —
e 0.50 BSC
L 0.45 0.60 0.75
L1 — 1.00 REF —
N(16) 144
R1 0.08 — —
R2 0.08 — 0.20
S 0.20 — —
aaa(1),(18) 0.20
(1),(18)
bbb 0.20
(1),(18)
ccc 0.08
ddd(1),(18) 0.08
DS11758 Rev 6 115/139

120

The following notes are related to Figure 49, Figure 50, Figure 51 and Table 67:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeter except where explicitly noted.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. Dimensions D2 and E2 show the maximum exposed metal area on the package
surface where the exposed pad is located (if present). It includes all metal protrusions
from exposed pad itself. Type of exposed pad on SPC584Gx, SPC58EGx, SPC58NGx
is as Figure 52. End user should verify D2 and E2 dimensions according to the specific
device application.
14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of
exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by
internal edge of inner groove.
15. The optional exposed pad is generally coincident with the top or bottom side of the
package and not allowed to protrude beyond that surface.
16. “N” is the max number of terminal positions for the specified body size.
17. Critical dimensions:
a) Stand-Off
b) Overall Width
c) Lead Coplanarity
18. For symbols, recommended values and tolerances, see Table 68.
116/139 DS11758 Rev 6

Figure 52. eTQFP144 leadframe pad design
Note: number, dimensions and positions of grooves are for reference only.
Table 68. eTQFP144 symbol definitions

Symbol Definition Notes
The tolerance that controls the position of the For flange-molded packages, this tolerance also
terminal pattern with respect to Datum A and B. The applies for basic dimensions D1 and E1. For
aaa center of the tolerance zone for each terminal is packages tooled with intentional terminal tip
defined by basic dimension e as related to Datum A protrusions, aaa does not apply to those
and B. protrusions.
The bilateral profile tolerance that controls the
position of the plastic body sides. The centers of the
bbb —
profile zones are defined by the basic dimensions D
and E.
The unilateral tolerance located above the seating
This tolerance is commonly know as the
ccc plane where in the bottom surface of all terminals
“coplanarity” of the package terminals.
must be located.
The tolerance that controls the position of the
This tolerance is normally compounded with
ddd terminals to each other. The centers of the profile
tolerance zone defined by “b”.
zones are defined by basic dimension e.
DS11758 Rev 6 117/139

120
5.3 FPBGA292 package information

Figure 53. FPBGA292 package outline
(6)
118/139 DS11758 Rev 6

Table 69. FPBGA292 package mechanical data

Dimensions (in millimeter)
Symbol
Min. Typ. Max.
A(1) – – 1.8
A1 0.35 – –
A2 – 0.53 –
A4 – – 0.80
D 16.85 17.00 17.15
D1 – 15.20 –
E 16.85 17.00 17.15
E1 – 15.20 –
e – 0.80 –
(2)
b 0.50 0.55 0.60
Z – 0.90 –
aaa – – 0.15
bbb – – 0.10
(3)
ddd – – 0.12
eee(4) – – 0.15
(5)
fff – – 0.08

The following notes are related to Figure 53 and Table 69:
1. FPBGA stands for Fine Pitch Plastic Ball Grid Array.
Fine pitch: e < 1.00 mm pitch.
Low Profile: The total profile height (Dim A) is measured from the seating plane to the
top of the component.
The maximum total package height is calculated by the following methodology
(tolerance values):
2 2 2
Amax = A 1 ( TYP ) + A 2 ( TYP ) + A 4 ( TYP ) + ( A 1 ) + ( A 2 ) + ( A 4 )
2. The typical ball diameter before mounting is 0.55mm.

3. Ref. JEDEC MO_219G_BGA Low Profile, Fine Pitch Ball Grid Array Family, 0.80MM
Pitch (SQ. & RECT.)
4. The tolerance of position that controls the location of the pattern of balls with respect to
datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular
to datum C and located on true position with respect to datums A and B as defined by
e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with
respect to each other. For each ball there is a cylindrical tolerance zone fff
perpendicular to datum C and located on true position as defined by e. The axis
perpendicular to datum C of each ball must lie within this tolerance zone. Each
DS11758 Rev 6 119/139

120
tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
6. The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify
the terminal A1 corner. Exact shape of each corner is optional.
120/139 DS11758 Rev 6

5.4 Package thermal characteristics

The following tables describe the thermal characteristics of the device. The parameters in
this chapter have been evaluated by considering the device consumption configuration
reported in the Section 4.7: Device consumption.
5.4.1 eTQFP144
Table 70. Thermal characteristics for 144 exposed pad eTQFP package
Symbol C Parameter(1) Conditions Value Unit
RθJA CC D Junction-to-Ambient, Natural Convection(2) Four layer board (2s2p) 21.4 °C/W
At 200 ft./min., four layer
RθJMA CC D Junction-to-Moving-Air, Ambient(2) 15.7 °C/W
board (2s2p)
RθJB CC D Junction-to-board(3) — 8.5 °C/W
RθJCtop CC D Junction-to-case top(4) — 5.4 °C/W
RθJCbottom CC D Junction-to-case bottom(5) — 1 °C/W
(6)
ΨJT CC D Junction-to-package top Natural convection 1 °C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.4.2 LQFP176
Table 71. Thermal characteristics for 176 exposed pad LQFP package
(2)
RθJA CC D Junction-to-Ambient, Natural Convection Four layer board (2s2p) 20.9 °C/W
at 200 ft./min., four layer
RθJMA CC D Junction-to-Moving-Air, Ambient(2) 15.3 °C/W
board (2s2p)
RθJB CC D Junction-to-board(3) — 9 °C/W
(4)
RθJCtop CC D Junction-to-case top — 7.3 °C/W
RθJCbottom CC D Junction-to-case bottom(5) — 1 °C/W
ΨJT CC D Junction-to-package top(6) Natural convection 1 °C/W
resistance.
DS11758 Rev 6 121/139

124
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
5.4.3 FPBGA292
Table 72. Thermal characteristics for 292-pin FPBGA

RθJA CC D Junction-to-Ambient, Natural Convection (2) Four layer board (2s2p) 21.3 °C/W
RθJB CC D Junction-to-board(3) — 9.8 °C/W
RθJC CC D Junction-to-case(4) — 6.5 °C/W
(5)
ΨJT CC D Junction-to-package top Natural convection 0.6 °C/W
resistance.
Method 1012.1).
5.4.4 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:
Equation 1
TJ = TA + (RθJA * PD)
where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The differences between the
values determined for the single-layer (1s) board compared to a four-layer board that has
two signal layers, a power and a ground plane (2s2p), demonstrate that the effective
thermal resistance is not a constant. The thermal resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
122/139 DS11758 Rev 6

planes also reduce the thermal performance. When the clearance between the vias leaves
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:
Equation 2
TJ = TB + (RθJB * PD)
where:
TB = board temperature for the package perimeter (°C)
RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:
Equation 3
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RθCA. For example, change
the air flow around the device, add a heat sink, change the mounting arrangement on the
printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case
DS11758 Rev 6 123/139

124
thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (ΨJT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:
Equation 4
TJ = TT + (ΨJT x PD)
where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1
mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (ΨJPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:
Equation 5
TJ = TB + (ΨJPB x PD)
where:
TT = thermocouple temperature on bottom of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
124/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Ordering information
6 Ordering information
Figure 54. Ordering information scheme

Example code:
SPC58 N G 84 C3 Q E H 0 Y
Product identifier Core Product Memory Package Frequency Custom Security Silicon Packing
version revision
Y = Tray
X = Tape and Reel (pin1 top right)
0 = 1st version
1 = 2nd version
0 = No security and no ASIL-D

C = Security HW (HSM)
S = Safety (ASIL-D)
H = ASIL-D + Security HW (HSM)
0 = 8x ISO CAN FD, FlexRay

E = Ethernet 0
T = Ethernet 0 and 1
X = Extended feature (a)
E = 120 MHz at 105 oC
F = 160 MHz at 105 oC
G = 180 MHz at 105 oC
N = 120 MHz at 125 oC
P = 160 MHz at 125 oC
Q = 180 MHz at 125 oC
E7 = eLQFP176
E5 = eTQFP144
C3 = FPBGA292
84 = 6 MB
80 = 4 MB
G = SPC58NGx family
N = Triple computing e200z4 core

(CPU_2 + CPU_1 + CPU_0)
4 = Single computing e200z4 core
(CPU_2)
E = Dual computing e200z4 core
(CPU_2 + CPU_0)
SPC58 = Power Architecture in 40 nm

a: 2nd checker core, additional RAM, Microsecond channel, SENT bus.
Available extended feature are described in a customer specific addendum.
DS11758 Rev 6 125/139

127
Ordering information SPC584Gx, SPC58EGx, SPC58NGx
Note: Please contact your ST sales office to ask for the availability of a particular commercial
product.
Features (for instance, flash, RAM or peripherals) not included in the commercial product
cannot be used.
ST cannot be called to take any liability for features used outside the commercial product.
Table 73. Code Flash options

SPC58xG84 (6M) SPC58xG80 (4M) Partition Start address End address
16 16 0 0x00FC0000 0x00FC3FFF
16 16 0 0x00FC4000 0x00FC7FFF
16 16 1 0x00FC8000 0x00FCBFFF
16 16 1 0x00FCC000 0x00FCFFFF
32 32 0 0x00FD0000 0x00FD7FFF
32 32 1 0x00FD8000 0x00FDFFFF
64 64 0 0x00FE0000 0x00FEFFFF
64 64 0 0x00FF0000 0x00FFFFFF
128 128 0 0x01000000 0x0101FFFF
128 128 1 0x01020000 0x0103FFFF
256 256 0 0x01040000 0x0107FFFF
256 256 0 0x01080000 0x010BFFFF
256 256 0 0x010C0000 0x010FFFFF
256 256 0 0x01100000 0x0113FFFF
256 256 0 0x01140000 0x0117FFFF
256 256 0 0x01180000 0x011BFFFF
256 256 0 0x011C0000 0x011FFFFF
256 256 1 0x01200000 0x0123FFFF
256 256 1 0x01240000 0x0127FFFF
256 256 1 0x01280000 0x012BFFFF
256 256 1 0x012C0000 0x012FFFFF
256 256 1 0x01300000 0x0133FFFF
256 256 1 0x01340000 0x0137FFFF
256 256 1 0x01380000 0x013BFFFF
256 NA 5 0x013C0000 0x013FFFFF
256 NA 5 0x01400000 0x0143FFFF
256 NA 5 0x01440000 0x0147FFFF
256 NA 5 0x01480000 0x014BFFFF
256 NA 5 0x014C0000 0x014FFFFF
256 NA 5 0x01500000 0x0153FFFF
126/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Ordering information
Table 73. Code Flash options (continued) (continued)

SPC58xG84 (6M) SPC58xG80 (4M) Partition Start address End address
256 NA 5 0x01540000 0x0157FFFF

256 NA 5 0x01580000 0x015BFFFF
Table 74. RAM options(1)

SPC58EGx
SPC584G84 SPC584G80
SPC58NGx Type Start address End address
768 640 512
128 128 128 PRAMC_0 0x40060000 0x4007FFFF

96 96 96 PRAMC_1 0x40080000 0x40097FFF
64 64 NA PRAMC_1 0x40098000 0x400A7FFF
8 8 8 PRAMC_2 (STBY) 0x400A8000 0x400A9FFF
120 120 120 PRAMC_2 (STBY) 0x400AA000 0x400C7FFF
128 128 128 PRAMC_2 (STBY) 0x400C8000 0x400E7FFF
64 64 NA PRAMC_3 0x400E8000 0x400F7FFF
64 NA NA D-MEM CPU_0 0x50800000 0x5080FFFF
64 NA NA D-MEM CPU_1 0x51800000 0x5180FFFF
32 32 32 D-MEM CPU_2 0x52800000 0x52807FFF
1. RAM size is the sum of TCM and SRAM.
DS11758 Rev 6 127/139

127
Revision history SPC584Gx, SPC58EGx, SPC58NGx
7 Revision history
Table 75. Document revision history

Date Revision Changes
28-Jul-2016 1 Initial release.

Changed Microsoft Excel® workbook attached to this document (was
SPC584Gx_SPC58EGx_SPC58NGx_IO_Definition_v1.xlsx dated
July 26, 2016).
For details, refer to the sheet Revision History of the attached file
“SPC584Gx_SPC58EGx_SPC58NGx_IO_Definition_v2.xlsx”.
09-Sep-2016 2
Updated Section 4.12: ADC system
For ADC12 bit, “FAST SAR” updated to “Fast SAR” and “Slow SAR”
updated to “Slow SAR (SARADC_B)”
For ADC10 bit, instance of “Slow SAR” removed and “FAST SAR”
replaced with “–”.
128/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx Revision history
Table 75. Document revision history (continued)

Following are the changes for this release of the document:
Updated the cover page.

Section 4.1: Introduction:
– Removed text “The IPs and...for the details”.
– Removed the two notes.
Updated the Table 2: SPC584Gx, SPC58EGx, SPC58NGx features
summary
Updated the Figure 1: Block diagram
Table 3: Parameter classifications:
Updated the description of classification tag “T”.
Section 4.2: Absolute maximum ratings:
– Added text “Exposure to absolute ... reliability”
– Added text “even momentarily”
Table 4: Absolute maximum ratings:
– For parameter “IINJ”, text “DC” removed from description.
– Updated values in conditions column.
– Added parameter TTRIN.
– For parameter “TSTG”, maximum value updated from “175” to “125”
– Added new parameter “TPAS”
06-Jul-2017 3 – For parameter “IINJ”, description updated from “maximum...PAD” to
“maximum DC...pad”
Table 5: Operating conditions:
– For parameter “VDD_LV”, changed the classification from “D” to “P”
– Renamed the “Wait State configuration” table to “PRAM wait state
configuration”
– Footnote “1.260 V - 1.290 V range .. temperature profile” updated
to Text “... average supply value below or equal to 1.236 V ...”
– For parameter “IINJ1” description, text “DC” removed.
– Added note “In the range [1.14-1.08]V, the device....” to parameter
VDD_LV.
– Added parameter IINJ2
– Removed note “Core voltage as ....”
– Removed parameter “VRAMP_LV”.
– Updated the table footnote “Positive and negative Dynamic
current....”
Table 6: PRAM wait states configuration: Added this table.
Table 9: Device consumption:
– Updated the table and it’s values.
Table 12: I/O pull-up/pull-down electrical characteristics:
– Added note “When the device enters into standby mode... an ADC
function.”
DS11758 Rev 6 129/139

138

Table 13: WEAK/SLOW I/O output characteristics:

– Added “10%-90% in description of parameter “tTR_W”.
– For parameter “Fmax_W”, updated condition “25 pF load” to
“CL=25pF”
– For parameter “tTR_S”, changed min value (25 pF load) from “4” to
“3”
– Changed min value (50 pF load) from “6” to “5”
– For parameter “|tSKEW_W|”, changed max value from “30” to “25”.
Table 14: MEDIUM I/O output characteristics:
– Added “10%-90% in description of parameter “tTR_M”.
Table 15: STRONG/FAST I/O output characteristics:
– Added “10%-90% in description of parameter “tTR_S”.
– Parameter “IDCMAX_S” updated:
– Condition added “VDD=5V+10%
– Condition added “VDD=3.3V+10%
Max value updated to 5.5mA
Table 17: I/O consumption:
Updated all the max values of parameters IDYN_W and IDYN_M
Section 4.8: I/O pad specification:
06-Jul-2017 3 (cont’)
– Replaced all occurences of “50 pF load” with “CL=50pF”.
– Removed note “The external ballast....”
Section 4.8.2: I/O output DC characteristics:
– Added note “10%/90% is the....”
– “WEAK” to “WEAK/SLOW”
– “STRONG” to “STRONG/FAST”
– “VERY STRONG” to “VERY STRONG / VERY FAST”
Table 19: Reset Pad state during power-up and reset:
– Added this table.
Section 4.11: Oscillators:
– Removed figure “Test circuit”
Table 20: PLL0 electrical characteristics:
– For parameter “IPLL0”, classification changed from “C” to “T”.
– Footnote “Jitter values...measurement” added for parameters:
|ΔPLL0PHI0SPJ|
|ΔPLL0PHI1SPJ|
ΔPLL0LTJ
– For parameter “IPLL1”, classification changed from “C” to “T”.
– Footnote “Jitter values...measurement” added for parameter
“|ΔPLL1PHI0SPJ|”
130/139 DS11758 Rev 6


Table 22: External 40 MHz oscillator electrical specifications:

– Classification for parameters “CS_EXTAL” and “CS_EXTAL” changed
from “T” to “D”.
– Updated classification, conditions, min and max values for
parameter “gm”.
– Footnote “Ixatl is the oscillator...Test circuit is shown in Figure 8”
modified to “Ixatl is the oscillator...startup of the oscillator”.
– Minimum value of parameter “VIHEXT” updated from “VREF+0.6” to
“VREF+0.75”
– Maximum value of parameter “VILEXT” updated from “VREF-0.6” to
“VREF-0.75”
– Parameter “gm”, value “D” updated to “P” for “fXTAL < 8 MHz”, and
“D” for others.
– Footnote “This parameter is...100% tested” updated to “Applies to
an...to crystal mode”. Also added to parameter “VILEXT”.
– For parameters “VIHEXT” and “VILEXT”, Condition “–” updated to
“VREF = 0.29 * VDD_HV_IO_JTAG”
– Parameter “gm”, value “D” updated to “P” for “fXTAL < 8 MHz”, and
“D” for others.
– Footnote “This parameter is...100% tested” updated to “Applies to
an...to crystal mode”. Also added to parameter “VILEXT”.
– For parameters “VIHEXT” and “VILEXT”, Condition “–” updated to
06-Jul-2017 3 (cont’)
“VREF = 0.29 * VDD_HV_IO_JTAG”
– Updated parameters CS_EXTAL and CS_XTAL.
Renamed the section “RC oscillator 1024 kHz” to Section 4.11.4: Low
power RC oscillator“
Table 23: 32 kHz External Slow Oscillator electrical specifications:
– For parameter “gmsxosc”, changed the cassification to “P”.
Table 24: Internal RC oscillator electrical specifications:
– For parameter “IFIRC”, replaced max value of 300 with 600.
– Added footnote to the description.
– For parameter IFIRC, changed the max value to 600 and added
– Min, Typ and Max value of ”δfvar_SW” updated from “-1”, “-”, “1” to “-
0.5”, “+0.3” and “0.5” respectively.
Table 25: 1024 kHz internal RC oscillator electrical characteristics:
– For parameter “δfvar_T”, and “δfvar_V“ changed the cassification to
“P”.
– For parameter “δfvar_V”, minimum and maximum value updated
from “-0.05” and “+0.05” to “-5” and “+5”
Table 26: ADC pin specification:
– For ILKG, changed condition “C” to “—”.
– Added parameter “IINJ1”
– For parameter CP2, updated the max value to “1”.
DS11758 Rev 6 131/139

138

Table 27: SARn ADC electrical specification:

– Classification for parameter “IADCREFH” changed from “C” to “T”.
– Removed parameter “TUEINJ2”
– For parameter fADCK (High frequency mode), changed min value
from “7.5” to “> 13.33”.
– Deleted footnote “Values are subject to change (possibly improved
to ±2 LSB) after characterization”
Table 28: ADC-Comparator electrical specification:
– Classification for parameter “IADCREFH” changed from “C” to “T”
– Removed table footnote “Values are subject to change (possibly
improved to ±2 LSB) after characterization”
– Removed parameter “TUEINJ2”
Updated Figure 8: Input equivalent circuit (Fast SARn and SARB
channels)
Table 29: Temperature sensor electrical characteristics:
– For “temperature monitoring range”, classification removed (was C)
– Min and Max value of parameter “ΔPERREF” for condition “Long
period” updated from “TBD” to “-500” and “+500” respectively.
Table 31: LFAST transmitter electrical characteristics,,:
– Footnote “The transition time is measured from...” removed.
06-Jul-2017 3 (cont’) Updated Figure 26: DSPI CMOS master mode — classic timing,
CPHA = 1
Table 30: LVDS pad startup and receiver electrical characteristics,:
– For parameter ILVDS_BIAS, changed the characteristics to “C”
Table 32: LFAST PLL electrical characteristics:
– Min and Max value of parameter “ERRREF” updated from “TBD” to
“-1” and “+1” respectively
– Max value of parameter “PN” updated from “TBD” to “-58”
– Frequency of parameter “ΔPERREF” updated from “10MHz” to
“20MHz”.
– Max value of parameter “ΔPERREF” for condition “Single period”
updated from “TBD” to “350”
Table 33: Power management regulators:
– Removed text “In parts packaged with LQFP176, the auxiliary and
clamp regulators cannot be enabled” from note 2.
– Removed “SMPS regulator mode” from note 2.
Table 34: External components integration:
– For PMOS, replaced “STT4P3LLH6” with “PMPB100XPEA”
– For NMOS, replaced “STT6N3LLH6” with “PMPB55XNEA”
– Added table footnote to typ value of CS2.
– Removed table footnote “External components number.......”
132/139 DS11758 Rev 6


Table 35: Linear regulator specifications:

– Classification of parameter “IDDMREG” changed from “P” to “T”.
– Classification of parameter “IDDMREG” changed from “T” to “P”.
– Added “After trimming, external regulator mode”
Table 36: Auxiliary regulator specifications:
– Classification of parameter “IDDAUX” changed from “P” to “T”.
– Classification of parameter “IDDAUX” changed from “T” to “P”.
– Added “After trimming, external regulator mode”
Table 38: Standby regulator specifications:
– Classification of parameter “IDDSBY” changed from “P” to “T”.
– Classification of parameter “IDDSBY” changed from “T” to “P”.
Table 39: Voltage monitor electrical characteristics:
– For VPOR031_C, changed the max value from 0.85 to 0.97.
– For TVMFILTER, replaced T with D.
– Min value of “VPOR200_C” updated from “1.96” to “1.80”
– Max value of “VPOR031_C” updated from “.85” “0.97”
– Changed the min value of parameter VPOR200_C from “1.96” to
“1.80”
– Changed the max value of parameter VPOR031_C from “0.85” to
“0.97”
– Changed the condition of parameter TVMFILTER from “T” to “D”
Figure 15: Voltage monitor threshold definition: Updated the figure.
06-Jul-2017 3 (cont’) Updated Table 40: Wait state configuration
Table 44: Nexus debug port timing: Classification of parameters
“tEVTIPW” and “tEVTOPW” changed from “P” to “D”.
Table 46: DSPI channel frequency support:
– Added column to show slower and faster frequencies.
Table 47: DSPI CMOS master classic timing (full duplex and output
only) MTFE = 0, CPHA = 0 or 1:
– Changed the Min value of tSCK (very strong) from 33 to 59.
Updated Section 4.16: Flash memory
Added Section 4.17.5: CAN timing
Updated Figure 53: FPBGA292 package outline
Table 70: Thermal characteristics for 144 exposed pad eTQFP
package:
Updated the values.
Table 71: Thermal characteristics for 176 exposed pad LQFP
package
and Table 72: Thermal characteristics for 292-pin FPBGA: Updated
the tables and its values.
Updated Figure 54: Ordering information scheme
Added Table 73: Code Flash options
Added Table 74: RAM options
Changed Microsoft Excel® workbook attached to this document.
For details, refer to the sheet Revision History of the attached file
“SPC584Gx_SPC58EGx_SPC58NGx_IO_Definition_v4.xlsx”.
DS11758 Rev 6 133/139

138

Section 1: Introduction
Table 2: SPC584Gx, SPC58EGx, SPC58NGx features summary:
Added “Flash overlay RAM: 2x16KB”
Section 3: Package pinouts and signal descriptions
Added “pad characteristics” to heading
Section 4.1: Introduction
Reformated note from introduction
Section 4.3: Operating conditions
Replaced reference to IO_definition excel file by "the device pin out
IO definition excel file"
Updated the following parameters:
– IDD_LKG for all conditions
– IDDSTBY8 for all conditions
IDD_LV: added footnote “IDD_LKG and IDD_LV are reported as...”
Section 4.8: I/O pad specification
Replaced all references to the IO_definitions excel file by “the device
pinout IO definition excel file”.
Reformated note from introduction.
08-Feb-2018 4 Table 16: VERY STRONG/VERY FAST I/O output characteristics
– “tTR20-80” replaced by “tTR20-8_V”
– “tTRTTL” replaced by “tTRTTL_V”
– "ΣtTR20-80” replaced by “ΣtTR20-80_V”
Table 10: I/O pad specification descriptions: Removed latest
sentence at Standby pads description.
Table 15: STRONG/FAST I/O output characteristics: updated values
for tTR_S for condition CL = 25 pF and CL = 50 pF
Section 4.9: Reset pad (PORST, ESR0) electrical characteristics:
Table 18: Reset PAD electrical characteristics: replaced reference to
IO_definition excel file by "Refer to the device pin out IO definition
excel file".
Section 4.10: PLLs
Added “fINFIN”
Changed “C” by “—” in column “C”
– |ΔPLL0PHI0SPJ|: changed “T” by “D” and added pk-pk to Conditions
value
– |ΔPLL0PHI1SPJ|: added pk-pk to Conditions value
Table 21: PLL1 electrical characteristics
Added “fINFIN”
Changed “C” by “—” in column “C”
134/139 DS11758 Rev 6


Section 4.12: ADC system

Table 26: ADC pin specification:
Updated Max value for CS
For parameter CP2, updated the max value from “1” to “2”.
Added electrical specification for R20KΩ symbol.
Changed Max value = 1 by 2 for Cp2 SARB channels
Table 27: SARn ADC electrical specification:
Added symbols tADCINIT and tADCBIASINIT
Column “C” splitted and added “D” for IADV_S
Table 28: ADC-Comparator electrical specification:
Added new parameter “tADCINITSBY”.
Set min = 5/fADCK µs for 10-bit ADC mode, min = 2/fADCK for ADC
comparator mode, at symbol tADCSAMPLE.
Column “C” splitted and added “D” for IADV_S
Section 4.14: LFAST pad electrical characteristics
Introduction paragraph:
– 1st sentence: hidden text “both the SIPI and”
– all 2nd sentence hidden: “The same LVDS.. tables”
Section 4.14.2: LFAST and MSC/DSPILVDS interface electrical
characteristics: title completed with “and MSC/DSPI”
Section 4.15: Power management:
Figure 15: Voltage monitor threshold definition: right blue line
08-Feb-2018 4 (con’t) adjusted on the top figure.
Section 4.15.1: Power management integration: added sentence “It is
recommended...device itself” for all devices.
Table 35: Linear regulator specifications:
Updated values for symbol “ΔIDDMREG”
Min: added -100
Max: added 100
Section 4.16: Flash memory:
Table 41: Flash memory program and erase specifications: updated
this table.
Section 4.17: AC Specifications
Table 57: TxEN output characteristics: added table footnote “ Pad
configured as VERY STRONG.”
Table 58: TxD output characteristics: changed note 3 to apply to the
whole table.
Table 60: CAN timing: added columns for “CC” and “D”.
Section 5: Package information:
Table 69: FPBGA292 package mechanical data: updated Amax
formula in table footnote 2.
Section 5.4: Package thermal characteristics: Reformated note from
introduction.
Section 6: Ordering information:
Chapter title heading changed to heading 1.
Figure 54: Ordering information scheme: updated for Packing.
DS11758 Rev 6 135/139

138

Section 4.2: Absolute maximum ratings

Table 4: Absolute maximum ratings: added a cross ref to footnote
starting with “VDD_HV: allowed 5.5 V –6.0 V for 60 seconds...” to all
VDD_HV* parameters having max=6.0V. The same to VIN parameter.
Section 4.5: Electromagnetic compatibility characteristics: updated
section title from Electromagnetic emission characteristics to
Electromagnetic compatibility characteristics.
Section 4.7: Device consumption
– Changed “mA” by “µA“ for IDDSTBY128 with TJ = 55 °C.
– Updated table footnote 4.
– Updated IDDSTBY8, IDDSTBY128 and IDDSTBY256 max values and “C”
column at TJ=40°.
Section 4.10: PLLs
Table 20: PLL0 electrical characteristics: the maximum value of
fPLL0PHI0 is changed from “400” to “FSYS” with a footnote.
Section 4.11: Oscillators
Table 22: External 40 MHz oscillator electrical specifications: updated
footnote 1.
Table 28: ADC-Comparator electrical specification: added “ADC
04-Feb-2019 5 comparator mode” condition to the following two parameters:
– IADCREFH Min: - and Max: 19.5 µA
– IADCREFL Min: - and Max: 20.5 µA
Figure 9: LFAST and MSC/DSPI LVDS timing definition: updated.
Section 4.15: Power management
Table 34: External components integration: added “2SCR574D” for
parameter QEXT.
Section 4.16: Flash memory
Table 40: Wait state configuration: changed the minimum frequency
from 40 to 55 MHz for APC=001.
Section 5.1: eLQFP176 package information: updated mechanical
drawings and mechanical data.
Section 5.2: eTQFP144 package information: updated mechanical
drawings and mechanical data.
Section 6: Ordering information
Figure 54: Ordering information scheme:
– Updated Silicon revision, Security and Custom Version option lists.
– Added figure footnotes.
Table 74: RAM options:
– Updated PRAMC_1_64K and PRAMC_2_128K start address.
– Updated PRAMC_2_120K and D-MEM CPU_2 end address.
136/139 DS11758 Rev 6


Updated Revision 5.
Minor format changes throughout the document.
Section 1: Introduction
Removed “Document overview” section title.
Section 2: Description: changed title type.
Table 2: SPC584Gx, SPC58EGx, SPC58NGx features summary:
minor format changes.
Figure 1: Block diagram: updated
Figure 2: Periphery allocation: updated
Section 4.3: Operating conditions
– Table 5: Operating conditions: VDD_HV_ADR_S: removed line for C
condition.
– Table 7: Device supply relation during power-up/power-down
sequence: changed VDD_HV_IO_ to VDD_HV_IO_FLEX.
Section 4.6: Temperature profile: added the second paragraph.
Section 4.7: Device consumption
Table 9: Device consumption: Updated unit from “µA” to “mA” for
IDDSTBY128 at TJ=40°C condition.
Section 4.9: Reset pad (PORST, ESR0) electrical characteristics
Figure 5: Startup Reset requirements: deleted VDDMIN
Section 4.10: PLLs
26-Jul-2019 6 – Changed condition from T to D for |ΔPLL0PHI1SPJ|, ΔPLL0LTJ and
IPLL0.
– Updated Max value for fPLL0PHI0 symbol and removed the footnote.
Table 21: PLL1 electrical characteristics: changed condition from T to
D for IPLL1.
Section 4.11: Oscillators
Table 24: Internal RC oscillator electrical specifications: updated Max
value for IFIRC.
Figure 8: Input equivalent circuit (Fast SARn and SARB channels):
added parameter “CEXT: external capacitance” and component to
scheme.
Table 26: ADC pin specification: added row for symbol “CEXT / SR”.
Table 30: LVDS pad startup and receiver electrical characteristics,:
removed the last sentence of Note “Total internal capacitance...”.
Section 4.15: Power management
Table 34: External components integration: updated Conditions for
CBV.
Table 39: Voltage monitor electrical characteristics: added footnote
“Even if LVD/HVD ...”.
Section 4.16: Flash memory
Table 41: Flash memory program and erase specifications: updated.
Table 42: Flash memory Life Specification: updated.
DS11758 Rev 6 137/139

138

Section 4.17: AC Specifications

Section 4.17.3.7: RMII transmit signal timing (TXD[1:0], TX_EN):
added Note “RMII transmit ... as 1ns”.
Section 5: Package information
– Added introduction sentence in each Package section.
– Added “Package mechanical drawings and data information” sub-
section and introduction sentence to the notes list.
Table 64: Package case numbers: removed package reference
column.
Table 65: eLQFP176 package mechanical data:
– Updated table, notes and numbering.
– Moved notes to new section Section 5.1.1: Package mechanical
26-Jul-2019 6 (con’t) drawings and data information.
Figure 49: eTQFP144 package outline: updated figure.
Table 67: eTQFP144 package mechanical data:
– Updated table, notes content and numbering.
– Moved notes to new section Section 5.2.1: Package mechanical
drawings and data information.
Figure 53: FPBGA292 package outline: updated.
Table 69: FPBGA292 package mechanical data: updated.
Section 5.4.3: FPBGA292: updated title.
Table 72: Thermal characteristics for 292-pin FPBGA: updated
values.
Section 6: Ordering information
Figure 54: Ordering information scheme: added figure footnotes.
138/139 DS11758 Rev 6

SPC584Gx, SPC58EGx, SPC58NGx
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS11758 Rev 6 139/139

139

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SPC584Gx, SPC58EGx,

July 2019 DS11758 Rev 6 1/139

– Fast wakeup schemes

Table 1. Device summary

eTQFP144 SPC584G80E5 SPC58EG80E5 SPC58NG80E5 SPC584G84E5 SPC58EG84E5 SPC58NG84E5

2/139 DS11758 Rev 6

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 14

DS11758 Rev 6 3/139

4.12.2 SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 50

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4/139 DS11758 Rev 6

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

DS11758 Rev 6 5/139

6/139 DS11758 Rev 6

The SPC584Gx, SPC58EGx, SPC58NGx microcontroller belongs to a family of devices

2.1 Device feature summary

Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary

DS11758 Rev 6 7/139

Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary (continued)

Core MPU: 24 per CPU

8/139 DS11758 Rev 6

Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary (continued)

External power supplies 3.3 V - 5 V

DS11758 Rev 6 9/139

2.2 Block diagram

Figure 1. Block diagram

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10/139 DS11758 Rev 6

Figure 2. Periphery allocation

DS11758 Rev 6 11/139

12/139 DS11758 Rev 6

• Body cross triggering unit (BCTU)

DS11758 Rev 6 13/139

3 Package pinouts and signal descriptions

Refer to the SPC584Gx, SPC58EGx, SPC58NGx IO_ Definition document.

14/139 DS11758 Rev 6

Table 3. Parameter classifications

DS11758 Rev 6 15/139

4.2 Absolute maximum ratings

Table 4. Absolute maximum ratings

16/139 DS11758 Rev 6

Table 4. Absolute maximum ratings (continued)

DS11758 Rev 6 17/139

18/139 DS11758 Rev 6

4.3 Operating conditions

Table 5. Operating conditions

VSS_HV_ADV- ADC ground

DS11758 Rev 6 19/139

Table 5. Operating conditions (continued)

20/139 DS11758 Rev 6

Table 6. PRAM wait states configuration

4.3.1 Power domains and power up/down sequencing

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