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Key Terms 299

Open file AL05 in the Applied Logic folder on the website. Run the simulation of the
valve-control logic using your Multisim software and observe the operation. Create
a new Multisim file, connect the temperature control logic, and run the simulation.

Putting Your Knowledge to Work

If the temperature of the syrup can never be more than 9°C below the specified value, can
the temperature control circuit be simplified? If so, how?

SUMMARY

s !.$ /2LOGICPRODUCESANOUTPUTEXPRESSIONIN3/0FORM
s !.$ /2 )NVERTLOGICPRODUCESACOMPLEMENTED3/0FORMWHICHISACTUALLYA0/3FORM
s 4HEOPERATIONALSYMBOLFOREXCLUSIVE /2IS !. An exclusive-OR expression can be stated in
two equivalent ways:

AB + AB = A ! B
s 4ODOANANALYSISOFALOGICCIRCUITSTARTWITHTHELOGICCIRCUITANDDEVELOPTHE"OOLEANOUTPUT
expression or the truth table or both.
s )MPLEMENTATIONOFALOGICCIRCUITISTHEPROCESSINWHICHYOUSTARTWITHTHE"OOLEANOUTPUT
expressions or the truth table and develop a logic circuit that produces the output function.
s !LL.!.$OR./2LOGICDIAGRAMSSHOULDBEDRAWNUSINGAPPROPRIATEDUALSYMBOLSSO
that bubble outputs are connected to bubble inputs and nonbubble outputs are connected to
nonbubble inputs.
s 7HENTWONEGATIONINDICATORSBUBBLES ARECONNECTEDTHEYEFFECTIVELYCANCELEACHOTHER
s !6($,COMPONENTISAPREDEFINEDLOGICFUNCTIONSTOREDFORUSETHROUGHOUTAPROGRAMORIN
other programs.
s !COMPONENTINSTANTIATIONISUSEDTOCALLFORACOMPONENTINAPROGRAM
s !6($,SIGNALEFFECTIVELYACTSASANINTERNALINTERCONNECTIONINA6($,STRUCTURALDESCRIPTION

KEY TERMS

Key terms and other bold terms in the chapter are defined in the end-of-book glossary.
Component A VHDL feature that can be used to predefine a logic function for multiple use
throughout a program or programs.
Negative-AND The dual operation of a NOR gate when the inputs are active-LOW.
Negative-OR The dual operation of a NAND gate when the inputs are active-LOW.
Node A common connection point in a circuit in which a gate output is connected to one or more
gate inputs.
Signal A waveform; a type of VHDL object that holds data.
Signal tracing A troubleshooting technique in which waveforms are observed in a step-by-step
manner beginning at the input and working toward the output or vice versa. At each point the
observed waveform is compared with the correct signal for that point.
Universal gate Either a NAND gate or a NOR gate. The term universal refers to the property of
a gate that permits any logic function to be implemented by that gate or by a combination of that
kind.
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300 Combinational Logic Analysis

TRUE/FALSE QUIZ

Answers are at the end of the chapter.

1. AND-OR logic can have only two 2-input AND gates.
2. AOI is an acronym for AND-OR-Invert.
3. If the inputs of an exclusive-OR gate are the same, the output is LOW (0).
4. If the inputs of an exclusive-NOR gate are different, the output is HIGH (1).
5. A parity generator cannot be implemented using exclusive-OR gates.
6. NAND gates can be used to produce the AND functions.
7. NOR gates cannot be used to produce the OR functions.
8. Any SOP expression can be implemented using only NAND gates.
9. The dual symbol for a NAND gate is a negative-AND symbol.
10. Negative-OR is equivalent to NAND.

SELF-TEST

Answers are at the end of the chapter.

1. The output expression for an AND-OR circuit having one AND gate with inputs A, B and C
and one AND gate with inputs D, E and F is
(a) ABCDEF (b) A + B + C + D + E + F
(c) ABC + DEF (d) (A + B + C )(D + E + F )
2. A logic circuit with an output X = AB + ABC consists of
(a) two AND gates and one OR gate
(b) two AND gates, one OR gate and an inverter
(c) two AND gates, two OR gates and two inverters
(d) two AND gates, one OR gate and three inverters
3. To implement the expression X Y Z + X Y Z + X Y Z + X YZ + X Y Z, it takes
(a) five AND gates, one OR gate, and eight inverters
(b) four AND gates, two OR gates, and six inverters
(c) five AND gates, three OR gates, and seven inverters
(d) five AND gates, one OR gate, and seven inverters
4. The expression ABCD + ABCD + AB CD
(a) cannot be simplified (b) can be simplified to ABC + AB
(c) can be simplified to ABCD + ABC (d) None of these answers is correct.
5. The output expression for an AND-OR-Invert circuit having one AND gate with inputs A, B, C
and another AND gate with inputs D, E, F is
(a) ABC 1 DEF (b) (A + B + C )(D + E + F )
(c) (A + B + C )(D + E + F ) (d) A + B + C + D + E + F
6. An exclusive-NOR function is expressed as
(a) A B + AB (b) AB + AB
(c) (A + B)(A + B) (d) (A + B)(A + B)
7. The AND operation can be produced with
(a) two NAND gates (b) three NAND gates
(c) one NOR gate (d) three NOR gates
8. The OR operation can be produced with
(a) two NOR gates (b) three NAND gates
(c) four NAND gates (d) both answers (a) and (b)
9. When using dual symbols in a logic diagram,
(a) bubble outputs are connected to bubble inputs
(b) the NAND symbols produce the AND operations
(c) the negative-OR symbols produce the OR operations
(d) All of these answers are true.
(e) None of these answers is true.
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Problems 301

10. All Boolean expressions can be implemented with

(a) NAND gates only
(b) NOR gates only
(c) combinations of NAND and NOR gates
(d) combinations of AND gates, OR gates, and inverters
(e) any of these
11. A VHDL component
(a) can be used once in each program
(b) is a predefined description of a logic function
(c) can be used multiple times in a program
(d) is part of a data flow description
(e) answers (b) and (c)
12. A VHDL component is called for use in a program by using a
(a) signal (b) variable
(c) component instantiation (d) architecture declaration

PROBLEMS
Answers to odd-numbered problems are at the end of the book.

Section 5–1 Basic Combinational Logic Circuits

1. Draw the ANSI distinctive shape logic diagram for a 4-wide, 3-input AND-OR-Invert circuit.
Also draw the ANSI standard rectangular outline symbol.
2. Write the output expression for each circuit in Figure 5–54.

A
B
A
C X
B X

D
C
(a) (b)

FIGURE 5–54
fg05_05400
3. Write the output expression for each circuit as it appears in Figure 5–55.

A A A
X
B B
X X B
(a) (b) (c)

A
A B
A B
X
B
X X
C
C
(d) (e) (f)

FIGURE 5–55
fg05_05500
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302 Combinational Logic Analysis

4. Write the output expression for each circuit as it appears in Figure 5–56 and then change each
circuit to an equivalent AND-OR configuration.
5. Develop the truth table for each circuit in Figure 5–55.
6. Develop the truth table for each circuit in Figure 5–56.
7. Show that an exclusive-NOR circuit produces a POS output.

A
A
B
B
X C X
C
D D
(a) (b)

A A

B
B X
C X
D C
E D
(c) (d)

A
B
A
C
B
D
X X
C E
D F
E G
(e)
H
(f)

FIGURE 5–56
fg05_05600

Section 5–2 Implementing Combinational Logic

8. Develop an AND-OR-Invert logic circuit for a power drive which switches on (logic 1) when
the guard is in place (logic 1) and switches off (logic 0) when the motor is too hot (logic 0).
9. An AOI (AND-OR-Invert) logic chip has two 4-input AND gates connected to a 2-input NOR
gate. Write the Boolean expression for the circuit (assume the inputs are labeled A through H).
10. Use AND gates, OR gates, or combinations of both to implement the following logic
expressions as stated:
(a) X = A + B + C
(b) X = ABC
(c) X = A + BC
(d) X = AB + CD
(e) X = (A + B)(C + D)
(f) X = A + BCD
(g) X = ABC + BCD + DEF
(h) X = ABC(D + E + F) + AC(C + D + E)
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Problems 303

11. Use AND gates, OR gates, and inverters as needed to implement the following logic expres-
sions as stated:
(a) X = AB + BC
(b) X = A(B + C)
(c) X = AB + AB
(d) X = ABC + B(EF + G)
(e) X = A[BC(A + B + C + D)]
(f) X = B(CDE + EFG)(AB + C)
12. Use NAND gates, NOR gates, or combinations of both to implement the following logic
expressions as stated:
(a) X = AB + CD + (A + B)(ACD + BE)
(b) X = ABC D + DEF + AF
(c) X = A[B + C(D + E)]
13. Implement a logic circuit for the truth table in Table 5–8.

TABLE 5–8

Inputs Output
A B C X

0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

14. Implement a logic circuit for the truth table in Table 5–9.

TABLE 5–9
Inputs Output
A B C D X

0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
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304 Combinational Logic Analysis

15. Simplify the circuit in Figure 5–57 as much as possible, and verify that the simplified circuit is
equivalent to the original by showing that the truth tables are identical.
16. Repeat Problem 15 for the circuit in Figure 5–58.

A A

B B

C X
C
FIGURE 5–57 FIGURE 5–58
fg05_05700 fg05_05800
17. Minimize the gates required to implement the functions in each part of Problem 11 in SOP form.
18. Minimize the gates required to implement the functions in each part of Problem 12 in SOP
form.
19. Minimize the gates required to implement the function of the circuit in each part of Figure
5–56 in SOP form.

Section 5–3 The Universal Property of NAND and NOR Gates

20. Implement the logic circuits in Figure 5–54 using only NAND gates.
21. Implement the logic circuit in Figure 5–58 using only NAND gates.
22. Repeat Problem 20 using only NOR gates.
23. Repeat Problem 21 using only NOR gates.

Section 5–4 Combinational Logic Using NAND and NOR Gates

24. Show how the following expressions can be implemented as stated using only NOR gates:
(a) X = ABC (b) X = ABC (c) X = A + B
(d) X = A + B + C (e) X = AB + CD (f) X = (A + B)(C + D)
(g) X = AB[C(DE + AB) + BCE]
25. Repeat Problem 24 using only NAND gates.
26. Implement each function in Problem 10 by using only NAND gates.
27. Implement each function in Problem 11 by using only NAND gates.

Section 5–5 Pulse Waveform Operation

28. The output of the logic circuit and input waveforms in Figure 5–59 is passed through an
inverter. Draw the output waveform.

A
A
B X
B

FIGURE 5–59
fg05_05900
29. For the logic circuit in Figure 5–60, draw the output waveform in proper relationship to the
inputs.

A
A
B X
B

FIGURE 5–60
fg05_06000
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Problems 305

30. For the input waveforms in Figure 5–61, what logic circuit will generate the output waveform
shown?

Inputs B

Output X

FIGURE 5–61
fg05_06100
31. Repeat Problem 30 for the waveforms in Figure 5–62.

Inputs B

Output X

FIGURE 5–62
fg05_06200
32. For the circuit in Figure 5–63, draw the waveforms at the numbered points in the proper rela-
tionship to each other.

A A 1
B B 3
C C 4
D D 5
2 X
E E
F F

FIGURE 5–63
fg05_06300
33. Assuming a propagation delay through each gate of 10 nanoseconds (ns), determine if the
desired output waveform X in Figure 5–64 (a pulse with a minimum tW 5 25 ns positioned as
shown) will be generated properly with the given inputs.

A A
G1
B B
G2
C C
100 ns pulse width G3
D D
G4 X
E E

X
25 ns minimum
FIGURE 5–64
fg05_06400
Section 5–6 Combinational Logic with VHDL
34. Describe a 2-input NAND gate with VHDL.
35. Describe a 3-input AND gate with VHDL.
36. Write a VHDL program using the data flow approach (Boolean expressions) to describe the
logic circuit in Figure 5–54(b).
37. Write VHDL programs using the data flow approach (Boolean expressions) for the logic
circuits in Figure 5–55(e) and (f).
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306 Combinational Logic Analysis

38. Write a VHDL program using the structural approach for the logic circuit in Figure 5–56(d).
Assume component declarations for each type of gate are already available.
39. Repeat Problem 38 for the logic circuit in Figure 5–56(f).
40. Describe the logic represented by the truth table in Table 5–8 using VHDL by first converting it
to SOP form.
41. Develop a VHDL program for the logic in Figure 5–65, using both the data flow and the struc-
tural approach. Compare the resulting programs.

A
G1
B
G2
C G4 X
D
G3
E

FIGURE 5–65

42. Develop a VHDL program for the logic in Figure 5–66, using both the data flow and the struc-
tural approach. Compare the resulting programs.

A
B G3
G2
C G1 X
G4
G5
D
E

FIGURE 5–66

43. Given the following VHDL program, create the truth table that describes the logic circuit.
entity CombLogic is
port (A, B, C, D: in bit; X: out bit);
end entity CombLogic;
architecture Example of CombLogic is
begin
X ,5 not((not A and not B) or (not A and not C) or (not A and not D) or
(not B and not C) or (not B and not D) or (not D and not C));
end architecture Example;
44. Describe the logic circuit shown in Figure 5–67 with a VHDL program, using the data flow
approach.
45. Repeat Problem 44 using the structural approach.

A1
G1

A2
G2
G6
G5 X
B1
G3

B2
G7 G4

FIGURE 5–67
fg05_07200
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Problems 307

Section 5–7 Troubleshooting

46. For the logic circuit and the input waveforms in Figure 5–68, the indicated output waveform is
observed. Determine if this is the correct output waveform.

A A
B B

C C

D D

FIGURE 5–68
fg05_06500
47. The output waveform in Figure 5–69 is incorrect for the inputs that are applied to the circuit.
Assuming that one gate in the circuit has failed, with its output either an apparent constant HIGH
or a constant LOW, determine the faulty gate and the type of failure (output open or shorted).

A
A G1
B
B G2
C G4
C D
D G3
E
E

FIGURE 5–69
fg05_06600
48. Repeat Problem 47 for the circuit in Figure 5–70, with input and output waveforms as shown.

A
A G1
B
B

C
C G2 G4 X
D
D

E E
G3
F F

FIGURE 5–70
fg05_06700
49. By examining the connections in Figure 5–71, determine the driving gate and load gate(s).
Specify by device and pin numbers.

1 74HC00 2 74HC00

FIGURE 5–71
fg05_06800
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308 Combinational Logic Analysis

50. Figure 5–72(a) is a logic circuit under test. Figure 5–72(b) shows the waveforms as observed
on a logic analyzer. The output waveform is incorrect for the inputs that are applied to the cir-
cuit. Assuming that one gate in the circuit has failed, with its output either an apparent constant
HIGH or a constant LOW, determine the faulty gate and the type of failure.

A
B

C
A
G1
B D
C G2 G4 X E
D
E F
G3
F
X

(a) (b)

FIGURE 5–72
fg05_06900
51. The logic circuit in Figure 5–73 has the input waveforms shown.
(a) Determine the correct output waveform in relation to the inputs.
(b) Determine the output waveform if the output of gate G3 is open.
(c) Determine the output waveform if the upper input to gate G5 is shorted to ground.

A A
B G3
B G2
C G1 X
C
G4
G5
D D
E E

FIGURE 5–73
fg05_07000
52. The logic circuit in Figure 5–74 has only one intermediate test point available besides the output,
as indicated. For the inputs shown, you observe the indicated waveform at the test point. Is this
waveform correct? If not, what are the possible faults that would cause it to appear as it does?

A TP

B
A
C B
D
C
E
D X
F
E
TP F

FIGURE 5–74
fg05_07100
Applied Logic
53. Describe the function of each of the three sensors in the tank.
54. Implement the inlet valve logic using NOR gates and inverters.
55. Repeat Problem 54 for the outlet valve logic.
56. Implement the temperature control logic using XNOR gates.
57. Design a circuit to enable an additive to be introduced into the syrup through another inlet only
when the temperature is at the specified value and the syrup level is at the low-level sensor.
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Answers 309

Special Design Problems

58. (a) Design a logic circuit to produce a HIGH output only if the input, represented by a 4-bit
binary number, is greater than twelve or less than three. First develop the truth table and
then draw the logic diagram.
(b) Describe the logic using VHDL.
59. (a) Develop the logic circuit necessary to meet the following requirements:
A battery-powered lamp in a room is to be operated from two switches, one at the back
door and one at the front door. The lamp is to be on if the front switch is on and the back
switch is off, or if the front switch is off and the back switch is on. The lamp is to be off if
both switches are off or if both switches are on. Let a HIGH output represent the on condi-
tion and a LOW output represent the off condition.
(b) Describe the logic using VHDL.
60. (a) Develop the NAND logic for a hexadecimal keypad encoder that will convert each key
closure to binary.
(b) Describe the logic using VHDL.

Multisim Troubleshooting Practice

61. Open file P05-61. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
62. Open file P05-62. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
63. Open file P05-63. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.
64. Open file P05-64. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.

ANSWERS
SECTION CHECKUPS
Section 5–1 Basic Combinational Logic Circuits
1. (a) AB + CD = 1 # 0 + 1 # 0 = 1 (b) AB + CD = 1 # 1 + 0 # 1 = 0
(c) AB + CD = 0 # 1 + 1 # 1 = 0
2. (a) AB + AB = 1 # 0 + 1 # 0 = 1 (b) AB + AB = 1 # 1 + 1 # 1 = 0
(c) AB + AB = 0 # 1 + 0 # 1 = 1 (d) AB + AB = 0 # 0 + 0 # 0 = 0
3. X = 1 when ABC = 000, 011, 101, 110, and 111; X = 0 when ABC = 001, 010, and 100
4. X = AB + A B; the circuit consists of two AND gates, one OR gate, and two inverters. See
Figure 5–6(b) for diagram.

Section 5–2 Implementing Combinational Logic

1. (a) X = ABC + AB + AC: three AND gates, one OR gate
(b) X = AB(C + DE): three AND gates, one OR gate
2. X = ABC + A B C; two AND gates, one OR gate, and three inverters
3. (a) X = AB(C + 1) + AC = AB + AC
(b) X = AB(C + DE) = ABC + ABDE

Section 5–3 The Universal Property of NAND and NOR Gates

1. (a) X = A + B: a 2-input NAND gate with A and B on its inputs.
(b) X = AB: a 2-input NAND with A and B on its inputs, followed by one NAND used as an
inverter.
2. (a) X = A + B: a 2-input NOR with inputs A and B, followed by one NOR used as an
inverter.
(b) X = AB: a 2-input NOR with A and B on its inputs.
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310 Combinational Logic Analysis

Section 5–4 Combinational Logic Using NAND and NOR Gates

1. X = (A + B + C)DE: a 3-input NAND with inputs, A, B, and C, with its output connected to
a second 3-input NAND with two other inputs, D and E
2. X = A B C + (D + E): a 3-input NOR with inputs A, B, and C, with its output connected to a
second 3-input NOR with two other inputs, D and E

Section 5–5 Pulse Waveform Operation

1. The exclusive-OR output is a 15 ms pulse followed by a 25 ms pulse, with a separation of 10 ms
between the pulses.
2. The output of the exclusive-NOR is HIGH when both inputs are HIGH or when both inputs are
LOW.

Section 5–6 Combinational Logic with VHDL

1. A VHDL component is a predefined program describing a specified logic function.
2. A component instantiation is used to call for a specified component in a program architecture.
3. Interconnections between components are made using VHDL signals.
4. Components are used in the structural approach.

Section 5–7 Troubleshooting

1. Common gate failures are input or output open; input or output shorted to ground.
2. Input shorted to VCC causes output to be stuck LOW.
3. (a) G4 output is HIGH until rising edge of seventh pulse, then it goes LOW.
(b) G4 output is the same as input D.
(c) G4 output is the inverse of the G2 output shown in Figure 5–49(b).

RELATED PROBLEMS FOR EXAMPLES

5–1 X = AB + AC + BC
5–2 X = AB + AC + BC
If A = 0 and B = 0, X = 0 # 0 + 0 # 1 + 0 # 1 = 0 = 1
If A = 0 and C = 0, X = 0 # 1 + 0 # 0 + 1 # 0 = 0 = 1
If B = 0 and C = 0, X = 1 # 0 + 1 # 0 + 0 # 0 = 0 = 1
5–3 Determine the even-parity output for all 16 input combinations. Each combination should
have an even number of 1s including the parity bit.
5–4 Apply codes with odd number of 1s and verify output is 1.
5–5 Cannot be simplified
5–6 Cannot be simplified
5–7 X = A + B + C + D is valid.
5–8 See Figure 5–75.

A
B
X = C (A + B)(B + D)

D
C
FIGURE 5–75

fg05_07300
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Answers 311

5–9 X = (ABC)(DEF) = (AB)C + (DE)F = (A + B)C + (D + E)F

5–10 See Figure 5–76.

A
A B
B C
C
ABC + DE D ABC + D + E
D
E
E

(a) (b)
FIGURE 5–76
fg05_07400

5–11 X = (A + B + C) + (D + E + F) = (A + B + C)(D + E + F) = (A B + C)(D E + F)

5–12 See Figure 5–77.
5–13 See Figure 5–78.

AHIGH A

B B
C
X X

FIGURE 5–77 FIGURE 5–78

fg05_07500 fg05_07600
5–14 See Figure 5–79.
5–15 See Figure 5–80.

B
C
D
Y1 A
Y2 B
Y3 C
Y4 D
X X

FIGURE 5–79 FIGURE 5–80

fg05_07700 fg05_07800
5–16 G5: NAND_gate2 port map (A 5. IN9, B 5. IN10, X 5. OUT5);
5–17 See Figure 5–81.

A
B
C
D
G4
FIGURE 5–81
fg05_07900
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312 Combinational Logic Analysis

TRUE/FALSE QUIZ
1. F 2. T 3. T 4. F 5. F
6. T 7. F 8. T 9. F 10. T

SELF-TEST
1. (c) 2. (d) 3. (a) 4. (a) 5. (c) 6. (a) 7. (a) 8. (d)
9. (d) 10. (e) 11. (e) 12. (c)