Esp32 c3
Esp32 c3
Esp32 c3
Datasheet
Including:
ESP32-C3
ESP32-C3FN4
ESP32-C3FH4
Version 1.1
Espressif Systems
Copyright © 2021
www.espressif.com
Product Overview
ESP32-C3 series of SoCs is an ultra-low-power and highly-integrated MCU-based solution that supports 2.4
GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The block diagram of ESP32-C3 is shown below.
Transmitter
Microprocessor
Receiver
2.4 GHz
2.4 GHz
2.4 GHz
Clock
Bluetooth LE
Cache SRAM Link Controller
Bluetooth LE
JTAG ROM RF Phase Lock Loop
Baseband
Peripherals RTC
RTC
SPI0/1 I2C GPIO RTC GPIO PMU
Memory
SPI2
⚙ I2S UART RTC Security
Watchdog
Timer ⚙ ⚙
TWAI® Pulse Counter RMT SHA RSA
GDMA
⚙ LCD DIG ADC Temperature
AES
⚙ RNG
Interface Controller Sensor
LED PWM
USB Serial/ Camera Watchdog
HMAC
⚙ Digital ⚙
JTAG Interface Timers Signature
Secure ⚙ Flash
General-purpose Timers System Timers Encryption
Boot
Solution Highlights
• A complete WiFi subsystem that complies • Storage capacities ensured by 400 KB of
with IEEE 802.11b/g/n protocol and supports SRAM (16 KB for cache) and 384 KB of ROM on
Station mode, SoftAP mode, SoftAP + Station the chip, and SPI, Dual SPI, Quad SPI, and QPI
mode, and promiscuous mode interfaces that allow connection to external flash
Features
WiFi CPU and Memory
• 1T1R mode with data rate up to 150 Mbps – 1 core at 160 MHz: 407.22 CoreMark; 2.55
CoreMark/MHz
• Wi-Fi Multimedia (WMM)
• 384 KB ROM
• TX/RX A-MPDU, TX/RX A-MSDU
• 400 KB SRAM (16 KB for cache)
• Immediate Block ACK
• 8 KB SRAM in RTC
• Fragmentation and defragmentation
• Embedded flash (see details in Chapter 1
• Transmit opportunity (TXOP)
ESP32-C3 Series Comparison)
• Automatic Beacon monitoring (hardware TSF)
• SPI, Dual SPI, Quad SPI, and QPI interfaces that
• 4 × virtual Wi-Fi interfaces allow connection to multiple external flash
• Simultaneous support for Infrastructure BSS in • Access to flash accelerated by cache
Station mode, SoftAP mode, Station + SoftAP
• Supports flash in-Circuit Programming (ICP)
mode, and promiscuous mode
Note that when ESP32-C3 scans in Station mode,
the SoftAP channel will change along with the Advanced Peripheral Interfaces
Station channel
• 22 × programmable GPIOs
• Antenna diversity
• Digital interfaces:
• 802.11mc FTM
– 3 × SPI
• Supports external power amplifier
– 2 × UART
– 1 × I2C
Bluetooth – 1 × I2S
• RSA Accelerator
Low Power Management
• Random Number Generator (RNG)
• Power Management Unit with four power modes
• HMAC
• Secure boot
Contents
Product Overview 2
Solution Highlights 2
Features 3
Applications 4
2 Pin Definition 10
2.1 Pin Layout 10
2.2 Pin Description 10
2.3 Power Scheme 12
2.4 Strapping Pins 13
3 Functional Description 16
3.1 CPU and Memory 16
3.1.1 CPU 16
3.1.2 Internal Memory 16
3.1.3 External Flash 16
3.1.4 Address Mapping Structure 17
3.1.5 Cache 17
3.2 System Clocks 18
3.2.1 CPU Clock 18
3.2.2 RTC Clock 18
3.3 Analog Peripherals 18
3.3.1 Analog-to-Digital Converter (ADC) 18
3.3.2 Temperature Sensor 18
3.4 Digital Peripherals 18
3.4.1 General Purpose Input / Output Interface (GPIO) 18
3.4.2 Serial Peripheral Interface (SPI) 20
3.4.3 Universal Asynchronous Receiver Transmitter (UART) 21
3.4.4 I2C Interface 21
3.4.5 I2S Interface 22
3.4.6 Remote Control Peripheral 22
3.4.7 LED PWM Controller 22
3.4.8 General DMA Controller 22
3.4.9 USB Serial/JTAG Controller 22
®
3.4.10 TWAI Controller 22
3.5 Radio and Wi-Fi 23
3.5.1 2.4 GHz Receiver 23
3.5.2 2.4 GHz Transmitter 23
3.5.3 Clock Generator 24
4 Electrical Characteristics 30
4.1 Absolute Maximum Ratings 30
4.2 Recommended Operating Conditions 30
4.3 VDD_SPI Output Characteristics 30
4.4 DC Characteristics (3.3 V, 25 °C) 31
4.5 ADC Characteristics 31
4.6 Current Consumption 32
4.7 Reliability 32
4.8 Wi-Fi Radio 33
4.8.1 Wi-Fi RF Transmitter (TX) Specifications 33
4.8.2 Wi-Fi RF Receiver (RX) Specifications 34
4.9 Bluetooth LE Radio 35
4.9.1 Bluetooth LE RF Transmitter (TX) Specifications 36
4.9.2 Bluetooth LE RF Receiver (RX) Specifications 37
5 Package Information 40
Revision History 42
List of Tables
1 ESP32-C3 Series Comparison 9
2 Pin Description 10
3 Description of ESP32-C3 Power-up and Reset Timing Parameters 13
4 Strapping Pins 14
5 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 15
6 IO MUX Pin Functions 19
7 Power-Up Glitches on Pins 20
8 Mapping of SPI Signals and Chip Pads 21
9 Connection Between ESP32-C3 and External Flash 21
10 Peripheral Pin Configurations 27
11 Absolute Maximum Ratings 30
12 Recommended Operating Conditions 30
13 VDD_SPI Output Characteristics 30
14 DC Characteristics (3.3 V, 25 °C) 31
15 ADC Characteristics 31
16 Current Consumption Depending on RF Modes 32
17 Current Consumption Depending on Work Modes 32
18 Reliability Qualifications 32
19 Wi-Fi Frequency 33
20 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 33
21 TX EVM Test 34
22 RX Sensitivity 34
23 Maximum RX Level 35
24 RX Adjacent Channel Rejection 35
25 Bluetooth LE Frequency 35
26 Transmitter Characteristics - Bluetooth LE 1 Mbps 36
27 Transmitter Characteristics - Bluetooth LE 2 Mbps 36
28 Transmitter Characteristics - Bluetooth LE 125 Kbps 36
29 Transmitter Characteristics - Bluetooth LE 500 Kbps 37
30 Receiver Characteristics - Bluetooth LE 1 Mbps 37
31 Receiver Characteristics - Bluetooth LE 2 Mbps 38
32 Receiver Characteristics - Bluetooth LE 125 Kbps 38
33 Receiver Characteristics - Bluetooth LE 500 Kbps 39
List of Figures
1 Block Diagram of ESP32-C3 2
2 ESP32-C3 Series Nomenclature 9
3 ESP32-C3 Pin Layout (Top View) 10
4 ESP32-C3 Power Scheme 12
5 ESP32-C3 Power-up and Reset Timing 13
6 Setup and Hold Times for the Strapping Pins 14
7 Address Mapping Structure 17
8 QFN32 (5×5 mm) Package 40
ESP32-C3 F H x
Flash
Flash temperature
H: High temperature
N: Normal temperature
Embedded flash
Chip series
1.2 Comparison
Table 1: ESP32C3 Series Comparison
2. Pin Definition
2.1 Pin Layout
26 GPIO19
25 GPIO18
29 XTAL_N
30 XTAL_P
27 U0RXD
28 U0TXD
32 VDDA
31 VDDA
LNA_IN 1 24 SPIQ
VDD3P3 2 23 SPID
VDD3P3 3 22 SPICLK
XTAL_32K_P 4 21 SPICS0
XTAL_32K_N 5 20 SPIWP
GPIO2 6
ESP32-C3 19 SPIHD
CHIP_EN 7 18 VDD_SPI
VDD3P3_RTC 11
MTCK 12
MTDO 13
GPIO8 14
GPIO9 15
GPIO10 16
9
MTMS
• VDDA1
• VDDA2
• VDD3P3_RTC
• VDD3P3_CPU
• VDD_SPI
VDDA1 and VDDA2 are the input power supply for the analog domain.
When working as an output power supply, VDD_SPI can be powered by VDD3P3_CPU via RSP I (nominal 3.3 V).
VDD_SPI can be powered off via software to minimize the current leakage of flash in Deep-sleep mode.
The RTC domain is powered from Low Power Voltage Regulator, which is powered from VDD3P3_RTC.
The Digital System domain is powered from Digital System Voltage Regulator, which is powered from
VDD3P3_CPU and VDD3P3_RTC at the same time.
Notes on CHIP_EN:
Figure 5 shows the power-up and reset timing of ESP32-C3. Details about the parameters are listed in Table
3.
t0 t1
2.8 V
VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU
VIL_nRST
CHIP_EN
Min
Parameter Description (µs)
Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, and
t0 50
VDD3P3_CPU rails, and activating CHIP_EN
Duration of CHIP_EN signal level < VIL_nRST (refer to its value in
t1 50
Table 14) to reset the chip
• GPIO2
• GPIO8
• GPIO9
Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference Manual.
During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down.
• power-on reset
• brownout reset
By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to
an external high-impedance circuit, the latched bit value will be ”1”
To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-C3.
Booting Mode 1
Pin Default SPI Boot Download Boot
GPIO2 N/A 1 1
GPIO8 N/A Don’t care 1
Internal weak
GPIO9 1 0
pull-up
Enabling/Disabling ROM Messages Print During Booting
Pin Default Functionality
When the value of eFuse field EFUSE_UART_PRINT_CONTROL is
0 (default), print is enabled and not controlled by GPIO8.
GPIO8 N/A 1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled.
2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled.
3, print is disabled and not controlled by GPIO8.
1
The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected be-
havior.
Figure 6 shows the setup and hold times for the strapping pins before and after the CHIP_EN signal goes high.
Details about the parameters are listed in Table 5.
t0 t1
VIL_nRST
CHIP_EN
VIH
Strapping pin
Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pins
Min
Parameter Description (ms)
t0 Setup time before CHIP_EN goes from low to high 0
t1 Hold time after CHIP_EN goes high 3
3. Functional Description
This chapter describes the functions of ESP32-C3.
• RV32IMC ISA
• up to 8 hardware breakpoints/watchpoints
• up to 16 PMP regions
• 400 KB of onchip SRAM: for data and instructions, running at a configurable frequency of up to 160
MHz. Of the 400 KB SRAM, 16 KB is configured for cache.
• RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in
Deep-sleep mode.
• 4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID.
CPU’s instruction memory space and read-only data memory space can map into external flash of ESP32-C3,
whose size can be 16 MB at most. ESP32-C3 supports hardware encryption/decryption based on XTS-AES to
protect developers’ programs and data in flash.
• 8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.
• 8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and
32-bit reads are supported.
Note:
After ESP32-C3 is initialized, software can customize the mapping of external flash into the CPU address space.
Note:
The memory space with gray background is not available for use.
3.1.5 Cache
ESP32-C3 has an eight-way set associative cache. This cache is read-only and has the following features:
• size: 16 KB
• pre-load function
• lock function
• PLL clock
The application can select the clock source from the three clocks above. The selected clock source drives the
CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock
source would be the external main crystal clock divided by 2.
• internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256)
The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:
• internal fast RC oscillator divide-by-N clock (typically about 17.5 MHz, and adjustable)
The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O
load. Generally, the chip’s internal temperature is higher than the operating ambient temperature.
All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are
configured as an input, the input value can be read by software through the register. Input GPIOs can also be set
to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting
and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other
functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state.
The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide
highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while
peripheral output signals can be configured to any IO pins. Table 6 shows the IO MUX functions of each pin. For
more information about IO MUX and GPIO matrix, please refer to Chapter IO MUX and GPIO Matrix (GPIO,
IO_MUX) in ESP32-C3 Technical Reference Manual.
Reset
• 0* - input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1). See details in Notes
We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power
consumption. You may add pull-up and pull-down resistors in your PCB design referring to Table 14, or enable
internal pull-up and pull-down resistors during software initialization.
Notes
• USB - GPIO18 and GPIO19 are USB pins. The pull-up value of a USB pin is controlled by the pin’s pull-up
value together with USB pull-up value. If any of the two pull-up values is 1, the pin’s pull-up resistor will be
enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP bit.
In SPI memory mode, SPI0, SPI1 and SPI2 interface with external SPI memory. Data is transferred in bytes.
Up to four-line STR reads and writes are supported. The clock frequency is configurable to a maximum of
120 MHz in STR mode.
When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports
two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master
and slave modes. The host’s clock frequency is configurable. Data is transferred in bytes. The clock
polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA.
– In master mode, the clock frequency is 80 MHz at most, and the four modes of SPI transfer format are
supported.
– In slave mode, the clock frequency is 60 MHz at most, and the four modes of SPI transfer format are
also supported.
The mapping between SPI bus signals and GPIO pins is shown in Table 8:
In most cases, the data port connection between ESP32-C3 and external flash is as follows:
You can configure instruction registers to control the I2C interface for more flexibility.
The I2S interface supports TDM PCM, TDM MSB alignment, TDM standard, and PDM TX interface. It connects
to the GDMA controller.
• can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be
up to 18 bits.
• has multiple clock sources, including APB clock and external main crystal clock.
• supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient
generator.
The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and
memory-to-memory data transfer at a high speed. All channels can access internal RAM.
Peripherals on ESP32-C3 with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC.
• USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not
support the faster 480 Mbit/s high-speed transfer mode)
• standard frame format (11-bit ID) and extended frame format (29-bit ID)
• multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)
• error detection and handling: error counters, configurable error interrupt threshold, error code capture,
arbitration lost capture
• clock generator
Additional calibrations are integrated to cancel any radio imperfections, such as:
• carrier leakage
• baseband nonlinearities
• RF nonlinearities
• antenna matching
These built-in calibration routines reduce the cost, time, and specialized equipment required for product
testing.
The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are
optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the
transmitter.
• 802.11b/g/n
• 802.11n MCS32
• antenna diversity
ESP32-C3 supports antenna diversity with an external RF switch. This switch is controlled by one or more
GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.
ESP32-C3 Wi-Fi MAC applies the following low-level protocol functions automatically:
• infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode
• 802.11mc FTM
3.6 Bluetooth LE
ESP32-C3 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an
RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and
Bluetooth mesh.
• 1 Mbps PHY
• coded PHY for longer range (125 Kbps and 500 Kbps)
• LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data
• LE privacy 1.2
• LE Ping
• Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.
• Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band,
Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active.
• Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts)
will wake up the chip. Wi-Fi and Bluetooth LE connection can remain active.
• Deep-sleep mode: CPU and most peripherals are powered down. Only the RTC memory is powered on.
Wi-Fi connection data are stored in the RTC memory.
For power consumption in different power modes, please refer to Table 17.
3.8 Timers
3.8.1 General Purpose Timers
ESP32-C3 is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers and
54-bit auto-reload-capable up/down-timers.
During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order
to detect and recover from booting errors.
• four stages, each with a programmable timeout value. Each stage can be configured, enabled and
disabled separately
• interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or
system reset for RWDT upon expiry of each stage
• write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
• Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature)
can be booted.
• HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity
verification and other purposes.
• Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity
verification.
• World Controller provides two running environments for software. All hardware and software resources are
sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed
by hardware in the general world, thus establishing a security boundary.
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the
device. These are stress ratings only, and do not refer to the functional operation of the device.
Note:
In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_CPU may be affected by RSP I . For
example, when VDD3P3_CPU is used to drive a 3.3 V flash, it should comply with the following specifications:
Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the maximum current.
1
To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value.
2
kSPS means kilo samples-per-second.
4.7 Reliability
Table 18: Reliability Qualifications
5. Package Information
Note:
• For the source file of recommended PCB land pattern (dxf), you can view it with Autodesk Viewer;
• For information about tape, reel, and product marking, please refer to Espressif Chip-Packing Information.
Developer Zone
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Revision History
Date Version Release Notes
Authorized Distributor
Espressif:
ESP32-C3-DevKitM-1 ESP32-C3-DevKitC-02 ESP32-C3 ESP32-C3FH4 ESP32-C3FN4