Module 3

Processor Structure and Function

 CPU Structure
• CPU must:
– Fetch instructions
– Interpret instructions
– Fetch data
– Process data
– Write data
 Remember….
• The processor needs to store some data
temporally.
• It must remember the location of the last
instruction so that it can know where to get
the next instruction.
• It needs to store instructions and data
temporally while an instruction is being
executed.
CPU With System Bus
CPU Internal Structure
 Registers
• CPU must have some working space
(temporary storage)
• Called registers
• Number and function vary between processor
designs
• One of the major design decisions
• Top level of memory hierarchy
 How big?
• Large enough to hold full address
• Large enough to hold full word
• Often possible to combine two data registers
 How Many GP Registers?
• Between 8 - 32
• Fewer = more memory references
• More does not reduce memory references and
takes up processor real estate
 Register Organization

• User-visible registers: These enables the machine - or

assembly-language programmer to minimize main
memory reference by optimizing use of registers.

• Control and status registers: These are used by the

control unit to control the operation of the CPU.
Operating system programs may also use these in
privileged mode to control the execution of program.
 User Visible Registers

• General Purpose
• Data
• Address
• Condition Codes
 General Purpose Registers
 May be true general purpose
 can be assigned to a variety of functions by the programmer
 May be used for data or addressing
 Data
 used to hold only data and cannot be employed in the
calculation of an operand address.
 Addressing
 Segment pointers
 Index registers
 Stack Pointer
 Condition Code Registers
• Sets of individual bits
– e.g. result of last operation was zero
• Can be read (implicitly) by programs
– e.g. Jump if zero
• Can not (usually) be set by programs
 Program Status Word
• A set of bits Includes Condition Codes
• Sign of last result
• Zero
• Carry
• Equal
• Overflow
• Interrupt enable/disable
• Supervisor
 Supervisor Mode
• Kernel mode
• Allows privileged instructions to execute
• Used by operating system
• Not available to user programs
 Control & Status Registers
• Program Counter
• Instruction Decoding Register
• Memory Address Register
• Memory Buffer Register

• Revision: what do these all do?

Example Register Organizations
 Features of an ISA

 Example of instructions in an ISA

 Arithmetic instructions : add, sub, mul, div
 Logical instructions : and, or, not
 Data transfer/movement instructions
 Complete
 It should be able to implement all the
programs that users may write.

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 Features of an ISA – II

 Concise
 The instruction set should have a limited size.
Typically an ISA contains 32-1000 instructions.
 Generic
 Instructions should not be too specialized, e.g.
add14 (adds a number with 14) instruction is
too specialized
 Simple
 Should not be very complicated.
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 Designing an ISA
 Important questions that need to be
answered :
 How many instructions should we have ?
 What should they do ?
 How complicated should they be ?

Two different paradigms : RISC and CISC

RISC CISC
(Reduced Instruction Set (Complex Instruction
Computer) Set Computer)

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 RISC vs CISC
A reduced instruction set computer (RISC) implements
simple instructions that have a simple and regular
structure. The number of instructions is typically a small
number (64 to 128). Examples: ARM, IBM PowerPC,
HP PA-RISC

A complex instruction set computer (CISC) implements complex instructions

that are highly irregular, take multiple operands, and implement complex
functionalities. Secondly, the number of instructions is large (typically
500+). Examples: Intel x86, VAX

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 Completeness of an ISA

How can we ensure that an

ISA is complete ?

 Complete means :
 Can implement all types of programs
 For example, if we just have add instructions,
we cannot subtract (NOT Complete)

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 Completeness of an ISA – II

How to ensure that we have just enough

instructions such that we can implement every
possible program that we might want to write ?

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 Let us now design an ISA ...

 Single Instruction ISA

 sbn – subtract and branch if negative
 Add (a + b) (assume temp = 0)

1: sbn temp, b, 2
2: sbn a, temp, exit

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 Single Instruction ISA - II
 Add the numbers – 1 … 10
Initialization:
one = 1
index = 10
sum = 0

1: sbn temp, temp, 2 // temp = 0

2: sbn temp, index, 3 // temp = -1 * index
3: sbn sum, temp, 4 // sum += index
4: sbn index, one, exit // index -= 1
5: sbn temp, temp, 6 // temp = 0
6: sbn temp, one, 1 // (0 - 1 < 0), hence goto 1

exit

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 Multiple Instruction ISA
 Arithmetic Instructions
 add, subtract, multiply, divide

 Logical Instructions
 or, and, not

 Move instructions
 Transfer values between memory locations

 Branch instructions
 Move to a new program location, based on the values of some
memory locations

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 CISC RISC
• It consists of a large set of • It consists of small set of
instructions with variable instructions with fixed format
formats (Typically 16 to 64 bits and these instructions are of
per instruction) register based instructions.
• It has higher number of • It has a limited number of
addressing modes, typically 12 addressing modes, typically 3 to
to 24. 5.
• It consists of complex • It consists of simple instructions
instructions that take multiple that take single cycle to
cycles to execute execute.
• Instructions are not pipelined or • Instructions are pipelined
less pipelined • Complexity lies the compiler
• Complexity lies in microprogram
 Instruction Cycle
 Fetch
Read next instruction from memory into the processor
 Indirect Cycle (Decode Cycle)
May require memory access to fetch operands, therefore more
memory accesses.
 Interrupt
Save current instruction and service the interrupt
 Execute
Interpret the opcode and perform the indicated operation
 Indirect Cycle
• May require memory access to fetch operands
• Indirect addressing requires more memory
accesses
• Can be thought of as additional instruction
subcycle
Instruction Cycle with Indirect
Instruction Cycle State Diagram
 Data Flow (Instruction Fetch)
• Depends on CPU design
• In general:

• Fetch
– PC contains address of next instruction
– Address moved to MAR
– Address placed on address bus
– Control unit requests memory read
– Result placed on data bus, copied to MBR, then to IR
– Meanwhile PC incremented by 1
 Data Flow (Data Fetch)
• IR is examined
• If indirect addressing, indirect cycle is
performed
– Right most N bits of MBR transferred to MAR
– Control unit requests memory read
– Result (address of operand) moved to MBR
 Data Flow (Fetch Diagram)

PC MAR
Memory
Control
Unit

MBR
IR MBR
Data Flow (Indirect Diagram)

MAR
Memory
Memory
Control
Unit

MBR
MBR
 Data Flow (Execute)
• May take many forms
• Depends on instruction being executed
• May include
– Memory read/write
– Input/Output
– Register transfers
– ALU operations
 Data Flow (Interrupt)
• Simple
• Predictable
• Current PC saved to allow resumption after interrupt
• Contents of PC copied to MBR
• Special memory location (e.g. stack pointer) loaded to
MAR
• MBR written to memory
• PC loaded with address of interrupt handling routine
• Next instruction (first of interrupt handler) can be
fetched
 Data Flow (Interrupt Diagram)

PC
PC MAR
Memory
Control
Control
Unit
Unit

MBR
Control Unit Design
DESIGN ISSUES OF RISC PROCESSOR
 Characteristic of RISC
• Although a variety of different approaches to
reduce Instruction set architecture have been
taken, certain characteristics are common to
all of them:
– One instruction per cycle.
– Register–to–register operations.
– Simple addressing modes.
– Simple instruction formats.
 Characteristic of RISC cont.d
1. One machine instruction per machine cycle :
• A machine cycle is defined to be the time it takes to fetch two operands
from registers, perform an ALU operation, and store the result in a
register.
With simple, one-cycle instructions there is little or no need of microcode,
the machine instructions can be hardwired. Hardware implementation of
control unit executes faster than the microprogrammed control, because it
is not necessary to access a microprogram control store during instruction
execution.
• One Cycle Execution Time. RISC processors have a CPI (clock per
instruction) of one cycle. This is due to the optimization of each
instruction on the CPU
2. Register –to– register operations
• With register–to–register operation, a simple LOAD and STORE operation
is required to access the memory, because most of the operation are
register–to-register. Generally we do not have memory–to–memory and
mixed register/memory operation.
 Characteristic of RISC cont.d
3. Simple Addressing Modes
• Almost all RISC instructions use simple register addressing. For
memory access only, we may include some other addressing, such
as displacement and PC-relative. Once the data are fetched inside
the CPU, all instruction can be performed with simple register
addressing.
4. Simple Instruction Format
• Generally in most of the RISC machine, only one or few formats are
used. Instruction length is fixed and aligned on word boundaries.
Field locations, especially the opcode, are fixed.
With fixed fields, opcode decoding and register operand accessing
can occur simultaneously. Simplified formats simplify the control
unit.
 CISC
• Intel IA-32, belongs to the Complex Instruction
Set Computer (CISC) design.
• The obvious reason for this classification is the
“complex” nature of its Instruction Set
Architecture (ISA). The motivation for designing
such complex instruction sets is to provide an
instruction set that closely supports the
operations and data structures used by Higher-
Level Languages (HLLs).
• However, the side effects of this design effort are
far too serious to ignore.
 Addressing Modes in CISC
• The decision of CISC processor designers to
provide a variety of addressing modes leads to
variable-length instructions. For example,
instruction length increases if an operand is in
memory as opposed to in a register.
a) This is because we have to specify the memory
address as part of instruction encoding, which takes
many more bits.
b) This complicates instruction decoding and
scheduling. The side effect of providing a wide range
of instruction types is that the number of clocks
required to execute instructions varies widely.
c) This again leads to problems in instruction
scheduling and pipelining.
• Because CISC and RISC have their advantages
and disadvantages, modern processors take
features from both classes. For example, the
PowerPC, which follows the RISC philosophy,
has quite a few complex instructions.
 RISC Vs CISC: An Example
• Multiplying Two Numbers in Memory. The main
memory is divided into locations numbered from (row)
1: (column) 1 to (row) 6: (column) 4.
• The execution unit is responsible for carrying out all
computations.
• However, the execution unit can only operate on data
that has been loaded into one of the six registers (A, B,
C, D, E, or F).
• Let's say we want to find the product of two numbers -
one stored in location 2:3 and another stored in
location 5:2 - and then store the product back in the
location 2:3
• The CISC Approach. The primary goal of CISC
architecture is to complete a task in as few lines of
assembly as possible. This is achieved by building
processor hardware that is capable of understanding
and executing a series of operations.

• For this particular task, a CISC processor would come

prepared with a specific instruction (say "MUL").

– When executed, this instruction loads the two values into

separate registers, multiplies the operands in the
execution unit, and then stores the product in the
appropriate register.
– Thus, the entire task of multiplying two numbers can be
completed with one instruction:
MUL 2:3, 5:2
• MUL is what is known as a "complex instruction."
• It operates directly on the computer's memory
banks and does not require the programmer to
explicitly call any loading or storing functions.
• It closely resembles a command in a higher level
language.
• For instance, if we let "a" represent the value of
2:3 and "b" represent the value of 5:2, then this
command is identical to the C statement "a = a x
b."
• Advantage.
• One of the primary advantages of this system is
that the compiler has to do very little work to
translate a high-level language statement into
assembly.
• Because the length of the code is relatively short,
very little RAM is required to store instructions.
The emphasis is put on building complex
instructions directly into the hardware.
 The RISC Approach
• RISC processors only use simple instructions that
can be executed within one clock cycle.
• Thus, the "MUL" command described above
could be divided into three separate commands:
– "LOAD," which moves data from the memory bank to
a register,
– "PROD," which finds the product of two operands
located within the registers
– "STORE," which moves data from a register to the
memory banks.
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
 Analysis
• At first, this may seem like a much less efficient way of completing the
operation. Because there are more lines of code, more RAM is needed to
store the assembly level instructions.
• The compiler must also perform more work to convert a high-level
language statement into code of this form.
• Advantage of RISC. However, the RISC strategy also brings some very
important advantages. Because each instruction requires only one clock
cycle to execute, the entire program will execute in approximately the
same amount of time as the multi-cycle "MUL" command.
• These RISC "reduced instructions" require less transistors of hardware
space than the complex instructions, leaving more room for general
purpose registers.
• Because all of the instructions execute in a uniform amount of time (i.e.
one clock), pipelining is possible.
• (1) Separating the "LOAD" and "STORE" instructions actually reduces the
amount of work that the computer must perform.
• (2) After a CISC-style "MUL" command is executed, the processor
automatically erases the registers. If one of the operands needs to be used
for another computation, the processor must re-load the data from the
memory bank into a register.
• In RISC, the operand will remain in the register until another value is
loaded in its place.
 The Performance Equation
• The following equation is commonly used for
expressing a computer's performance ability:

– CISC Approach. The CISC approach attempts to

minimize the number of instructions per program,
sacrificing the number of cycles per instruction.
– RISC Approach. RISC does the opposite, reducing the
cycles per instruction at the cost of the number of
instructions per program.