e & = ef 2 SS ss EEE mm SoomorLrSaesegwgySS=—=—=—=—_—_———————_—X__"_-= Boolean Algebra and Logic Gates ee 2-1 BASIC DEFINITIONS Boolean algebra, like any other deductive mathematical system, may be defined with a set of elements, a set of operators, and a number of unproved axioms or postulates. A set of elements is any collection of objects having a common property. If Sisa set, and x and y are certain objects, then x € S denotes that xis a member of the set S, and y ¢ S denotes that y is not an element of S. A set with a denumerable number of elements is specified by braces: A = {1, 2, 3, 4}, ie., the elements of set A are the numbers 1, 2, 3, and 4. A binary operator defined on a set S of elements is a rule that assigns to each pair of elements from S a unique clement from S. As an example, consider the relation aeb = c. We say that « is a binary operator if it specifies a rule for finding ¢ from the pair (a, b) and also if a, 4, ¢ © S. However, + is not a binary operator if a, 6 © £, while the rule finds ces. The postulates of a mathematical system form the basic assumptions from which it is possible to deduce the rules, theorems, and properties of the system The most common postulates used to formulate various algebraic structures are: 1. Closure. A set S is closed with Tespect to a binary operator if, for every Pair of elements of S, the binary operator Specifies a rule for obtaining a unique element of S. For example, the set of natural numbers N = (1, 2, 3. 4,...) is closed with respect to the binary operator plus (+) by the ty Operator minus (—) by the rules of arithmetic subtracti “ subtraction because 2~3 = — | ang 23€EN, while (—1) @ x Associative law. A binar, : ? eae binary operator + on a set S is said to be associative (xey)oz = 02). forall x,y, > es : eS — Scanned with CamScannera BASIC DEFINITIONS 35, 3. Commutative law. A binary operator + on a set S is said to be commutativ} whenever: xay=yex forallx,y ES 4, Identity element. A set S is said to have an identity element with respect to a binary operation * on S if there exists an element e ES with the property: erx=xee=x — foreveryx ES Example: The element 0 is an identity element with respect to operation + on the set of integers I= {...,—3, -2, -1, 0, 1,2,3,-.. } since: x+0=0+x=x foranyxEl The set of natural numbers N has no identity element since 0 is excluded from the set. Inverse. A set S having the identity element e with respect to a binary operator + is said to have an inverse whenever, for every x € S, there exists an element y € S such that: a) xy =e Example: In the set of integers T with e = 0, the inverse of an element a is (a) since a + (—a) = 0. . Distributive law. If « and - are two binary operators on a set S, + is said to be distributive over - whenever: ry xe(y +2) = (xay): (x92) ‘An example of an algebraic structure is a field. A field is a set cs elements, together with two binary operators, each having properties 1 to 5 and both operators combined to give property 6. The set of real numbers ‘together with the binary operators + and « form the field of real numbers. “The field of teal numbers is the basis for arithmetic and ordinary algebra. “The operators and postulates have the following meanings: "The binary operator + defines addition. The binary operator - multiplicative identity is Scanned with CamScanner36 BOOLEAN ALGEBRA AND LOGIC GATES, : Waal. The multiplicative inverse of a = 1/a defines division, ie. @- 1/ The only distributive law applicable is that of - over + a (b+ 0) = (ab) + (a-0) 2:2 AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA 7 f logic and developed In 1854 George Boole (1) introduced a patente nn aoey in 1938 CE is purpose braic system eee : cae. Beit ial neta algebra called switching-lgebra, in which he demonstrated that the properties of bistable electrical switching circuits can be represented by this algebra. For the formal definition of Boolean algebra, ‘we shall employ the postulates formulated by E. V. Huntington (3) in 1904. These Postulates or axioms are not unique for defining Boolean algebra. Other sets of Postulates have been used.* Boolean algebra is an algebraic structure defined ona set of elements B together with two binary operators + and - Provided the following (Huntington) postulates are satisfied: . (@) Closure with respect to the operator +. (©) Closure with respect to the operator . 2. (@) An identity element with t i : An MSPect to +, designated by 0: x +0 = 0 4 (b) An identity element with Tespect to i, “+ designated by 1: x. | = 3. (a) Commutative with respect ao (©) Commutative with rns, cs a bs 2 mae Oe 4. (a) - is distributive oy, . ee er +: x. = (©) + is distributive over ee = * a ae). * For every clement x ¢ B, ther ae Somplement of x) such ike, there exists an a ele; ’ 6. Th r C@xt yoy ‘Ment x’ TONE ehists at least two el ‘ements x, Scanned with CamScannerSEC. 2-2 AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA 37, 2. The distributive law of + over -, ie, x + (y+ z) = (x + y): (x + 2), is valid for Boolean algebra, but not for ordinary algebra. 3, Boolean algebra does not have additive or multiplicative inverses; there- fore, there are no subiraction or division operations, pea uoniekgiNisionioperations 4, Postulate 5 defines an operator called complement which is not available in f fi rdinary algebr: se aeee ae 5. Ordinary algebra deals with the real numbers, which constitute an infinite set of elements. Boolean algebra deals with the as yet undefined set_of elements B, but in the two-valued Boolean algebra defined below (and of interest in our subsequent use of this algebra), B is defined as a set with only two elements, 0 and 1. 5 Oand Boolean algebra resembles ordinary algebra in some respects. The choice of symbols + and - is intentjonal to facilitate Boolean algebraic manipulations by persons already familiar with ordinary algebra. Although one can use some knowl- edge from ordinary algebra to deal with Boolean algebra, the beginner must be careful not to substitute the rules of ordinary algebra where they are not applicable. It is important to distinguish between the elements of the set of an algebraic structure and the variables of an algebraic system. For example, the elements of the field of real numbers are numbers, whereas variables such as a, b, c, etc., used in ordinary algebra, are symbols that stand for real numbers. Similarly in Boolean algebra, one defines the elements of the set B, and variables such as x, y, z are merely symbols that represent the elements. At this point, it is important to realize that in order to have a Boolean algebra, one must show: 1. the elements of the set B, 2, the rules of operation for the two binary operators, and 3. that the set of elements B, together with the two operators, satisfies the six Huntington postulates. @ne can formulate many Boolean algebras, depending on the choice of elements of B and the rules of operation.* In our subsequent work, we deal only with a two-valued Boolean algebra, ie. one with only two elements. Two-valued Boolean algebra has applications in set theory (the algebra of classes) cand in propositional logic. Our interest here is with the application of Boolean algebra to gate-type circuits. Two-Valued Boolean Algebra A two-valued Boolean algebra is defined on a set of two elements, B = (0, 1}, with : for the two binary operators + and - as shown.in the following operator rule for the complement operator is for verification of postulate 5): {for exam le, Hohn (6), Whitest (7), or Birkhotf and Bartee (4) vod Scanned with CamScannerre 38 BOOLEAN ALGEBRA AND LOGIC GATES. Ha x x 0 1 1 0 ‘These rules are exactly the same as the AND, OR, and NOT operations, respec. ‘tively, defined in Table 1-6. We must now show that the Huntington postulates are “valid for the set B = (0, 1) and the two binary operators defined above. ‘bna) moind 1. Closure is obvious from the tables since the result of each operation is either 1 or 0 and 1,0€ B. ». 2. From the tables we see that: @0+00 SO) VAL Sebat O+15140=1 -0=0-1=0 from the’ symmetry of thé bi - vedi airless wees tags Nat be aiebutes an, x: Uy, zh (we anhse oy eee GOES hold true from the operator tables ; * 2 Possible values of xy, andr For cach meee, ruth table of all 20 + dand show tat he value sth are as (2+ Ce So GN+eD Scanned with CamScannerGalks BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA 39 6, Postulate 6 is satisfied because the two-valued Boolean algebra has two distinct elements | and 0 with 1 # 0. We have just established a two-valued Boolean algebra having a set of two elements, 1 and 0, two binary operators with operation rules equivalent to the AND and OR operations, and a complement operator equivalent to the NOT operator. Thus, Boolean algebra has been defined in a formal mathematical manner and has been shown to be equivalent to the binary logic presented heuristically in Section 1-8. The heuristic presentation is helpful in understanding the application of Boolean algebra to gate-type circuits, The formal Presentation is necessary for developing the theorems and properties of the algebraic system. The two-valued Boolean algebra defined in this section is also called “switching algebra” by engineers. To emphasize the similarities between two-valued Boolean algebra and other binary systems, this algebra was called “binary logic” in Section 1-8. From here on, we shall drop the adjective “two-valued” from Boolean algebra in subsequent discussions. 2-3 BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA Duality The Huntington postulates have been listed in pairs and designated by part (a) and Part (b). One part may be obtained from the other if the binary operators and the identity elements are interchanged. This important property of Boolean algebra is called the duality principle. It states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity slements are interchanged. In a two-valued Boolean algebra, the identity elements and the elements of the set B are the same: | and 0. The duality principle has many applications. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1’s by 0's and 0's by I's. Basic Theorems Table 2-1 lists six theorems of Boolean algebra and four of its postulates. The Notation is simplified by omitting the - whenever this does not lead to confusion. a and postulates listed are the most basic relationships in Boolean algebra. The reader is advised to become familiar with them as soon as possible. pe like the postulates, are listed in pairs; each relation is the dual of the with it. The postulates ai ic axioms of the algebraic structure and of. The theorems rust be proven from the postulates. The proofs of With one. variable are presented below. At the right is listed the ep te which justifies each step of the proof. beth Biupin 2: va: Scanned with CamScanner)x-1ax @) xtx <1 ©) xx =0 ayes ©) x-xex @x+1<1 ©) x-0=0 eorem 3, involution Gy = x ‘ ©) 9 = yx Postulate 3, commutative (a) x + yeytx leorem 4, associative % Xt OF Da +y) +z Oy oo {ott Xx +; Treat’ 4 distibutive (2% O ny, tot Ore pay orem 5, DeMorgan AS inde Carden 0) xe + yalg Theorem 6, absorption (2) ," we id THEOREM T@): x + x2) 4H XS eH) FY = + x(x + x) by postulate: 2(b) Sa). ze , 4) = 5) a 2a) THEOREM 1): x-x = x XX = xx 4 by postulate: 2a) = XxX + xx! S(b) = x(x > x!) 4a) = x1 S(@) =x 2b) Note that theorem 10) is the dual of theorem 1(@) and that each Step of | Proof in part (b) is the dual of part (a). Any dual theorem can be Similarly deriy from the Proof of its Corresponding Pair, THEOREM 2@: x4 15 i PS hen) ERIE By Sb! xO by postulate: 2b) Scanned with CamScannerASIC TI $60.23 BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA 4f The theorems involving two or three variables may be proven algebraically from the postulates: and the theorems which have already been proven. Take, for the absorption theorem. L 7 | example; THEOREM 6(a): x + xy = x. Ce x+xa=x-1+ xy _ by postulate 2(b) = x(1 + y) by postulate 4(a) t = xy) by postulate 3(a) =x by theorem 2a) | =x by postulate 2(b)' 4 THEOREM 6(b): x(x +») = x by duality, 9 2, 7” The theorems of Boolean algebra ‘can’be shown to hold true by means of truth tables. In truth tables, both sides of the relation are checked to yield identical results for all possible’ combinations of variables involved. The following truth table verifies the first absorption theorem. gh? ay 0 0 i} 1 +0 0l* The algebraic proofs of the associative law and De Morgan's theorem are long and 4 will not be shown here. However, their validity is easily shown with truth tables. Vt For example, the truth table for the first De Morgan's theorem (x + y)' = x'y’ is shown below. Operator Precedence a precedent ing Boolean expressions is (1) parentheses, (2) is NOT.) AND and aye aa Ee gis the expression inside the parentheses {Ff TUS be evaluated before all other operations. The next operation that holds Precedence is the complement, then follows the AND, and finally the OR. As ie ‘consider the truth table for De Morgan's theorem. The left side of the Eire, Scanned with CamScanner, nests Bis x')”. fore, the expression inside the P's. exp? ‘evaluated es then complemented. The right side °° poth me prece- complement of x and the complement of metic the segition are Fesult is then ANDed. Note that in ordinary anit and ad dence holds (except for the complement) when multiplical replaced by AND and OR, respectively. Venn Diagram «chips among the A helpful illustration that may be used to visualize the une consists of a variables of a Boolean expression is the Venn diagram. This diaBM 1 ing circles, rectangle such as shown in Fig. 2-, inside of which are drawn OVE! TFT ay point, one for each variable. Each circle is labeled by a variable. We deSIBE™ cote a, inside a circle as belonging to the named variable and all points owIsic® © not belonging to the variable, Take, for example, the circ‘e labeled inside the circle, we say that x = 1; when outside, we say x= 0. Now overlapping circles, there are four distinct areas inside the rectangle: the area no belonging to either x or y (x’y’), the area inside circle y but outside x (x'y), th area inside circle x but outside y (xy’), and the area inside both circles (xy)- Venn diagrams may be used to illustrate the postulates of Boolean algebra o seer bes validity of theorems. Figure 2-2, for example, illustrates that the are aust the date pide, the circle “x and therefore x +2 = x. Figure 2- S the distributive law x(y + z) = xy + xz. In this diagram we have thre overlapping circles, one for cach of the variables dz. It is possi distinguish eight distinct areas in athree-variable Veno dineary, fo thee lar example, the distributive law is demonstrated by note ha eer es Batic. ing the circle x with the area en ma ee Ene area iuterec aes y OF z is the area belonging to x closing Scanned with CamScannerx42) ay has Figure 2-3 Venn diagram illustration of the distributive law 2-4 BOOLEAN FUNCTIONS A binary variable can take the value of 0 or 1. A Booleas ion is an expression formed with binary variables, the two binary operators OR and AND, the unary operator NOT wrentheses, and ‘equal sign. For a given value of the variables, the / ‘anction can be either 0 or 1. Consider, for example, the Boolean function: rhe function F, is equal to 1 if x = | andy = land z' = 1; otherwise F, = 0. The above is an example of a Boolean function represented as.an algebraic expression, ‘A’Boolean function may also be represented in a truth table, To representa function in a truth table, we need a list of the 2" combinations of I's and 0's of the n binary variables, and a column showing the combinations for which the function is equal to 1 or 0. As’ sown in Table 2-2, there are eight possible distinct combinations for assigning bits to three variables. The column labeled F, contains either a.0-or a 1 for each of these Combinations. The table shows that the function Fy is ¢ 1 ly when 'x = 1, y= 1, and z = 0. Tt is equal to 0 otherwise. Note that the statement z' = 1 is equivalent to saying that 2 = 0.) Consider now efi qed iavithoal= oat be nee i F,= 972 narang okiainsy Oo =0, while z = Scanned with CamScannerSe Taste 2-2. Truth tables for F, = xyz’, Fy = x + y't Fy = xiy't + x'yt + 10, and Fy = ay’ + x’ 2 y z F Fy Fy Fa et ee 0 Od 0 0 0 o o 0 1 0 1 1 ' 0 1 0 0 0 0 # 0 1 1 0 0 1 1 1 o 0 0 1 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 OP Ps ee table. The number of Any Boolean function can be represented i 8 ables Harte function. rows in where 1 is the number of Binary varia” the binary The 1's and 0's combinations for each row is easily obtamNE™ " e is a value numbers by counting from 0 to 2" — 1. For each row of the table TN tcaic for the function equal to either 1 or 0. The question now eeu it possible to expression of a given Boolean function unique? In other wore®, Se aia find two algebraic expressions that specify the same function? The ee question is yes. As a matter of fact, the manipulation of Boolean algebra is appl mostly to the problem of finding simpler expre the same function. Consider, for example, the function: ssions for Fy= xy + x2 From Table 2-2, we find that F, is the same as.Fs, since both have identical 1’s and 0's for each combination of values of the three binary variables. In general, two functions of n binary variables are said to be equal if they have the same value for all possible 2” combinations of the n variables. A Boolean function may be transformed from an algebraic expression into 4 logic diagram composed of AND, OR, and NOT gates. The implementation of the four functions introduced in the previous discussion is shown in Fig. 2-4. The logic diagram includes an inverter circuit for every variable present in its complement form. (The inverter is unnecessary if the complement of the variable is available.) There is an AND gate for each term in the expression, and an OR gate is used to combine two or more terms. From the diagrams, it is obvious that the implement2- tion of F, requires fewer gates and fewer inputs than Fy. Sirice F, and Fes equal Boolean functions, it is more economical to implement the eceutian d form. To find simpler circuits, one must know how to manipul, = tions i i a = itl eh 2a P pplication. In this section, consider” tion is given to the criterion of equipment minimization, “4 Scanned with CamScanner—p—_ (iNet (bo) Fy =a tye ; A foveal on) —y ) @ ()) Fy Saye trys tn" @) Fy = tr: Figure 2-4 Implementation of Boolean functions with gates Algebraic Manipulation eres eet A literal isa primed or unprimed variable. When a Boolean function is imple- mented with logic gates, each literal in the function designates an input to a gate, and each term is implémented with a gate. The minimization of the number of literals and the number of terms results in a circuit with less equipment. It is not always possible to minimize both simultaneously; usually, further criteria must be available. At the moment, we shall narrow the minimization criterion to literal minimization. We shall discuss other criteria in Chapter 5. The number of literals 45 Scanned with CamScannerCH.2 Unfor. Be final 295) we te the mized ih : ‘tia wit 1 proces em pecomes familiar With 5 meth tunately, there Ani hod availal , The only method avait? Sher m anipulaion fice! an : basic theorems, Ras to. use. The following ¢: EXAMPLE minimum number of ii ‘amples illustrate this __ pootean fue at: Simplify th iterals. -«s eee 2. +e ee 3 vs 4 te Oo ’ 1 oy pepe + 2) day + x2 + Ee ANE ye XIE ra ee) + ve +9) =x x's yt ate +2 by Lx +xy pax'z +0" siete duality from function 4. Functions 1 and 2 are the duals of each other and use dual expressions in corresponding steps. Function 3 shows the equality of the functions F3 and F, discussed previously. The fourth illustrates the fact that an increase in the number - Hed sometimes leads to a final simpler expression. Function 5 is not minimized directly but i " rae e lirectly but can be derived from the dual of the steps used to derive Complement of a Function The complement of a function F is F’ and is obtai for V's and V's for Os in the value of F ea from an interchange of 0's derived lgebraealy through De Morgan's thesia oe ent of a function may be TE fay, Dep ferns 7 ree-variable form of extended to three of derived below. The postulates and theorems at sae Dee Morgan's theorem is (A+ B+CY=(A 4+ xy petabie 21: = Aix’ Seer =4'(B + cy ‘heorem 5(a) (De Morgan) =A (BIC! Substitute B+ C= mane” By theorem a) (De Mo scram) (essociathe) He in form the two-vari- Scanned with CamScannerSEC. 2-5 able case and can be derived by successive CANONICAL AND STANDARD FORMS = 47 substitutions similar to the method used in the above derivation. These theorems can be generalized as follows: (AF B+ C+D4--: +FY =ABCD'...F (ABCD: ++ Fy = A'+ B The generalized form of De Morgan's th 1 Gl AO. EES orem states that the complement of a function is obtained by interchanging AND and OR operators and complementing each literal. EXAMPLE 2-2: Find the complement of the functions F, = x’yz! + x’y’z and F, = x(y’2’ + yz). Applying De Morgan's theo- rem as many times as necessary, the complements are obtained as follows: Fi = (x'yz’ + -x'y'z)' = (xyz) (x'y'2 = (x to + z(x + y+ 2) Fy =[x(2" + ar (2 + yzY = + OzY - (zy =x t(y +2) + 2) ‘A simpler procedure for deriving praee e of a function is to take the dual of the function and complement each literal. This method follows from: the generalized De Morgan’s theorem. Remember ‘that the dual of a function is eetained from the interchange of AND and OR operators and 1's and 0's EXAMPLE 2-3; Find the complement of the functions F and F, of Example 2-2 by taking their. duals and complementing each literal. 1. Fy = xyz tx Y'2 The dual of F, is (x) ty + 2X2! + y+ D- ‘Complement each literal: (x +." + Doty bh z)= Fe 2. Fy = x0"2) + 92). THe dual OFF) iO" ZIPS Gomiplement each literal? x" +07 + 207" 4 2) = Fa: 2-5 CANONICAL AND STANDARD FORMS Minterms and Maxterms A binary variable may appear either form (x’). Now considet two binary ‘operation. Since each variable may ap! in its normal form (x) ‘ Mariables x and y combined with an AND pear in either form, there are four possible or in its complement Scanned with CamScanner‘Tape 2-3 Minterms and maxterms for three bi ry variables Minterms 6 Sohne ApS + get 000. xy" mo x+y te ie O01 xy'z m xty tz Ma O 1 0) xyz! m, 5 TO Ms OL dis xyz ms tyre Ma 10.05 xy'2' ma x te Ms MeO Ty Gay's ms xy te Ms, 110 x» mg x ty ae val i en cd m ny 2 combinations: x’y', x’y, xy’, and xy. Each of these four AND terms represents oné of the distinct areas in the Venn diagram of Fig. 2-1 and is called a minterm or % standard product. Ina similar manner, n variables canbe combined to’ form 2 minterms. The 2" different minterms may be determined by/a method similar to the one shown in Table 2-3 for three variables. The binary numbers from 0 to 2" — | are listed under the n variables. Each minterm is obtained from an AND term of the n variables, with each variable being primed if the corresponding bit of the binary number is a0 and unprimed if a'1. A’symbol for €ach minterm is also shown in the table and is of the form m,, where j denotes the decimal equivalent of the binary number of the minterm designated. __ In a similar fashion, m variables forming an OR term, with each variable being primed or unprimed, provide 2" possible combinations, called maxterms or standard sums. The eight maxterms for three variables, together with their bolic designatic listed in Table 2-3. Any 2" eo See ge a Any 2" maxterms for n variables may be determined similarly. Each maxterm is obtained from an OR term of the m variables, with each variable being unprimed if the oo bere primed if a 1.* Note that each maxterm is the complemene nr ne, Ot i 2 0 and minterm, and vice versa. of its corresponding A Boolean function may be expressed algebrai ‘ by forming a minterm for each combination of tin ica ima given truth table the function, and then taking the OR of all those terms, F which produces a | in A, in Table 2-4 is determined by expressing th ss: For example, the function A= X24 wie xyz = m, + m, f/agghaN 4 t+ m, - a0. The defi variables, with each variable being cmon es mata ah OME hk cee ‘ype functions, | 0) tus Scanned with CamScanner‘Taste 2-4 Functions of three variables xe Function fy wv 000 0 ool 0 o10 0 ord 1 1.0.0 0 1041 1 110 1 1 yg od 1 Similarly, it may be easily verified that: Sy = X'yz + 292 + xyz’ + xyz = m, + ms + Mm, + mM, These examples demonstrate an important property of Boolean algebra: Any Boolean function can be expressed as a sum of minterms (by “sum” is meant the ORing of terms). ‘Now consider the complement of a Boolean function. It may be read from the truth table by forming a minterm for each combination that produces a 0 in the function and then ORing those terms. The complement of f, is read as: Si = xy't! + xyz! + xyz + 2092 + 297" If we take the complement of f;, we obtain the function f,: fra (ety tx ty + Mxty ot 2x byt Ze +9 +2) = Mo: Mz: My Ms" Mc Similarly, it is possible to read the expression for f; from the table: LEE Hele ty 4 Da ty + Gt y+ z)(x' +y + z) ff ion 3 bs = MoM\M,M, | These examples demonstrate a second important property of Boolean algebra: Any | Boolean function can be expressed as a product of maxterms (by “product” is the ANDing of terms). The procedure for obtaining the product of s directly from the truth table is as follows. Form a maxterm for each on of the vatiables which produces a 0 in the function, and then form the all those maxterms. Boolean functions expressed as a sum of minterms or ns are.said’ ; Bat Scanned with CamScannerSum of Minterms Ba i btain 2” distinc i iables, one can 0! It was previously stated that for 7 binary vari ones as a sum of minterms. re: t minterms, and that any Boolean function can be exp! BS eae give the 1's of The minterms whose sum defines the Boolean function i or 0 for each he mont ab sin Hs ue the ost ent sihce there are 2" minterms, 0) Bitreaabs toned with m variables to be 2”. It is sometimes Clea eo es the Boolean function in its sum-of-minterms form. If not in this ee ae made so by first expanding the expression into a sum of AND Cer ee is then inspected to see if it contains all the variables. If it misses 0 re variables, it is ANDed with an expression such as x + x, where x is one of the missing variables, The following example clarifies this procedure. EXAMPLE 2-4: Express the Boolean function F = A + B’C in a sum of minterms. The function has three variables A, B, and C. The first term A is missing two variables; therefore: A= A(B + B’) = AB + AB’ This is still missing one’variable: A= AB(C + C') + ABYC+ cy = ABC + ABC’ + AB’C + AB’C’ The second term B’C is missing one variable: BC=BIC( A+ A) = AB’C + A'B'C Combining all terms, we have: Featsc gel = ABC + 4BC’ But 4B’ is poss Det twice, ae Ascending or eee one of them theorem 1 (x + x = x, it »e finally obtain: “'T@98iNg the minterms in PABCH ABC 44BC + ABC aio, His, someti s Me + cist FA. B, c) 2 ; Scanned with CamScanner25 SEC. 2. CANONICAL AND STANDARD FORMS 5ST Ee The eae. symbol > stands for the ORing of terms; the numbers following it are the minterms of the function. The letters in parentheses following F form a list of the variables in the order taken when the minterm is converted to an AND term. Product of Maxterms . ‘ Each of the 2” functions of » binary variables can be also expressed as a product of maxterms. To express the Boolean function as a product of maxterms, it must t be brought into a form of OR terms. This may be done by using the distributive law x + yz = (x + y)(x + 2). Then any mi . \ . y missing variable x in each ‘OR term is ORed with xx’. This procedure is clarified by the following example. first inction F = xy + xz he function into OR ~ 6 rg \v r EXAMPLE 2-5: Express the Boolean fut in a product of maxterm form. First convert tt terms using the distributive law: ¥ Fexytxza(ot x'\(xy + 2) = (xt xy + x)(x + y+ 2) " = (x) + yx + DY +2) The function has three variables: x, y, and z. Each OR term is missing one variable; therefore: ( MI EA, Habba? AK. bch) Mathoihs) ee poven ch xackae ON SHOR PHD CL EYE) re ee de ae deal oll ale Combining all the terms and removing those that appear more than once, we finally obtain: FH=(xty eal ty’ + 2 ty + et = MyM.MiMs 10 express this function is as fol F(x», 2) = (0, 2,4 5) Ding of maxterms; ytz) x A convenient way lows: the numbers are The product symbol, II, denotes the AN the maxterms of the function. een Canonical Forms «» Satiersion betw set i Is the sum. of e C0 ion expressed as the sum of minterms equal a i 3 inal function. This is because the original function minterms that make the function equal to 1, while its et 6 Scanned with CamScanner— funct complement is a 1 for those minterms that the consider the function: ae F(A, B,C) = 214 5 This has a complement that can be expressed 88: + Ms F(A, B, C) = 3(0,2,3) = 0 2 's theorem, Now, if we take the complement of F’ by De Morgan's different form: + tems = MoM2Ms F = (1g + m, + my)! = mig= my: ms and maxterms as ‘hat the following relation holds sae interms ‘The last conversion follows from the definition of mH shown in Table 2-3. From the table, it is cleat true: mj = M, interm with the That is, the maxterm with subscript j is a complement of the mint same subscript j, and vice versa. 5 The last example demonstrates the conversion between a function eo in sum of minterms and its equivalent in product of maxterms. A similar argument will show that the conversion between the product of maxterms and the sum of minterms is’ similar. We now state a general conversion procedure. To convert from one canonical form to another, interchange the symbols > and II and list those numbers missing from the original form, As another example, the function: (x,y,z) = T1(0, 2, 4, 5) is expressed in the product of maxterm form. Its conversion to sum of minterms is: F(x, y, z) = X(1,3, 6, 7) Note that, in order to find the missing terms, one must i | t of minterms or maxterms is 2", where n is the See rss ey nL ine Fiactife, of binary variables in the Standard Forms __ Another way to ex configuration, ‘press Boolean functions ig j if . Buration, the terms that form the function mag Standard form, {n this f Contain one, two or at! Scanned with CamScanneri SEC. 2-6 OTHER LOGIC OPERATIONS 53 number of literals. There are two types of standard forms: the sum of products and product of sums. The sum of products is a Boolean expression containing AND terms, called product terms, of one or more literals each. The sum denotes the ORing of these terms. An example of a function expressed in sum of products is: Fy = y' + xy + xyz! The expression has three product terms of one, two, and three literals each, respectively. Their sum is in effect an OR operation. ‘A product of sums is a Boolean expression containing OR terms, called sum terms, Each term may have any number of literals. The product denotes the 'ANDing of these terms. An example of a function expressed in product of sums is: Fy = x(y’ + z)(x’ + y + 2! + w) This expression has three sum terms of one, two, and four literals each. The product is an AND operation. The use of the words product and sum stems from the similarity of the AND operation to the arithmetic product (multiplication) and the similarity of the OR operation to the arithmetic sum (addition). ‘A Boolean function may be expressed in a nonstandard form. For example, the function: F, = (AB + CD)(A’B' + C'D’) is neither in sum of products nor in product of sums. It can be changed to a standard form by using the distributive law to remove the parentheses: F,= A'B'CD + ABC'D' 2-6 OTHER LOGIC OPERATIONS When the binary operators AND and OR are placed between two variables x and », they form two Boolean functions x-y and x +), respectively. It was stated Previously that there are 2” functions for n binary variables. For two variables, n=2 and the number of possible Boolean functions is 16. Therefore, the AND of 16 possible functions formed with two and OR functions are only two of a total ‘ 3 binary variables. It. would be instructive to find the other 14 functions and investigate their ties. " The eases ge 16 functions formed with two binary variables x and The truth tables for th are listed in - is table, each of the 16 cokumns Fy to Fs represents J are listed in Table 2-5. In this table, a etal truth table of ‘ble function for the two given variables ¢ function eid from the 16 binary combinations that can be assigned the functions are shown with an operator symbol. For example, F, Scanned with CamScannerScanned with CamScannerSEC. 2-6 OTHER LOGIC OPERATIONS 55 second column of Table 2-6. However, all the new symbols shown, except for the exclusive-OR symbol ®, are not in common use by digital designers. Each of the functions in Table 2-6 is listed with an accompanying name and comment that explains the function in some way. The 16 functions listed can be subdivided into three categories: 1. Two functions that produce a constant 0 or 1. 2. Four functions with unary operations complement and transfer. 3. Ten functions with binary operators that define eight different operations AND, OR, NAND, NOR, exclusive-OR, equivalence, inhibition, and implication, Any function can be equal to.a constant, but a binary function can be equal to only 1 or 0. The complement function produces the complement of each of the binary variables: A function which is.equal to,an input variable has been given the name transfer, because the variable x or y is transferred through the gate that forms the function without changing its value. Of the eight binary operators, two (inhibi- tion and implication) are used by logicians but are seldom used in computer logic. The AND and.OR operators have been mentioned in conjunction with Boolean algebra. The other four functions are extensively used in the design of digital systems, The NOR function is the complement of the OR function and its name is an abbreviation of not-OR. Similarly, NAND is the complement of AND and is an _ abbreviation of not-AND. The exclusive-OR, abbreviated XOR or EOR, is similar to OR but excludes the combination of both x and y being equal to 1. The equivalence is.a function. that is 1, when the two binary variables are equal, i.e., when both are 0 or both are I. The exclusive-OR and equivalence functions are the complements, of each other, This can be easily verified by inspecting Table 2-5. _ The truth tabie for the exclusive-OR is F and for the equivalence is Fy, and these two functions are the complements of each other. For this reason, the equivalence function is often called exclusive-NOR, i.c., exclusive-OR-NOT, ont Boolean algebra, as defined in Sections 2-2, has two binary operators, which we have called AND-and OR, and a unary operator, NOT (complement). From | the definitions, we have deduced a number of properties of, these operators and now have defined other binary operators in terms of them. There is nothing unique about this procedure. We could have just as well started with the operator NOR (for example, and later defined AND, OR, and NOT in terms of it, There are, _ © nevertheless, good reasons for inti ucing Boolean algebra in the way it has been introduced. The concepts of “and,” “or,” and “not” are familiar and are used by people to express everyday logical ideas. Moreover, the Huntington postulates lect the dual nature of the algebra, emphasizing the symmetry, of + and - with to each other. fay rsttadl’bew 1005 a sndon sb Scanned with CamScannerae pa DIGITAL LOGIC GATES 4 AND, OR, and pe Glace Bootean functions are expressed in terms Of Te ypes Rear tion it is easier to implement @ Boolean func! tions # H ate for the other logic OPETAE TT of net it possibility of constructing interest. Factors to be weighe logic gates are (1) the feasibility components, (2) the possibility of ¢x f the binary operator is e wit? racing the BV, inf tl two ti tending the gate to more than ro git in ve ch as commutativity or mone i t Boolean func’ uc the basic properties o| a and (4) the ability of the gate to implemen sant and conjuction with other gates. a const” gered as rf the 16 functions defined in Table 2-6, two are Sa consid Biative others are repeated twice. There are only fen functions It not corn thet candidates for logic gates. Two. inhibition and implica jon wales equiva- or associative and thus are impractical ie im ae NORD aeclusive-OR an fer, AND, OR, NAND- i: Ht Fig. 2-5. eight: complement, trans lence, are used as standai "The graphic symbols Each gate has one or two binary in binary output variable designated by F. The bower is the Logie SOME oye in the output of defined in Fig. 1-6. The inverter circuit inver' re It produces the NOT, or complement, function. he smal The triangle i i logic complement. : the graphic symbol of an inverter designates the logi insfer function ‘symbol by itself designates a buffer circuit. ‘A buffer produces the trai . a since the binary value of the but does not produce any particular logic operation, eb output is equal to the binary value of the input. This circuit 1s used-merely for power amplification of the signal and is equivalent to two inverters connected in cascade. The NAND function is the complement of the AND function, as indicated by i pts symbol which consists of an AND graphic symbol followed by a small a e e RG tenet is the complement of the OR function and uses an OR ic symbol followed by a i ee « far more ‘ahaa te, Ts rae AND ind NOR easy onto ih Hea, ‘ause Boolean functions can be uaiNinpl aoe d The exclusive-OR a -OR gate has a i f eet additional curved ta a similar to that of the OR gate, gate is th le input si oi . le complement of the ceceele The equivalence, of small citcle on the ou itput si a4: put side of the graphic SSabee IR, as indicated by the Extension to Multiple Inputs rd gates in digital design. hown in and truth tables of the eight £20 are ercand y-and One put variables designat tet circuits were ‘AND, OR, we ‘a binary variable. The gates shown in Fi hhave more than two 18. 2-5, except for the i inputs. A gay inverter and but “dl * can be extended to ha fer, can be extended 10 Scanned with CamScannerName Graphic Algebraic Truth symbol function table x y|F x 0 ofo AND ee PO Fey 0 1/0 1 o]o tala x yl F am) OR : a> F Fexty Ory Libd 1 0; 1 1oaild x|[F Inverter x > Fo F=x' oft ilo FE x Buffer x —p— F Fie x raed 1a — col Hono NOR Fo F=(x+yy NAND 7 > Femi: Exclusive-OR x p Frw'txy (KOR) y =x®y Exclusive NOR ay Fae ey equivalence” +208 Figure 2-5 Digital logic gates -o0-|5| o-oo] mlooo-|5|o---| > Scanned with CamScanner$8 BOOLEAN ALGEBRA AND LOGIC GATES CHa i i i ive and associative. The AND binary operation it represents is commutative an e and Q Operations, defined in Boolean algebra, possess these two Properties. For the on function we have: r “i : x+y=y+x commutative and ate Se ate (NT RP Gly ee pate ; = * Which indicates that he uetati " leat ore ctor ure ate, SRN and thatthe OR function Th id Ni . MS are co s to have more than twa mmutative i i = and their Bates can be so ‘puts, provided eS an b sent ie I ditfculty is that the NAND anion the operation is u Noi DN x1 42), ag shown in Fig, Fa RR operators ae CR eerecte : yy NaN pe Sgt he a Pe oe fads ol Pal dificult, we de ow “omplemented OR (or ANG YS define the ee OR dive ? Bate: Thus, by definitions fn it The xyz (ero We have: i Tas wapng belkead 8 ADS tay See r cascaded Ng™POs for the ‘ OL sianity the OF ME NANG TCMpUL ga a Signify the Prope sequen ee sen is Tes > Scanned with CamScanner(b) Three-input NAND gate (ABCY + (DEY'\' = ABC + DE (c) Cascaded NAND gates Figure 2-7 Multiple-input and cascaded NOR and NAND gates ‘of Fig. 2-7(c). The Boolean function for the circuit must be written as: F =[(ABC)(DE) |’ = ABC + DE The second expression is obtained from De Morgan’s theorem. It also shows that an expression in sum of products can be implemented with NAND gates. Further discussion of NAND and NOR gates can be found in Sections 3-6, 4-7, and 4-8. The exclusive-OR and equivalence gates are both commutative and associa- pve, afd can be extended to more than two inputs. However, multiple-input ‘exclusive-OR gates are uncommon from the hardware standpoint. In fact, even a two-input function is usually constructed with other types of gates. Moreover, the definition of these functions must be modified when extended to more than two variables. The exclusive-OR is an odd function, ie., it is equal to | if the input variables have an odd number of I’s. The equivalence function is an even function, ie, it is equal to 1 if the input variables have an even number of 0's. The construction of a three-input exclusive-OR function is shown in Fig. 2-8. It is (a) Using two-input gates (b) A three-input gate tok Figure 28 Three-input exclusive-OR gate Scanned with CamScannerChe 60 BOOLEAN ALGEBRA AND LOGIC GATES . i input gates aS shown in (a). Graphically ted by cascading two-inp\ Saat Ok Ptah ke ally implemen s ara ) eat ie represented with a single three-input gate fonly one input is equal to | in indicates that the output Fis equal to 1 ber of 1's in the input in (c) clearly aren i the tol ts are equal to I, ie., when seen eet Sa al Pe her discussion of exclusive-OR and equivale: in Section 4-9. 2-8 IC DIGITAL LOGIC FAMILIES The IC was introduced in Section 1-9, where it was stated that digital circuits are invariably constructed with ICs. Having discussed various digital logic gates in the previous section, we are now in a position to present IC gates and discuss their general properties. Digital IC gates are classified not only by their logic operation, but also by the specific logic-circuit family to which they belong. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. The basic circuit in each family is either a NAND or a NOR gate. The electronic components employed in the construction of the basic circuit are usually uused to name the logic family. Many different logic families of digital ICs have been introduced commercially. The ones that have achieved wi : are listed below. earn Popularity TTL Transistor-transistor logic ECL Emitter-coupled logic MOS Metal-oxide semiconductor . MOS Complementary metal-oxide semiconductor PL Integrated-injection logic é TTL has an extensive list of digital functions popular logic family. ECL is used in systems requi MOS and PL are used in circuits requiring high component , used in systems requiring low power consumption. The analysis of the basic electronic circuit in each logic Chapter 13. The reader familiar with basic electronics can Tefe; ‘ this time to become acquainted with these electronic circuits. Hes. discussion to the general properties of the various IC gates available. Because of the high density with which transistors can be fabr:. and PL, these two families are mostly used for LSI functions, families, TTL, ECL, and CMOS, have LSI devices and also a large num, and SSI devices. SSI devices are those that come with a small number flip-flops (presented in Section 6-2) in one IC package. The limit on the Scanned with CamScannerOGIC FAMILIES 87 ge. 2-8 IC DIGITAL L circuits in SSI devices is the number of pins in the package. A 14-pin package, for xample, can accommodate only four two-input gates, because each gate requires t for output, for a total of 12 three external pins—two each for inputs and one each a tot ins. The remaining two pins are needed for supplying power to the circuits. — ‘Some typical SSI circuits are shown in Fig. 2-9. Each IC is enclosed within a 14- or 16-pin package: The pins are numbered along the two sides of the package Ghd specify the connections that can be made. The gates drawn inside the ICs are for information only and cannot be seen because the actual IC package appears as shown in Fig. 1-8. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series. The former has a wide operating-temperature range, suitable for qmilitary use, and the latter has a narrower temperature range, suitable for industrial use. The numeric designation of the 7400 series means that IC packages are numbered as 7400, 7401, 7402, etc. Some vendors make available TTL ICs with different numerical designations, such as the 9000 or the 8000 series. Figure 2-9a) shows two TTL SSI circuits. The 7404 provides six (hex) inverters in a package. The 7400 provides four (quadruple) 2-input NAND gates. ‘The terminals marked Vcc and GND are the power supply pins which require a voltage of 5 volts for proper operation. The most common ECL type is designated as the 10,000 series. Figure 2-9(b) shows two ECL circuits. The 10102 provides four 2-input NOR gates. Note that an ECL gate may have two outputs, one for the NOR function and another for the OR function (pin 9 of the 10102 IC). The 10107 IC provides three exclusive-OR gates, Here again there are two outputs from each gate; the other output gives the exclusive-NOR function or equivalence. ECL gates have three terminals for power eae Voc, and Vcc are usually connected to ground, and Veg to a —5.2-volt supply. CMOS circuits of the 4000 series are shown in Fig. 2-“(c). Only two 4-input NOR gates can be accommodated in the 4002 because of pin limitation. The 4050 type provides six buffer gates. Both ICs have two unused terminals marked NC (no connection). The terminal marked Vp requires a power supply voltage from 3 to 15 volts, while Vs is usually connected to ground. Positive and Negative Logic The binary signal at the inputs or output of any gate can have one of two values, a during transition. One signal value represents logic-1 and the other, logic-0. ice two signal values are assigned to two logic values, there exist two different assignments. of signals to logic. Because of the principle of duality of Boolean an periae of signal-value assignment results in a dual-function Consider the two values of a binary signal as shown in Fig. 2- ‘be higher than the other since the two values must be Beets _ a them. We designate the higher level by H and the lower level Scanned with CamScannerVeo me ie tae ty: 110 : Mee nt taanad bag inS nate GND 7400--Quadruple 2-input NAND gates Hees es 1615 14 Tals drigbueyto riboroi rt ots Foaywog got alnaisnra) godt oved etm {Meds oonste 3 nose ; agai NOR i © ©0107 Tipe exeisive-OR/NOR tes po ; s : © (b) ECL gates. baw vinO 42) 5 gi 21 urate, a. £95738, OOP adi. Yo etinxari Cottam nig Yo 22ygoo4 SONA ait Scanned with CamScannermor t.. ee Logie Signal value abun. Logic Signal value value ' Say H ° " o l galls a (a) Positive logic (b)_ Negative lo; Figure 2-10 Signal-amplitude assignment and type of logic by L. There are two choices for logic-value assignment. Choosing the high-level H to represent logic-1, as shown in Fig. 2-10(a), defines a positive-logic system. Choosing the low-level. to represent logic-1, as shown in Fig. 2-10(b), defines a negative-logic system. The. terms positive and negative are somewhat misleading since both signal values may. be positive or both may be negative. It is not signal polarity. that determines the type of logic, but rather the assignment of logic values according to the relative amplitudes of the signals. Integrated-circuit data sheets define digital functions not in terms of logic-1 or logic-0, but rather in terms of H and L levels. It is up to the user to decide on a positive or negative logié assignment. The high-level and low-level voltages for the three IC digital logic families are listed in Table 2-7. In each family, there is a range of voltage values that the circuit will recognize as a high or low level. The typical value is the most.commonly encountered. The table also lists the voltage- supply requirements for each family as a reference. TTL has typical values of H = 3.5 volts and L = 0.2 volt. ECL has two negative values, with H = — 0.8 volt and L = — 1.8 volt. Note that even though both levels are negative, the higher one is —0.8. CMOS gates can use a supply Voltage Vp anywhere from 3 to 15 volts; typically, either 5 or 10 volts is used. The signal values in CMOS are a function of the supply voltage with H = Vp and L=0 volt. The polarity assignments for positive and negative logic are also i ion, it would be necessary to justify the logic symbols 2 rake, for example, one of the gates of the 7400 ‘High-level voltage (V) | Low-level voltage (V) ~ Ra "Range Typical Scanned with CamScannerCH.2 64 BOOLEAN ALGEBRA AND LOGIC GATES IC. This gate is shown in block diagram form in Fig, 2-11) 2 esha truth Table for this gate given in a data sheet js shown in Fig, ze Dee el the physical behavior of the gate, with H being typically 3. volt. This physical gate can function as either 2 NAND or on the polarity assignment. phe Bite, Seo able of Fig. 2-11(6) assumes positive logic assignment with we hhis truth table with the truth tables in Fig. 2-5, we recognize it as a NAND gate. The grap! sitive-logic NAND gate 1s shown in Fig. 2-11(¢) and is simil : ‘Now consider the negative-logic assignment for this physical gate with L=1 and HO. The result isthe truth table shown in Fig. 2-11(¢). This table can be recognized to represent the NOR function even though its entries are listed tackwards. The graphic symbol for a negative-logic NOR gate is shown in Fig. 2-11), The small triangle in the input and output wires designates a polarity jadieator. The presence of this polarity indicator along @ termin: negative logic is assigned to the terminal. Thus, the same physical gate can fasstion either as a positivelogic NAND or as a negative-logic NOR. The one bs Palit Lon 4 8 17 H L HL | aH 7400 t HA L by ‘gate (4) Truth table in terms of H and L. (b) Gate block diagram es Duns at ee 0 ras , € (c) Truth table for Positive logic: (4) Graphic Hl, rene ) Graphic symbol for h Positive logic NAND gate. z 0 arate . Gaon pUeOn at ». 3 er (0 Graphic symbol fc Negative logic NOR, NOR gate. Scanned with CamScannerSEC. 28 IC DIGITAL LOGIC FAMILIES 65 drawn in the diagram is completely dependent on the polarity assignment that the designer wishes to employ. In a similar manner, it is possible to show that a positive-logic NOR is the same physical gate as a negative-logic NAND. The same relation holds between AND and OR gates or between exclusive-OR and equivalence gates. In any case, if negative logic is assumed in any input or output terminal, it is necessary to include the polarity indicator triangle symbol along the terminal. Some digital designers use this convention to facilitate the design of digital circuits when NAND or NOR gates are used exclusively. We will not use this symbology in this book but will resort to other methods for designing with NAND and NOR gates. Note that the ICs presented in Fig. 2-9 are shown with their positive-logic graphic symbols. They could have been shown with their negative-logic symbols if one wished to do so. The conversion from positive logic to negative logic, and vice versa, is essentially an operation that changes 1’s to 0's and 0's to I's in both inputs and output of a gate. Since this operation produces the dual of a function, the change of all terminals from one polarity to the other results in taking the dual of the function. The result of this conversion is that all AND operations are converted to OR operations (or graphic symbols) and vice versa. In addition, one must not forget to include the polarity indicator in graphic symbols when negative logic is assumed. The small triangle that represents a polarity indicator and the small circle that Tepresents a complementation have similar effects but different meanings. There- fore, one can be replaced by the other, but the interpretation is different. A circle followed by a triangle, as in Fig. 2-11(f), represents a complementation followed by ‘a negative-logic polarity indicator. The two cancel each other and both can be removed. But if both are removed, then the inputs and output of the gate will represent different polarities, Special Characteristics The characteristics of IC digital logic families are usually compared by analyzing _ the circuit of the basic gate in each family. The most important parameters that are evaluated and compared are fan-out, power dissi tion, propagation dé d in._We first explain the properties of these parameters and then use _ them to compare the IC logic families. __... Fan-out specifies the number of standard loads that the output of a gate can lo ve without impairing its s normal operation. A standard load is usually defined as the amount of current needed by a of another gal e same IC family. i the term loading. tea -out. This term is derived from that the output of a gate can supply a limited amount of current, above to operate properly and is said to be overloaded. The output of @ ‘connected to the inputs of other similar gates. Each input consumes t of power from the gate input, so that each additional connection Scanned with CamScanneric GATES sted for a family mount of 10adin, ma fied maximaUm log eq 66 BOOLEAN ALGEBRA AND LOGI he gate. adds to the load of a eel standard digital circuits. These rules y a each output © ata SProne power demai ‘can be connected 1 = allowed for each oul] may cause a malfunction from it. The fan-out 1s th the output of @ gale The fan-out Boolean functions. Care must prerloaded gate, Noninvernnr r bulls ies ae 0 eee provide additional drivin hear oes 10 0 le n ist ~repres {ual power dig Powe, ted redrresents the actual P ; pa tl ‘er does not include the be ne yer. i i aft be considered when simplifyin, pabilities ken not to develOP repressions that result i gp ‘ers or buffers are s employed tg sometime: he supplied his ms the power delivered 10 the ee i a ec with four gates will require, from its power PP dissipated in each Bale In a given system, there may required by each TC ‘aust be considered. The tola he sum total of the POWEr dissipated in all ICs ge transition delay time for a signal to prope e from input to oul ut when the bina si 3e 7 he signals Booogie mies cot ‘amount of time (0 Propagate, “from the inpnts 10 the ake tre 1s defined as, WHE PT gation délay of the gate din nanoseconds ( id Lns is equal to 10-* ofa output. This ion delay is expresse' ather, it rep! power delivered gate from the pow’ Supply, four times the POWST be many ICs, and the power power dissipation in a system © Propagation delay ant ital circuit to its outputs pas n delays through the gates is ration is important, circuit must have a uts of a dig propagatio’ When speed of ope! d the digital outputs second. The signals thal through a series of g the total propagation each gate must have a smal minimum number of series 8 The input signals in mos than one gate. All those gates inputs constitute the first logic level of the circuil input from an output of a first-logic-level gate are t travel from the inp! ates. The sum of the delay of the circuit. I propagation delay ani ates between inputs and { digital circuits are applied simul.aneously to mort that receive their inputs exclusively from external t. Gates that receive at least ont considered to be in the secon’ logic level, and similarly for third and higher levels. The total propagation delay of Pe Fie to the propagation delay of a ate times the number of logit ey ath cieeu, AO a reduction in the number of logic levels results in * Rane signal lelay and faster circuits. The reduction of the propagation iy in circuits may be more important than the reduction in’the total number © gates A speed of operation is a major factor. ‘is fh 3 ge a oe Bs iH i ihe maximum noise voltage added to the input signal of # plat eeu ae = nal gue an_undesirable change in the circuit output AS MS Awe. OsPes OF Ties ci DC noise is used by a drift in dl ___ voltage levels of a signal. AC noise ee Site fife a sea ae Bi 2) e that may be created by othe! Scanned with CamScannerSEC. 2-8 IC DIGITAL LOGIC FAMILIES 67 _switching signals., Thi is “Superimposed upon ae pata a term used to denote an undesirable signal that is PRP ant hoist Eavironme: operating signal. The ability of circuits to operate ‘nt is important in many applications. Noise margin is expressed in voits (V) and Frasted by The met nd represents the maximum. noise signal that canbe Characteristics of IC Logic Families ‘The basic circuit of the TTL logic family is the NAND gate. There are mam versions of TTL, and three of them are listed in Table 2-8. This table gives the general characteristics of the IC logic families. Values listed are representative on a comparison basis. For any one family or version, the values may vary somewhat. un Tasie 2-8 Typical characteristics of IC logic families IC logic Fan-out Power Propagation Noise family dissipation (mW) delay (ns)__ margin (V) Standard TTL 10 10. 10 04 Schottky TTL 10 2 3 oa Low-power Schottky TTL 20 2 10 04 ECL 25 5 2 02 MOS 50 On 5 B | ‘The standard TTL gate was the first version of the TTL family. Additional improvements were added as the technology progressed. The Schottky TTL is a } later improvement that reduces the propagation delay but results in an increase in “power dissipation. The low-power Schottky TTL version sacrifices some speed for i “reduced power dissipation. It has the same propagation delay as the standard TTL, the power dissipation is reduced considerably. The fan-out of the standard TTL is 10 but the low-power Schottky version has a fan-out of 20. Under certain "conditions the other versions may also have a fan-out of 20. The noise margin is ter than 0.4 V, with a typical value of | V. “The basic circuit of the ECL family is the NOR pate. ‘The special advantage ECL gates is their low propagation delay. Some ECL versions may have a gation delay as low as 0.5 ns. The power dissipation in ECL gates is ively high ‘and the noise margin low. These two parameters impose 4 when choosing ECL over other logic families. However, because of tion delay, ECL offers the highest speed of any family and is the fast systems. el ‘GMOs ce the inverter from which both NAND and NOR “The special advantage of CMOS is its extremely low tatic conditions, the CMOS gate power dissipation is ‘ : Scanned with CamScannerTE! cH Loic GATES 2 ‘ALGEBRA AND 68 BOOLEAN the gate signal changes state, there 2 eh a Shea whicl TH \d averages: o negligible an ea in the table is a typical value of dynanic 8 dynamic power ran be listed ircuit is exerci 2 wet dissipation in CMOS gates {OS is its high propagation delay. 7; Poets cme major disadvantage of CM iring high-speed operatig’* The one major disad for use in systems requiring ® P erations, means that it is not practical for the CMOS gate depend on the power suppjy The characteristic peice power dissipation increases with increase in volta, vel ae es delay decreases with increase in voltage supply, and thy wee as tgnated tobe about AO% ofthe voltage supply value, REFERENCES 1. Boole, G., An Investigation of the Laws of Thought. New York: Dover Pub., 1954. 2. Shannon, C. E., “A Symbolic Analysis of Relay and Switching Circuits.” Trans. of the AIEE, Vol. 57 (1938), 713-23. 3. Huntington, E. V., “Sets of Independent Postulates for the Algebra of Logic.” Trans, ‘Am. Math. Soc., Vol. 5 (1904), 288-309, “ GitollG. and T.C. Bartee, Modern Applied Algebra. New York: McGraw-Hill Book » I! 5. Birkhoff, G., and S. Maclane, A Me : Mibaias Cong ‘Survey of Modern Algebra, 31d ed. New York: The 6. Hohn, F. E., Applied Boolean Algebra, 2nd 7. Whitesitt, J. E., Boolean Algebra and i i toe and its 10. RCA Solid State Data Book Series: COS, N. J. RCA Solid State Div., 1974, PROBLEMS 21. Which of the six basic laws (closure, associat comm, ‘istrbutive) are satisied forthe pair of binary operne : Scanned with CamScannerPROBLEMS 9 that the set of three elements {0, 1, 2) and the two binary operators + and: as -2. Show 2 ‘a Boolean algebra. State which of the Huntington Sctined by the above table is not postulates is not satisfied. 3.32 | Démonstrate by means of truth tables the validity of the following theorems of Boolean algebra. ty 1(@ The associative laws. (b) De Morgan's theorems for three variables. (6) The distributive law of + Over * 2-4, Repeat problem 2-3 using Venn diagrams. 2.5. _ Simplify the following Bool functions to @ minimum number of literals. @ay ty! Bisa 7 ) (x +e +9) (© 92 + xy + 07 t @ zx + exy 1+ (©) (A + BY(A! + BY © (D y(w2! + 2) +7 2-6. Reduce the following, Boolean expressions to the required number of literals. (a) ABC + A'B'C + ‘A'BC + ABC’ + ABC’ to five literals (b) BC + AC’ + AB + BCD) » to four literals to three literals (© [(CDy + AY +4 + CD + AB (@ (A+ C+ DIA + CH DA 4Ch+ DA + BY) to four literals | Boolean finctions and reduce them to a Find the complement of the following ‘minimum number of literals. e pei) (BCA A’DIAB’# CDI D oe ¢ HAC DD IASBEL2IO0 ast > : " pide tion ais : AB’ + CoDi ges opophagy Cxtvdzec ammo © a Fubetions(Fy aie: FR" 1h omaioiate ae di oi unction E'= F, + Fy, obtained ofall themintrms in, Fy. and Fa function G = Fifi hom ins those minterms common 10, 09f FARO aie. (¢ SOL-6 mnsldorq te) giv Scanned with CamScanner70 BOOLEAN ALGEBRA ‘anp LOGIC GATES jinimut enGanty the functions 7, and T (0 @ mini m number of literals. ‘ th \ \ ae 0 ee A tal, | ey ° pase ar diespaarinrto eZ neat 1 L Ry 1 aye } Express the following functions in a sum of minterms and a product of maxterms, (a) FIA, B, C, D) = D(A’ + B) + B'D (b) Flow, x,y, 2) = yz + wry! + wz! + wix'z (©) FIA, B, C, D) = (A + B' + CYA + BWA + C+ D’) (A'+ B+ C+ D'\B+ C+D!) \ (@) FIA, B, C) = (A’ + BYB’ + C) ©.Flexy Dm, eis (9) Flx,y4 2) = (ay + 2)(y + x2) oN i ‘Convert the following to the other canonical () F(x, ¥,2) = XU, 3, 7) () F(A, B,C, D) = 30, 2, 6.11, 13, Te ey es 6 ot lO FG, 9 HO3, GD. og (@) FA, B,C D) = 1100, 1, 2, 3, 4,6, 12) What ig the difference! ew A ee neleae wien eee canofiieal form and (2) Prove the above statement for no ke 214, Scanned with CamScanner20, 21. .-22. 23. 2-24, PROBLEMS = 71 (©) The NAND operator is not associative. (a) The NOR and NAND operators are not distributive. A majority gate is a digital circuit wh : g ose output is equal ipsa Th ou O otherwise. By means sgl Sat iets hocks petion implemented by a 3-input majority gate. ‘Simplify the function. ee Verify the truth table for the 3-inj { yput exclusive-OR gate listed in Fi vy eticombinations of x,y» and z; evaluate A = *@ Be leis yy and 25 = x@y; th = eight com> x ® y; then evaluate F= A @z = TTL SSI come mostly in 14-pin packages. Two pi Z . pins are reserved f and the other pins are used for input and output terminals. Tin Gaal ce enclosed in one such package if it contains the following types of gates: (a) 2-input exclusive-OR gates. (b) 3-input AND sates. (©) 4-input NAND gates. (d) 5-input NOR gates. (©) S:input NAND gates. Show that a positive-logic [AND gate is a negative-logic OR gate, and vice versa. An IC logic family has NAND gates with fan-out of 5 and buffer gates with fan-out of 10. Show how the output signal of single NAND B81 can be applied to 50 other gate inputs. gn 8 ANO Scanned with CamScanner