6/10/2021 Microprocessor (210254)

The 80386 processor has two versions 80386DX and 80386SX where

The 80386DX has 32 bit address bus and 32 bit data bus and 80386SX has 32 bit
address bus and 16 bit data bus.

The 80386DX has 32 bit address bus and 32 bit data bus and 80386SX has 32 bit
address bus and 32 bit data bus.

The 80386DX has 32 bit address bus and 32 bit data bus and 80386SX has 24 bit
address bus and 32 bit data bus.

The 80386DX has 32 bit address bus and 32 bit data bus and 80386SX has 24 bit
address bus and 16 bit data bus.

Clear selection

If the source operand is a part of the instruction instead of register or memory, it

Register addressing mode

Immediate addressing mode

Direct addressing mode

Based addressing mode

The segmentation unit translates logical addresses into linear addresses at the
request of.

Execution unit

Data unit

Bus control unit

Paging unit
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6/10/2021 Microprocessor (210254)
g g

Clear selection

What is the width of GDTR?

16 bits

24 bits

32 bits

48 bits

Clear selection

Which of the following is not a bit test instruction?

BSF

BTC

BTR

BTS

Clear selection

The test register(s) that is provided by 80386 for page caching is

test control registers

page cache registers

test control and test status registers

test control and page cache registers

Clear selection

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6/10/2021 Microprocessor (210254)

For JA to be true, following condition should be satisfied

CF=ZF=1

CF=1 or ZF=1

CF=ZF=0

CF=0 or ZF=0

Clear selection

Which instruction is used to swap the content of two operand?

XCHG

TEST

AND

OR

Clear selection

There are instructions that use data from the instruction itself as operand, such
an operand is called _______.

immediate operand

register operand

memory operand

direct operand

Clear selection

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6/10/2021 Microprocessor (210254)

The physical memory that the 80386 can access is ___.

16 MB

1 MB

10 GB

4 GB

Clear selection

______CALL is used for procedure not in same code segment.

Remote

Near

Far

Close

Clear selection

The instructions available in the 80386 that are not available in its real address
mode is

addressing techniques

instructions for protected address mode

instructions for interrupt handling

All of above

Clear selection

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6/10/2021 Microprocessor (210254)

Which of the following is an illegal instruction?

MOV AX, 3000

INC AL,1

AND BX,BX

ADD AX,30

Clear selection

Which of the following flag remains unaffected on execution of AAD?

SF

CF

PF

ZF

Clear selection

The system address registers are accessible in _______mode operation of the

real

protected

A&B

None of these

Clear selection

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6/10/2021 Microprocessor (210254)

Which of the following is not a bit test instruction?

BTC

BTS

BSF

BTR

Clear selection

Instruction used to load LDT register is

LGDT

LLDT

SLDT

SGDT

Clear selection

Which of the following is a data segment register of 80386?

GS

all of the mentioned

ES

FS

Clear selection

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6/10/2021 Microprocessor (210254)

Which of the following is not a newly added instruction of 80386, that are not
present in 80286?

bit scan instructions

shift double instructions

bit test instructions

none of the mentioned

Clear selection

The 16-bit registers are available with their extended size of 32 bits, by adding
the registers with a prefix of

XX

32

Clear selection

The unit that is used for handling data, and calculate offset address is

execution unit

instruction unit

bus interface unit

memory management unit

Cl l ti
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6/10/2021 Microprocessor (210254)
Clear selection

The unit that is disabled in real address mode is

central processing unit

memory management unit

paging unit

bus control unit

Clear selection

Poping from the stack into CS register can be accomplished by which of the
following instruction?

RET

POP

MOV

LDA

Clear selection

ALU of 80386DX is ______bit

16

30

32

20

Clear selection

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6/10/2021 Microprocessor (210254)

The central processing unit has a sub-division of

execution unit and instruction unit

execution unit and memory unit

memory unit and control unit

memory unit and ALU

Clear selection

The 80386 has ______ address space in the real mode.

10 gb

1 gb

10 mb

1 mb

Clear selection

The instruction that shifts the specified number of bits in the instruction, from
the upper side of the source operand into the lower side of the destination
operand is

SHLD

SETNS

none of the mentioned

SHRD

Cl l ti
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6/10/2021 Microprocessor (210254)
Clear selection

The CMP instruction modifies the register?

IP or CS: IP

destination register

flag register

segment register

Clear selection

In Flat model the memory address range supported by 80386 is ________

zero to a maximum of 1gigabytes

zero to a maximum of 2gigabytes

zero to a maximum of 4gigabytes

None of these

Clear selection

Identify the addressing mode of instruction Mov EBX,[EAX]

Direct mode

Register indirect mode

Based mode

Index mode

Clear selection

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6/10/2021 Microprocessor (210254)

Among eight debug registers, DR0-DR7, the registers that are reserved by Intel
are

DR0, DR1, DR2

DR4, DR5

DR1, DR4

DR5, DR6, DR7

Clear selection

The unit that increases the speed of all shift and rotate operations is

instruction unit

memory management unit

execution unit

barrel shifter

Clear selection

If DF=0 then the ESI and EDI registers are ___ by 1 for the string operations.

Increment

Decrement

Multiplied

Rotated

Clear selection

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6/10/2021 Microprocessor (210254)

What is the use of INC instruction?

INC adds one to the destination operand.

INC adds one to the source operand.

INC adds two to the destination operand.

None of these

Clear selection

Identify the addressing mode of instruction [EAX][EDI + 24]

Based Index mode

Based scaled Index mode

Based scaled Index mode with displacement

Based Index mode with displacement

Clear selection

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