This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2021.3068076, IEEE
Transactions on Industry Applications

A Single-Source Switched-Capacitor Based Step-Up

Multilevel Inverter with Reduced Components
Kaibalya Prasad Panda, Student Member, IEEE, Prabhat Ranjan Bana, Student Member, IEEE, Oleh
Kiselychnyk, Member, IEEE, Jihong Wang, Senior Member, IEEE and Gayadhar Panda, Senior
Member, IEEE

Abstract— Switched-capacitor based multilevel inverters (SC Symmetrical MLIs have simpler control while the
MLIs) have received a great deal of interest that reduces the dc asymmetrical structures can increase the voltage levels using
source requirement and improves the power quality. However, less number of dc sources. The CMLI structure in [5] is
multiple dc sources and requirement of a large number of
equipped with capacitors in one of the modules to reduce the
switches to generate a high-quality boost output are the
fundamental issues in the SC MLIs. This paper presents a step- number of dc sources. Even though this circuit creates 5-levels
up 17-level SC MLI using reduced number of switches, three at the output the boosting factor (ratio of the output voltage to
capacitors and a single dc source. The steady-state voltage across input voltage) is still one. The voltage boosting is elemental in
the capacitors is maintained in the ratio 1:2:0.5 that contributes PV systems to match the output voltage with the grid/load
to quadruple boosting ability without using any auxiliary requirement.
capacitor voltage balancing circuit. Besides, lower switch count in
Several structural modifications have been done in recent
the conduction path and operation of 50 % of the switches at
fundamental frequency ensures total power loss reduction in the years to reduce the number of switches, dc sources, and
proposed circuit. A comparative assessment with recently control complexity [7], [11]. These structures can be broadly
developed 17-level MLIs in terms of the number of components, classified into two types. i.e., reduced source switched-
gain, stress and cost factor elucidates the advantages of the capacitor (SC) based boost type topologies and multi-dc non-
proposed MLI. After a detailed circuit analysis and loss boosting MLIs. The switched-source and switched-diode
evaluation, simulations are performed to verify the step-up and
MLIs without the inherent boosting feature are esteemed as
inherent balancing features of the proposed MLI. Further, using
both the fundamental frequency and high-frequency switching the non-boosting type MLIs. Towards an attempt to reduce the
techniques, extensive experimental test results are presented number of dc source structures are developed in [12], [13].
under different transient conditions to validate the operational The input voltage is equally distributed among the capacitors,
feasibility of the 17-level prototype. which appear across the load and consequently lack the ability
to boost the output. Circuit proposed in [14]–[16] for the
Index Terms— Multilevel inverter, reduced components, self- renewable energy application uses series diodes in the
voltage balance, single-source, switched-capacitor, voltage gain.
conduction path. Thus, their operation in highly inductive
loads is unfeasible. However, the voltage level enhancement
I. INTRODUCTION
integrating a floating capacitor is an additional advantage of
Development of multilevel inverters (MLIs) has been a recent the circuit proposed in [14]. An additional switch in [15] can
trend for a variety of low, medium and high-power eliminate the voltage spike appearing due to the inductive
applications [1]–[5]. This is due to the competence of MLI in loads only in the first voltage step. The MLI presented in [17]
generating a sinusoidal-like output using the combination of is suitable for PV systems. However, the circuit requires
switches and dc sources. Diodes and capacitors are the multiple input sources identical to the conventional CMLI.
additional components used in the MLI to strengthen The above-discussed structures embody a back-end H-bridge
structural flexibility. MLIs are used in different applications for generating the negative levels. Excluding the full bridge,
that include photovoltaic (PV) systems, electric vehicles, potential non-boosting structures are disclosed in [18]–[20],
STATCOM, traction drives, high-frequency power which reduces the voltage stress significantly.
distribution, etc. [5]–[7] to enhance the power quality, Apart from this, significant research interest is growing in
efficiency and reliability. Popular MLI topologies are the recent years to develop SC MLIs with inherent boosting
neutral-point clamped (NMLI), flying-capacitor MLI (FMLI) ability. Voltage balancing of SCs without auxiliary sensors
and cascaded H-bridge MLI (CMLI). Both the NMLI and and voltage boosting without additional inductor/transformers
FMLI are subjected to voltage balancing problems and makes the SC MLIs suitable for the PV applications and high-
collapsing of the whole module due to the series connection of frequency ac power distribution [8], [21]–[23]. The MLI
switches [6], [8]. CMLI, on the other hand omits the topologies presented in [24]–[26] uses the same basic unit to
requirement of additional clamping diodes/capacitors. generate high output voltage levels using reduced number of
However, the requirement of large number of semiconductor components. The basic unit consisting of one dc source and a
devices remains a concern in these MLIs for generating higher capacitor can create a two-step twofold boosted output. The
voltage levels at the output. Based on the requirement and charging of the capacitor in parallel and discharging in series
application, CMLI can be operated using equal (symmetrical), with the source enables self-voltage balancing. Single-phase
unequal (asymmetrical) and varying dc sources [9], [10]. extension of these circuits requires more number of dc

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sources. On the other hand, this offers an opportunity to capacitors (C1-C3), two diodes (D1 & D2) and a single dc
increase the voltage levels (17-level, 25-level, 49-level, 81- power supply (Vin). All the switches have an anti-parallel
level) by operating the MLI in symmetrical as well as diode connected across it. The circuit produces a 17-level
asymmetrical modes. A novel basic module proposed in [27] quadruple boost output (0, ±0.5Vin, ±1Vin, ±1.5Vin…, ±4Vin)
synthesizes 9-level twofold boost output using a single dc without using an H-bridge for changing the polarity. The
source. However, the extended version of this structure switch pairs S1-S2 and S11-S12 are complementary, thus reduces
requires multiple dc sources. SC MLI introduced in [28] the control complexity. The switches S5-S10 operates in
requires a number of series-connected dc sources to obtain the fundamental frequency and switch pair S3-S4 operates at lower
desired output. The basic module of the disclosed structure in frequency, which results in low switching losses. In addition,
[29] can produce three-fold three-step output. However, the the voltage stress across each switch in Fig. 1 implies only
switch count and the number of dc source increase when high- three switches S8-S10 withstands peak load voltage stress. The
quality voltage is intended to produce at the output. ratio of voltage across the capacitors C1, C2, and C3
Most recent research also involves the design of SC MLIs (VC1:VC2:VC3) is naturally maintained at 1:2:0.5 in the steady-
with single input even in the extended forms. Charging spike state. To verify the inherent balancing of the capacitors, the
in SCs is addressed in [23] by developing such MLI with a operation of the 17-level SC MLI is analyzed hereafter.
quasi-resonant front-end structure integrated with a back-end 2 S7 S5 2 S10 S11
full-bridge. All the capacitors are equally charged and the S6 C2 4 0.5
input voltage is divided among the capacitors. Consequently, 2
this topology lacks in boosting the voltage. The MLI circuits S3 2
D1 C1 C3
proposed in [30], [31] reduce the voltage stress satisfyingly at S4
2
the cost of a large number of circuit components. Research S2 1
4 0.5
effort is also made in [32] to develop a single-dc hybrid NMLI Vin S1 D2 S9
4 S8 S12
1
based structure to reduce the stress on the switches while + Vo -
Io X Voltage stress
generating 7-level, 9-level and 11-level output. However, the Load
voltage gain in 11-level inverter is limited to 2.5 times the Fig. 1. Proposed 17-level SC MLI topology
input voltage. Recently configured MLIs in [22], [33], [34]
attains high voltage gain (6 times, 4 times and 3 times) using In the positive half-cycle of the output voltage, the first
lower number of components. Conventional H-bridge is not voltage step (+0.5Vin) is produced by discharging only the
required in these circuits to generate the ac voltage output. capacitor C3. The second voltage step (+Vin) is produced by
Including further extension to the 9-level circuit proposed in including the source voltage in the load current path and
[22] towards voltage quality improvement using a lower bypassing the capacitor C3. During this, the diode D1 is in
number of components, an improved SC MLI is proposed in forward conduction and the voltage across the capacitor C1 is
this work with the following prominent features: clamped to Vin by turning on the switch S1. By additionally
i. Single dc source is required to generate a 17-level turning on the switch S11, the capacitor C3 voltage is again
output. added with the input voltage and thus, +1.5Vin is obtained at
ii. Only 12 switches and three capacitors are used in the the load. In the next level (+2Vin), the capacitor C1 discharges
circuit. to the load in series with Vin by turning on switch S2 and C2 is
iii. The capacitor voltages are self-balanced without charged during this instant by triggering the switch S4. The
auxiliary sensors/closed-loop controller. diode D2 is connected to avoid unwanted discharging of the
iv. Four times boosting ability of the circuit (Vo = 4Vin). capacitor C2. The voltage steps +2.5Vin and +3.5Vin are
v. More than 50 % of switches operate at a low obtained by discharging the capacitor C3 as mentioned earlier.
frequency; as a result switching loss is reduced. Discharging of C2 in series with the source produces +3Vin at
vi. The proposed circuit can adequately operate under the output and the load voltage becomes +4Vin when both the
any loading power factor (PF). capacitors (C1 and C2) discharge in series with the source. In
The next section introduces the proposed topology as well the negative half-cycle, the voltage steps -Vin, -2Vin, -3Vin, and
as the capacitor sizing and self-balancing mechanism. The -4Vin are produced similarly by turning on the switches (S8,
power loss analysis is discussed thoroughly in Section III. A S10, S12) instead of the switches (S7, S9, S11). The capacitor C3
comparison with the recent-art MLIs in Section IV confirms is charged during the intermediate voltage levels -0.5Vin, -
the structural advancement. Followed by a detailed discussion 1.5Vin, -2.5Vin, and -3.5Vin. It is also worth noting that there
on the modulation scheme in Section V, Sections VI and VII always exists a path for the reverse flow of current, which
present extensive simulation and experimental investigation, facilitates successful operation of the proposed circuit under
respectively to validate the workability of the 17-level SC different load PF.
MLI. Concluding remarks are provided in Section VII. Table I presents the switching states to synthesize the 17-
level output with any loading PF and the output waveform of
II. SC MLI TOPOLOGY AND ITS OPERATIONAL PRINCIPLES the proposed SC MLI with capacitor charging-discharging
The proposed 17-level SC MLI circuit is shown in Fig. 1. pattern is shown in Fig. 2(a). Fig. 2(b) shows the capacitors C1
The proposed circuit consists of 12 switches (S1-S12), three charges in parallel with the dc source to Vin and discharges in

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series with the source. The capacitor C2 is charged in parallel 0.5Vin voltage across it. Fig. 2(d) shows the equivalent circuit
with Vin+VC1 and discharges in series the accumulated energy and conduction path during the intermediate voltage steps in
(2Vin) to the load as depicted in Fig. 2(c). The capacitor C3 is the positive and negative cycle. Thus, the natural balancing
discharged in the whole positive half-cycle and charged ability of all the three capacitors is confirmed.
symmetrically in the negative half-cycle, thus maintaining
4Vin
Discharging Charging

2Vin
+ve half cycle Reversed -ve half cycle

0.5Vin T/4 LDP of C3 T/2 LDP of C1 3T/2 LDP of C2 T

t1 t2 t3 t4 t5 t6 t7 t8 t16
C1
C2
C3
(a)

S5 S5 S5
C2 C2 C2
Non-conducting devices D1 C1 D1 C1 S6 S6 S6
S3 S3 S3
Conducting devices & Vin S2 2Vin D1 C1 2Vin D1 C1 3Vin D1 C1 4Vin
S2 S4 S4 S4
capacitor discharging
S2 S2 S2
Vin S1 Vin S1
Vin Vin Vin
Capacitor charging S1 D2 S1 D2 S1 D2

(b) (c)

S7 S5 S10 S11 S7 S5 S10 S11 S7 S5 S10 S11 S7 S5 S10 S11

S6 C2 S6 C2 S6 C2 S6 C2

S3 S3 S3 S3
D1 C1 C3 D1 C1 C3 D1 C1 C3 D1 C1 C3
S4 S4 S4 S4
S2 S2 S2 S2
Vin S1 D2 Vin S1 D2 Vin S1 D2 Vin S1 D2
S8 S9 S12 S8 S9 S12 S8 S9 S12 S8 S9 S12
+ Vo - + Vo - + Vo - + Vo -
Io Io Io Io
0.5Vin 1.5Vin 2.5Vin 3.5Vin

S7 S5 S10 S11 S7 S5 S10 S11 S7 S5 S10 S11 S7 S5 S10 S11

S6 C2 S6 C2 S6 C2 S6 C2

S3 S3 S3 S3
D1 C1 C3 D1 C1 C3 D1 C1 C3 D1 C1 C3
S4 S4 S4 S4
S2 S2 S2 S2
Vin S1 D2 Vin S1 D2 Vin S1 D2 Vin S1 D2
S8 S9 S12 S8 S9 S12 S8 S9 S12 S8 S9 S12
+ Vo - + Vo - + Vo - + Vo -
Io Io Io Io
-0.5Vin -1.5Vin -2.5Vin -3.5Vin
(d)

Fig. 2. Operation of the proposed circuit (a) output pattern of the proposed SC MLI, charging-discharging operation of (b) C1, (c) C2, (d) C3

TABLE I (Io) and fundamental voltage where the peak fundamental load
SWITCHING PATTERN OF THE PROPOSED 17-LEVEL SC MLI
current is Iomax.
Conducting switches in Voltage Conducting switches in
Positive half-cycle steps Negative half-cycle /
∆ = 2∫ sin( − ) (1)
S1 – S5 – S7 – S10 – S12 0 S1 – S8 – S9 – S12
S1 – S5 – S7 – S10 – S11 ± Vin/2 S1 – S5 – S6 – S8 – S10 – S11
S1 – S5 – S6 – S7 – S9 – S12 ± Vin S1 – S5 – S6 – S8 – S10 – S12 /
S1 – S5 – S6 – S7 – S9 – S11 ± 3Vin/2 S2 – S4 – S6 – S8 – S10 – S11 ∆ = 2∫ sin( − ) (2)
S2 – S4 – S6 – S7 – S9 – S12 ± 2Vin S2 – S4 – S6 – S8 – S10 – S12
S2 – S4 – S6 – S7 – S9 – S11 ± 5Vin/2 S1 – S3 – S6 – S8 – S10 – S11
S1 – S3 – S5 – S7 – S9 – S12 ± 3Vin S1 – S3 – S6 – S8 – S10 – S12 ∆ = 4∫ sin( − ) (3)
S1 – S3 – S5 – S7 – S9 – S11 ± 7Vin/2 S2 – S3 – S8 – S10 – S11
S2 – S3 – S5 – S7 – S9 – S12 ± 4Vin S2 – S3 – S8 – S10 – S12
Further, based on the fundamental frequency switching output
A. Steady-state switched-capacitor analysis voltage shown in Fig. 2(a), one half-cycle (T/2) can be divided
into sixteen time steps (t1-t16) and therewith t1, t2, t5 and t7 (in
Fig. 2(a) implies that the overall charging time of the sec) are expressed in (5) using (4) [29]:
capacitors is significantly lower than the total output voltage
duration, attesting quick recovery of the capacitor voltages .
after the discharging period. The low parasitic resistance path = = (4)
and adequate charging instant further warrant retaining the
desired capacitor voltage. To select the suitable capacitance,
different factors, i.e., the largest discharging period (LDP) where Ns is the number of voltage steps and Nl is the number
duration of the capacitors (C1 & C2), total discharging time in of levels in the output.
the whole positive half cycle (C3), nominal frequency, lower
( / ) ( / ) ( / ) ( / )
voltage ripple and type of loading, are considered. Assuming , , ,
( / ) ( / ) ( / ) ( / ) (5)
equal duration for all the voltage steps, the discharging , , ,
amount of the capacitors C1–C3 can be expressed as in (1)-(3)
considering φ is the lagging angle between the load current

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The corresponding voltage ripple (∆VrC) is expressed in (6) III. POWER LOSS EVALUATION FOR THE PROPOSED CIRCUIT
and capacitance is given in (7) considering k% voltage ripple Switching loss (Psl), ripple loss (Prl), and conduction loss
in the capacitors. (Pcl) are the three major losses associated with the SC boost
∆ type MLIs [23], [29], [31]. These losses are evaluated in the
∆ = (6) following sections for the proposed 17-level MLI.

≥
∆
, ≥
∆
and ≥
∆
(7) A. Switching loss
( ) ( . )

The time delay between the transitions of a switching state

Applying (1), (2), (3) and (5), the capacitance is finally produces switching power loss (Psl). The blocking voltage (VB)
expressed in (8), (9) and (10). across a semiconductor switch during its off-state charges the
built-in parasitic capacitor (Cp) linearly. Further, Cp discharges
≥ [cos(0.9484 − ) − sin ] (8) from the magnitude VB to zero during the on-state of the
switch. Therefore, the energy loss (Esl) by a semiconductor
≥ [cos(0.5974 − ) − sin ] (9) switch for one transition state can be evaluated using (14).
Thereby the switching power loss during the switching actions
can be calculated using (15).
≥ [cos(0.0625 − ) − cos(0.1886 − )] (10)
= (14)
Using the series-parallel charge balancing principle and with
the selected values given in (8) and (9) considering k% of = = (15)
voltage ripple, the capacitors C1 and C2 naturally maintain the
voltage in a 1:2 ratio. However, capacitors C3 symmetrically As can be noted from Fig. 1, the switches S5-S10 block sum-
discharge and charge in the positive and negative half-cycles, total voltage stress of 18Vin and operate in a fundamental
respectively. Thereby, the self-balancing nature of C3 can also frequency (considering purely resistive loading). Thus,
be verified considering any intermediate voltage steps. For considering fs and fo as the switching and fundamental
instance, consider the equivalent circuit shown in Fig. 3 for frequencies, (15) can be further simplified as follows:
the synthesis of ± 2.5Vin output voltage. The net charge (∆QC3)
is zero, which can be expressed as follows: = [18 +7 ] (16)

∆ =[ (+) − (−)] (11) B. Ripple loss

where IC3 is the current flowing through the capacitor C3. Internal resistances of the capacitor and semiconductor
Assuming the net impedance Z, following expressions are devices that are in the charging path of capacitors (C) generate
derived from the equivalent circuit. ripple loss in the SC MLI. The voltage difference (∆Vc)
between the actual and desired voltage of the capacitor is the
(+) = = (12) key influencing parameter of the ripple energy loss (Erl) that is
evaluated in terms of the charging time (tc) and charging
(−) = = (13) current (Ic).

∆ = ∫ ( ) (17)
Using (12) and (13), ∆ = and hence, VC3 =
0.5Vin at the steady-state. = ∆ (18)

- VC1 + - VC2 + From (17) and (18), the ripple power loss (Prl) can be
Discharging Cycle

Charging Cycle

Io IC3 (-) calculated by (19). It can be observed that the larger value of
+ C1 + + C2 +
LOAD

Vin Vo=+2.5Vin Vo Vin C3 VC3

the capacitance can minimize the Prl. However, a trade-off is
- - - Vo=-2.5Vin - vital between the sizing and the ripple loss due to capacitors.
C3
LOAD
IC3 (+) Io
+ VC3 - + Vo -
= = ∫ ( ) (19)
Fig. 3. Equivalent circuit of proposed circuit during Vo = ±2.5Vin

The above deduction demonstrates the inherent voltage C. Conduction loss

balancing and selection process of suitable capacitance in the
proposed SC MLI. Considering about 5-7% of voltage ripple, The loss incorporated by the parasitic elements of the
the proposed circuit is developed and examined further. conducting devices in the load current path results in the
conduction loss (Pcl). Fig. 4 shows the generalized equivalent

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circuit for the proposed MLI for synthesizing any voltage IV. COMPARATIVE EVALUATION
level. Therein, the output current expression (Io) is given by
To assess the advantages of the proposed SC MLI, a
(20).
comparison is carried out in Table II with recently developed
17-level MLI topologies based on different parameters and
= sin = sin (20) taking into account symmetrical configurations. As stated
earlier, the compared topologies are categorized into two
where mi is the modulation index, which is the ratio of broad categories. The switched-dc or switched-diode based
reference voltage (desired value) to the maximum obtainable circuits basically consist of multiple dc sources and do not
fundamental voltage and Zl is the load impedance. The possess the boosting ability. The SC-based topologies reduce
conduction loss can be evaluated by considering the duration the source count and feature the boosting ability. A number of
of each voltage level. For instance, the time duration (t1-t2) in capacitors and switches are used in such circuits to produce a
Fig. 2(a) represents the voltage level 0.5Vin. Consequently, the high-quality output voltage. However, the proposed circuit
energy loss is expressed in (21), considering the on-state aims at reducing the number of components to produce a 17-
switch resistance (Rs), the internal resistance of the capacitor level output.
(Rc), and forward voltage drop of the diode (VD). Except the MLI proposed in [23], the required number of dc
sources (Ndc) in all the non-boosting structures is more than
( . ) =∫ (4 + ) (21) one. Most of the SC MLIs also require multiple input sources
when extended to create 17-level output, unlike the proposed
The diode voltage drop is not included in (21) as it is in MLI. In view of least number of switches (Nsw) and drivers
reverse bias during 0.5Vin. Consequently, the total conduction (Ndr), the proposed circuit ranks first among other SC MLIs.
loss of the proposed MLI considering all the voltage levels is The MLI disclosed in [14] involves fewer switches and drivers
but at the cost of large number of dc sources. The single dc SC
=8 ∑ . , ,⋯ ( ) (22)
MLIs [30] and [31] do not require discrete diodes (Ndd), but
kRs lVd involve a large number of switches. On the contrary, the
proposed 17-level topology uses only two diodes. Although
Io mV c the use of capacitors supports voltage boosting, the inrush
jVin mR c current increases with increase in number of capacitors. Lower
Zl number of capacitors (Ncap) in the proposed circuit limits the
Fig. 4. Generalized equivalent circuit of the proposed MLI inrush current and increases the reliability. More number of
switches in the conducting path increases the power loss. The
Taking into account the losses derived in (16), (19) and proposed MLI is also superior among all the MLI topologies
(22), the power losses and overall efficiency of the proposed on account of maximum number of switches in the conduction
MLI are evaluated in Section VI using (23). (Nms) for 17-level operation.

= (23)

TABLE II
COMPARISON OF THE SYMMETRICAL 17-LEVEL MLI TOPOLOGIES
MSV TSV Cf Cf Full-
Parameters Ndc Nsw Ndr Ndd Ncap Nms Gain
(x Vin) (x Vin) (δ=0.5) (δ=1.5) bridge
[12] 4 20 20 0 8 10 8 48 1 14.35 15.76 YES
[14] 6 9 9 3 1 6 4 20 1 10.76 12.53 YES
Non-boosting
Switched-
dc/diode

[15] 8 13 13 8 0 10 8 47 1 22.09 24.85 YES

[17] 8 20 20 0 0 10 8 48 1 24.94 27.76 YES
[18] 8 18 18 0 0 9 8 36 1 22.24 24.35 NO
[19] 8 18 18 0 0 9 2 32 1 22.12 24 NO
[23] 1 18 18 8 8 10 8 56 1 3.85 4.26 YES
[24] 4 24 24 4 4 12 2 40 2 16.59 17.76 YES
Switched-capacitor

[25] 2 18 18 6 6 8 8 44 4 6.91 7.56 NO

[26] 4 20 20 4 4 10 8 40 2 14.24 15.41 NO
Boosting

[27] 2 18 14 2 4 6 4 40 2 5.47 6.06 NO

[29] 2 18 18 2 6 7 8 58 4 6.43 7.28 NO
[30] 1 39 39 0 7 16 1 39 8 6.08 6.37 NO
[31] 1 20 16 0 5 10 2 21.5 4 3.16 3.47 NO
Proposed 1 12 12 2 3 6 4 25 4 2.30 2.67 NO
Total standing voltage (TSV) and maximum standing the conventional full-bridge is avoided for producing ac
voltage (MSV) are further evaluated for MLI topologies. TSV output. The MLIs proposed in [31] and [14] have the
is calculated taking into account voltage stress across all the minimum TSV. However, the former requires almost double
switches. Proposed MLI reduces the TSV to a great extent as the number of switches than the proposed MLI and the latter is

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a multi-dc topology that lacks the boosting ability. Proposed = ,0 ≤ ≤1 (27)

( )
MLI has a quadruple boosting gain using minimum number of
switches. Besides, cost factor (Cf) is chosen as a parameter to
The proposed MLI is designed to output a 17-level staircase
establish the design superiority which is defined as,
voltage waveform. Considering the expressions (25) & (27),
.
the associated non-linear equations for the MLI are given in
= (24) (28) with the target to eliminate the 3rd to 15th order
harmonics. To extract the optimal solutions (αp), particle
The Cf is evaluated considering different values of the swarm optimization algorithm (PSO) is employed taking into
weightage coefficient δ (low for more weightage to the account the angle constraint in (29) and fitness function given
number of components and high for more weightage to the in [16].
TSV). The proposed MLI has the least Cf among the other
MLIs under both the conditions (δ = 0.5 and 1.5). Hence, the cos + ⋯ + cos = 8
proposed MLI is a suitable alternative to the recently cos 3 + ⋯ + cos 3 = 0
(28)
developed MLIs for obtaining high-quality output using least ⋮
switch count. cos 15 + ⋯ + cos 15 = 0
V. MODULATION SCHEME
0< < <⋯< ≤ /2 (29)
Fundamental switching control and high frequency switching
control are the two main categories of PWM control schemes Moreover, the performance of the optimization process for the
generally employed to verify the MLI working. Selective proposed MLI can be verified from Fig. 5. Corresponding to
harmonic elimination switching control (SSC) is one of the the minimum value of the fitness function (i.e., in the range
former category of control schemes which aggressively 0.9-0.94), switching angles are selected to verify the operation
eliminates the targeted lower order dominant harmonics and of the proposed circuit. Figure also implies that the total
thereby maintains the highest quality of output waveforms [9], harmonic distortion (THD) level decreases with the increase in
[11], [14], [16]. The fundamental component of staircase mi and also the fundamental value is retained at the desired
output voltage waveform in terms of Fourier series equations level even under a lower mi value. This is one of the dominant
can be expressed as in (25), which is valid for any single- features of the SSC technique and thus, the number of levels
phase MLI. in the output voltage and current does not reduce with the
decrease in mi although an increase in THD can be expected in
= cos + ⋯ + cos sin( ) (25) such scenario. Besides the optimum values of the switching
angles are chosen corresponding to the minimum fitness
Here αp (proportional to ti), n, and Vd are the symbolic function value, a lower mi value of 0.3 is taken as reference to
representation of switching angles, order of harmonics, and verify the SSC principle in next Section.
nominal value of the dc voltage, respectively. Further, p is
directly associated with the number of voltage levels (Nl) as;

=( − 1)/2 (26)

For any voltage level, the switching angle values can be

determined within the modulation index (mi) range of [0, 1] to
eliminate the targeted lower order harmonics from the system, Fig. 5. Fitness function and THD evaluation using SSC technique
and thus it can be regarded as the key control parameter. The
expression of mi in terms of the fundamental and nominal dc
voltage is given as follows:

(a1ã4 + a6ã8)A + (a1ã3 + a5ã7)B + C S1 S2

0 A a1 (a6)A + (a5)B S3
Positive half cycle VCar1
detection (a4ã6)A + (a3ã5)B S4

0 B (a1ã4 + a6ã8)A + (a1ã3)B + AC S5

Negative half cycle
a2 (a2ã6)A + (a1ã6)B S6
Vref detection

Vref VCar2 (A + C) (B + C) S7 S8

(a2)A + BC S9

= C a8 (a1ã2)A + (a1)B + AC S10

0
Zero level detection VCar8 (a2ã3+a4ã5+a6ã7+a8)(A + B) + C S12 S11
Reference Signal Comparator Circuit Switching Logic Decoder Pulses to Switch
Fig. 6. Block diagram of PPC scheme with switching logic

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2021.3068076, IEEE
Transactions on Industry Applications

The fundamental frequency SSC scheme maintains the To validate the 17-level operation using the SSC technique,
required fundamental value of the output and thus cannot first the results are obtained in Fig. 7(a) under dynamically
regulate the ac output (or the voltage gain), which is generally varying mi condition at constant loading of 90 Ω. The 17-level
required in different application of an MLI. In such a case, the output is acquired even with low mi due to fundamental
phase-disposition PWM control (PPC) scheme [14], [19], [33] switching SSC principle, whereas the THD in the load voltage
reduces (See Fig. 7(b)) with the increase in mi. Quadruple
may be employed. In the PPC scheme, multiple carrier signals
step-up ability with the inherent balancing of capacitor
are compared with the reference sinusoidal signal to generate
voltages VC1, VC2 and VC3 are in accordance with the
the PWM signals through the pulse logic decoder as shown in theoretical analysis. Fig. 7(c) verifies the working under a
Fig. 6. In the decoder circuit, the switching logic presented in change in load PF with the change in loading from 90 Ω-108
Table I is synthesized through the appropriate combination of mH to 120 Ω-108 mH. The capacitor voltage ripple decreases
logic gates. The PPC scheme doesn’t involve any complex with an increase in R value for a fixed C1, C2, and C3. The
equations to retain the fundamental component, unlike the capacitor voltages inherently settle to the original value under
SSC technique. Nevertheless, the conversion ratio of the sudden variation in input from 80 V to 100 V as shown in Fig.
proposed circuit can be varied in the range of 0.5Vin to 4Vin by 7(d), which verifies the successful performance of the
varying the mi. proposed SC MLI. Fig. 7(e) depicts the voltage ripple
decreases considerably and the load current drops due to an
VI. SIMULATION ANALYSIS increase in frequency from 50 Hz to 150 Hz (switching angles
corresponding to 150 Hz are also saved in look-up table) in
The proposed 17-level MLI consisting of 12 IGBT switches presence of inductive loading. Evidently, the proposed MLI
is simulated in MATLAB/Simulink environment. The input dc can act as a potential high-frequency ac source for different
source is considered 100 V and the inverter is operated with a applications. Fig. 7(f) shows the voltage stress across all the
50 Hz nominal frequency unless otherwise specified. The unidirectional switches are in accordance with Fig. 1. It is also
capacitance values are accordingly calculated using (8)-(10) apparent that apart from switches S1, S2, S11 and S12, all other
and C1, C2, and C3 are chosen as 3300 μF, 4700 μF, and 2200 switches operate at a low frequency, which thus results in low
μF, respectively. Using the SSC technique, the eight switching power loss in the circuit.
angles corresponding to different mi are saved in a look-up
table for the generation of switching pulses.
Vo (V), 30*Io (A), Vc1 (V), Vc2 (V), Vc3 (V) Vo (V), 30*Io (A), Vc1 (V), Vc2 (V), Vc3 (V)
Selected order of harmonics (3rd to 15th) are
minimized at 0.94 mi using SSC technique

mi = 0.3 mi = 0.94

m i = 0.3 to 0.94 PF=0.93 to 0.96

Time (s) Time (s)

(a) (b) (c)
Vo (V), 30*Io (A), Vc1 (V), Vc2 (V), Vc3 (V) Vo (V), 30*Io (A), Vc1 (V), Vc2 (V), Vc3 (V) VS1(V) to VS6(V) VS7(V) to VS12(V)

Input steps up (Vin= 80 to 100 V) Fo= 50 to 150 Hz

Time (s) Time (s) Time (s)

(d) (e) (f)
Fig. 7. Simulation analysis, (a) Change in modulation index, (b) Harmonic analysis of the load voltage, (c) Change in loading PF, (d) Change in input voltage,
(e) Change in nominal frequency, (f) Voltage stress across all the switches

VII. EXPERIMENTAL VERIFICATION programmable dc supply is initially set to 100 V. As the

To verify the suitable real-time operability, a test setup of output voltage is boosted to four-times the input, the RMS
the proposed 17-level MLI is developed in the laboratory. A value of the load voltage is about 280 V. IGBT switches
12N60A4D with integrated anti-parallel diodes are considered

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2021.3068076, IEEE
Transactions on Industry Applications

for S1-S12 and two MUR860 is used as D1 and D2. Selected transient. Self-balancing of the capacitors in both Fig. 8(a) &
values of the capacitance (C1-C3) are same as in simulation (b) is obtained due to appropriate charging-discharging.
with internal resistances 36 mΩ, 18 mΩ and 54 mΩ, Herein the capacitor currents and the source current are
respectively. A DSP controller with Simulink interfacing is depicted in Fig. 8(c) with 90 Ω load, which implies
used to produce the switching pulses of (0-5) V. An isolated symmetrical charging pattern of the capacitors in a full cycle.
driver circuit built using TLP250 is then used to amplify these The current spikes are reduced using a small inductor (0.03
pulses (about 20 V) which drive the switches. In addition, the mH) in the charging loop that is not shown in the circuit
driver circuit also provides adequate isolation between the analysis for the sake of simplification. The captured power
power circuit and control circuit. A ScopeCoder (DL850E) is analyzer results in Fig. 8(d)-(g) shows the change in active-
used to capture the voltage-current waveforms and the reactive power (P, Q), PF (λ), phase angle (Ф), efficiency (η1),
performance parameters are obtained using a WT1800 power voltage THD and current THD. Fig. 8(d) and (e) are obtained
analyzer. in accordance with Fig. 6(a) at fixed resistive loading and
Identical to the result shown in Fig. 7(a), experimental change in mi. The THD varies with the change in mi. Fig. 8(f)
outputs are obtained with a change in mi and with fixed and (g) are obtained in accordance with Fig. 8(b) with a
resistive loading of 90 Ω in Fig. 8(a). The desired 17-level change in load from RL-1 to RL-2. A proportional increase in
output is obtained with a change in switching pulse in the active power and change in efficiency is witnessed with
conjunction with variation in mi from 0.3 to 0.94. Further, tests decrease in the impedance and PF. Fig. 8(h) and (i) further
follow considering higher mi value (0.94). The RMS value of verify the self-balancing and step-up abilities of the proposed
load current varies from 2.9 A to 3.9 A and the PF varies from circuit with sudden variation in input voltage (90 V to 100 V)
0.93 to 0.85 as the load changes from 90 Ω-108 mH (RL-1) to and output frequency (150 Hz to 50 Hz), respectively. Similar
60 Ω-120 mH (RL-2) in Fig. 8(b). The output voltage and observation as in Fig. 7(f), the voltage stress on switches is
capacitor voltages are undistorted during the sudden load testified in Fig. 8(j).
AcqMode : Normal AcqMo de : Normal AcqMode : Normal
200kS/s 5ms/div 200kS/s 5ms/div 200kS/s 5ms/div

IC1
VC2 VC1 Vo VC2 VC1 Vo
IC2
VC3 VC3
Io Io IC3
mi change Load change Iin
CH1:200 V/div CH2: 5 A/div CH3: 200 V/div CH4:200 V/div CH5:200 V/div CH1:200 V/div CH2: 5 A/div CH3: 200 V/div CH4:200 V/div CH5:200 V/div CH1:10 A/div CH2: 10 A/div CH3: 5 A/div CH4:10 A/div

(a) (b) (c)

Input Output Input Ou tp ut Input Output Input Ou tput

PF PF PF PF

Frequency Frequency Frequency Frequency

Efficiency Efficiency Efficien cy Efficien cy

Voltage THD Voltage THD Voltage THD Voltage THD

Current THD Current THD Current THD Current THD

(d) (e) (f) (g)

AcqMode : Normal AcqMode : Normal AcqMode : Normal
100kS/s 10ms/div 200kS/s 5ms/div 100kS/s 10ms/div

CH1:200 V/div CH2: 200 V/div CH3: 400 V/div CH4:400 V/div
V S1

VS 2
Vo
VC2 VC1 Vo V S3

V S4
VC2 VC3 V S6
V S9
VC1
V S1 0
Input supply variation VC3 Output frequency variation V S1 1
CH1:200 V/div CH3: 200 V/div CH4:100 V/div CH5:100 V/div CH1:200 V/div CH3: 200 V/div CH4:200 V/div CH5:200 V/div CH5:400 V/div CH6: 1000 V/div CH7: 1000 V/div CH8:100 V/div

(h) (i) (j)

Fig. 8. Experimental output voltage & current waveform (a) Sudden variation in mi, (b) Change in loading PF, (c) Current through the capacitors and input
current, (d) Parameters at mi = 0.3, (e) Parameters at mi = 0.94, (f) Parameters under RL-1, (g) Parameters under RL-2, (h) Input supply step-up, (i) Sudden
change in output frequency, (j) Voltage stress across (S1, S2, S3, S4, S6, S9, S10, S11)

To verify the adequate operation of the proposed circuit, 2 kHz and 50 Hz, respectively. Initially, the proposed inverter
experimental tests are further performed with PPC technique produce a 13-level output with 0.6 mi and desired 17-level
considering a switching frequency and nominal frequencies of output is obtained as shown in Fig. 9(a) once the mi is changed

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2021.3068076, IEEE
Transactions on Industry Applications

to unity. Fig. 9(b) ascertains a clean sinusoidal load current, with corresponding output power considering pure resistive
undistorted load voltage and self-balanced capacitor voltages loading of 90 Ω. It is clear from Fig. 9(c) that the switching
with a change in loading from RL-1 to RL-2 under the PPC power loss, conduction loss and the ripple losses increase with
scheme. The efficiency of the prototype is further evaluated an increase in the output power.

AcqMode : Normal AcqMode : Normal

200kS/s 5ms/div 200kS/s 5ms/div 100 60

Power loss (W)

Effi ciency (%)
95 40

VC2 VC1 Vo VC2 VC1 Vo 90 20

VC3 VC3 Io 85 0
Io
400 600 800 1000 1200
mi change Load change Out put power (W)
CH1:200 V/div CH2: 5 A/div CH3: 200 V/div CH4:200 V/div CH5:200 V/div CH1:200 V/div CH2: 5 A/div CH3: 200 V/div CH4:200 V/div CH5:200 V/div Psl Pcl Prl Efficiency

(a) (b) (c)

Fig. 9. Experimental verification of the proposed MLI with PPC scheme (a) Change in mi, (b) Change in loading PF, (c) Efficiency and loss evaluation

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIA.2021.3068076, IEEE
Transactions on Industry Applications

Journal of Emerging and Selected Topics in Power Electronics

Electronics, pp. 1– National Institute of Technology Meghalaya, Shillong, India. His research
1, 2018. interests include reduced switch multilevel inverter design, power quality
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Electronics, He was a visiting
isiting scholar with the University of Warwick, U.K., during
vol. 61, no. 7, pp. 3269–3278, Jul. 2014. January to March 2019, funded through the Joint UK-India
UK Clean Energy
[20] M. Sharifzadeh, H. Vahedi, and K. Al-Haddad,Haddad, “New Constraint in (JUICE) two months exchange program scheme. He was recipient of Prof.
SHE-PWM for Single-Phase Phase Inverter Applications,” IEEE Subhasis Nandi Student Travel Awards for Power Electronics,
Electron Drives and
Transactions on Industry Applications,, vol. 54, no. 5, pp. 4554
4554–4562, Energy Systems (PEDES 2018) conference and IAS Travel grant for Power
Sep. 2018. Electronics, Smart Grid and Renewable Energy (PESGRE 2020) conference.
[21] H. K. Jahan, M. Abapour, and K. Zare, “Switched
“Switched-Capacitor-Based He is a regular Reviewer of several IEEE and IET Journals.
Single-Source Cascaded H-Bridge Bridge Multilevel Inverter Featuring
Boosting Ability,” IEEE Transactions on Power Electronics, vol. 34,
Prabhat Ranjan Bana (S’19) received the B.Tech.
no. 2, pp. 1113–1124, Feb. 2019.
degree in electrical engineering from the PMEC,
[22] K. P. Panda, P. R. Bana, and G. Panda, “A Single Source SwitchedSwitched-
Berhampur, India, in 2016, and the M.Tech. degree in
Capacitor Based Multilevel Inverter for Photovoltaic Application,” in
power and energy systems specialization from the NIT
2020 IEEE International Conference on Power Electronics, Sma Smart
Meghalaya, Shillong, India, in 2019, where he was also
Grid and Renewable Energy (PESGRE2020),, Kerala, India, 2020, pp.
a Research Associate from July 2019 to
t February 2020.
1–6.
He is currently a Ph.D. Scholar in the Department of
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Electric Power Engineering, NTNU, Norway. His
Capacitor Multilevel Inverter With Self-Voltage
Voltage Balancing for Single
Single-
research interests include multilevel inverters, photovoltaic systems, and
Phase High-Frequency AC Microgrids,” IEEE Tran Transactions on
power quality.
Industrial Informatics, vol. 13, no. 5, pp. 2669–2679,
2679, Oct. 2017.
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Oleh Kiselychnyk (M’15) received the M.Sc. and Ph.D.
Switched Capacitor Units,” IEEE Transactions on Industrial
degrees in
n electrical engineering and automation
au from
Electronics, vol. 61, no. 9, pp. 4614–4621,
4621, Sep. 20
2014.
the National Technical
nical University of Ukraine “Kyiv
“Kyi
[25] R. Shalchi Alishah, S. H. Hosseini, E. Babaei, M. Sabahi, and G. B.
Polytechnic Institute” (NTUU “KPI”), in 1993 and 1997,
Gharehpetian, “New High Step-Up Up Multilevel Converter Topology
respectively. He is currently an Associate Professor in
With Self-Voltage
Voltage Balancing Ability and Its Optimization Analysis,”
the School of Engineering,
neering, University of Warwick,
IEEE Transactions on Industrial Electronics,, vol. 64, no. 9, pp. 7060–
Coventry, U.K. From 2002 until 2012, he h was a Docent
7070, Sep. 2017.
of the Department of Electrical
Elec Drives of NTUU “KPI.”
[26] E. Zamiri, N. Vosoughi, S. H. Hosseini, R. Barzegarkhoo, and M.
He was also a Visiting
Visit Fulbright Scholar at the
Sabahi, “A New Cascaded Switched-CapacitorCapacitor Multilevel Inverter
University of Utah, Salt Lake City, UT, USA, in 2009,
Based on Improved Series–Parallel
Parallel Conversion With Less Number of
and a Visiting German Academic Exchange Service Researcher at the th
Components,” IEEE Transactions
nsactions on Industrial Electronics
Electronics, vol. 63,
Hamburg University of Technology, ogy, Hamburg, Germany, in 2008. His main
no. 6, pp. 3582–3594, Jun. 2016.
research interests include
lude control of electrical motors and generators, power
[27] R. Barzegarkhoo, M. Moradzadeh, E. Zamiri, H. M. Kojabadi, and F.
electronic converters and automation of industrial installations.
installations
Blaabjerg, “A New Boost Switched-Capacitor
Capacitor Multilevel Converter
With Reduced Circuit Devices,” IEEE Transa Transactions on Power
Jihong Wang (M’06–SM’12)SM’12) received her Bachelor’s
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6754, Aug. 2018.
and Master’s Degrees in Electrical Engineering from
[28] S. S. Lee, K.-B. B. Lee, I. M. Alsofyani, Y. Bak, and J. F. Wong,
Wuhan University of Technology and Shandong
“Improved Switched-Capacitor
Capacitor Integrated Multilevel Inverter With a
University of Technology, China, respectively. She
DC Source String,” IEEE Transactions on Industry A Applications, vol.
obtained the Ph.D. degree from Coventry University,
55, no. 6, pp. 7368–7376, Nov. 2019.
U.K., in 1995. She is currently a Professor in Electrical
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Power and Control Engineering with the School of
using Novel Switched Capacitor Converters with Reduced
Engineering, University of Warwick,
Warwi UK. Her current
Components,” IEEE Transactions on Industrial Electronics
Electronics, pp. 1–1,
research interests include nonlinear system control, power system modelling
2020.
and control,, energy storage and grid integration. She was Technical Editor for
[30] A. Taghvaie, J. Adabi, and M. Rezanejad, “A Self Self-Balanced Step-Up
the IEEE/ASME Transactions on Mechatronics and is Associate Editor to the
Multilevel Inverter Based on Switched-Capacitor
Capacitor Structure,” IEEE
IEEE Journal
rnal of Emerging and Selected Topics in Industrial Electronics.
Electronics
Transactions on Power Electronics,, vol. 33, no. 1, pp. 199199–209, Jan.
2018.
Gayadhar Panda (M’07–SM’19) received the
[31] W. Lin, J. Zeng, J. Liu, Z. Yan, and R. Hu, “Generalized Symmetrical
bachelor’s degree in electrical engineering from the
Step-Up
Up Multilevel Inverter Using Crisscross Capacitor Units,” IEEE
Institute of Engineers,
Engineer Kolkata, India, the Master’s
Transactions on Industrial Electronics, pp. 1–1,1, 2019.
degree in power electronics from Bengal
[32] S. S. Lee, C. S. Lim, and K.-B. B. Lee, “Novel Active
Active-Neutral-Point-
Engineering College (presently IIEST), Shibpur,
Clamped Inverters With Improved Voltage-Boosting Boosting Capability,”
India, and the Ph.D. degree in electrical engineering
IEEE Transactions on Power Electronics,, vol. 35, no. 6, pp. 5978 5978–
from Utkal University, Bhubaneswar, India, in 1996,
5986, Jun. 2020.
1998, and 2007, respectively.
[33] K. P. Panda, P. R. Bana, and G. Panda, “A Switched
Switched-Capacitor Self-
He is currently a Professor with the Department of Electrical Engineering,
Balanced High-GainGain Multilevel Inverter Employing a Single DC
National Institute of Technology, Meghalaya, India. He has served as Head of
Source,” IEEE Transactions
sactions on Circuits and Systems II: Express
the department and Chairman of various committees at institute level. He is
Briefs, vol. 67, no. 12, pp. 3192–3196,
3196, Dec. 2020.
also currently looking afterr Dean academic affairs (AA) at NIT Meghalaya.
[34] K. P. Panda, P. R. Bana, and G. Panda, “A Reduced Device Count
He has more than 20 years of teaching experience. His current research
Single DC Hybrid Switched-Capacitor Self-Balanced
Balanced Inverter,” IEEE
interests include automatic generation control, stability improvements using
Transactions on Circuits and nd Systems II: Express Briefs
Briefs, vol. 68, no.
flexible alternating current transmission system devices, power
pow quality, power
3, pp. 978–982, Mar. 2021.
electronic converters, and distributed power generation.

Kaibalya Prasad Panda (S’18) received the B.Tech.

degree in electrical and electronics engineering from the
Dr. M.G.R. University, Chennai, India, in 2011 and the
M.Tech. degree in power electronics and drives
specialization from the KIIT University, Bhubaneswar,
India, in 2013. He is currently working toward th
the Ph.D.
degree with the Department of Electrical Engineering,

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