Loss Balancing in Three-Level Voltage Source Inverters

applying Active NPC Switches

T. Bruckner S. Bernet
Dresden University of Technology ABB Corporate Research
Institute of Electrical Power Engineering P.O. Box 101332
01062 Dresden, Germany 69003 Heidelberg, Germany
[email protected] [email protected]

Abstract - This paper investigates the use of active neutral An additional critical operating point in electric drive
point clamp switches in the three-level NPC voltage source systems is zero speed, especially if synchronous machines are
inverter to balance the losses among the semiconductors. Both being used. This case is characterized by a very low funda-
control structure and algorithm are proposed which enable a mental output frequency (as low as zero Hertz) and a low
substantially increased output power of the inverter and an
improved performance at zero speed.
modulation depth. The maximum allowable phase current is
limited by the losses in the NPC diodes, which is equivalent
to case 2 in Table I. Due to the low fundamental output
I. INTRODUCTION frequency the devices of one phase may be stressed with the
peak value of the phase current for a time long enough to
Since its introduction in the early 80s the three-level
reach thermal steady state. The inverter design method based
Neutral Point Clamped Voltage Source Inverter (NPC VSI)
on average junction temperatures, which is used for output
E13 has gained more and more importance on the market.
Today this inverter is used in medium voltage drives (MVD)
for industry applications, such as rolling mills, fans, pumps,
marine and traction applications. l?,lOC
The analysis of this inverter at sinusoidal modulation shows 60
that its thermal design is mainly determined by the four
55
operating points given in Table I. In each of the four cases the
phase current and the output power of the converter are 50
limited by the maximum losses of the most stressed semi- 45
conductor device. At the same time all other semiconductors
reach a much lower junction temperature as shown in Fig. 1 40
and 2 for cases 1 and 2 of Table I. This unequal loss distribu- 37
tion yields a relatively low switch utilization which can be Tout Dout Tin Din Dnpc
considered as a drawback of the three-level NPC VSI. The Fig. 1. Average junction temperatures in a three-level NPC VSI at
maximum junction temperatures of the most stressed devices max. modulation depth (Eupec 3.3kV 1200A IGBTs, LIde=3400V,
are comparable in all four cases. Hence, all semiconductors I,,,p600A,f~1050Hz, M=1.15, PF=I, ambient temp. 19==37"C)
would have to be substituted by larger devices in order to
increase the converter output power.

TABLE I
OPERATION POINTS OF THE THREE-LEVEL NPc VsI WITH MAXIMUM
UNEQUAL SEMICONDUnOR LOSS DlSTRlBUTlON

Tout Doa Tin Din Dnpc

Fig. 2. Average junction temperatures in a three-level NPC VSI at

low modulation depth (Eupec 3.3kV 1200A IGBTs, (/dc=3400v,
I,,,=600A,f~1050Hz, M=O.Ol, PF=I, ambient temp. &=37"C)

0-7803-7067-8/01/$10.0002001 IEEE 1135

frequencies of fo>SHz, is no longer applicable. The achiev- 11. ANALYSIS
OF THE THREE-LEVEL VSI WITH ACTIVE NPC
able phase current is cut down drastically compared to rated SWITCHES
operation. Though this problem may be mitigated by a
A. Switch States
reduction of the switching frequency at zero speed, all
commercially available medium voltage drive systems still Consider a single phase leg of the circuit shown in Fig. 3.
suffer from about 30% derated output power at zero speed In contrast to the conventional diode-clamped NPC VSI, in
today. However, applications like hot and cold rolling mills the phase leg with active NPC switches there is more than one
typically demand up to 250% rated torque and hence more switch state to realize the zero state, one phase’s connection
than twice the rated phase current at zero speed. This requires to the neutral point. The switch states of the diode-clamped
a drastic overrating of the three-level NPC VSJ in these inverter and of the inverter with active NPC switches are
applications. given in Tables I1 and 111, respectively.
In today’s MVD inverters IGBT modules with integrated In the diode-clamped NPC VSI the utilization of the upper
inverse diodes are used as main switches by several manu- or lower NPC path is determined by the direction of the phase
facturers. For modularity reasons and to guarantee an equal current. The switches T2 as well as T3 are always turned on in
voltage sharing in the case of series connected devices [ 2 ] , “0”-state. If active NPC switches are applied, by turning on
IGBT modules are usually installed instead of single NPC T5 and T2 the phase current can be conducted through the
diodes as depicted in Fig. 3. These NPC IGBTs are operated upper path of the neutral tap in both directions. In the same
in the active region to control the voltage sharing of series manner, by turning on T6 and T3 the phase current can be
connected modules or they are turned off by a Gate-Emitter- conducted through the lower path of the neutral tap in both
short while the integrated inverse diode acts as NPC diode. directions. Of course, all four switches T5, TZ,Tg, and T3 of
However, active NPC switches allow a specific utilization of the phase considered could also be turned on at once. Then,
the upper and lower path of the neutral tap and therewith the current distribution between the upper and the lower NPC
enable the reduction of the aforementioned drawbacks. Active path is determined by the variation of the on-state character-
NPC switches have not yet been utilized in this way. This istics of the devices being used. This state is not investigated
paper shows the opportunities of an active use of the NPC further. If the upper NPC path is utilized (T6 and T3 are off)
switches to achieve a better loss distribution and higher T4 may be in on- or off-state. This is also true for TI during
semiconductor utilization. the conduction of the lower NPC path (T5 and T2 are off). The
resulting four switch states are designated “OL2”, “OLl”,
In particular, the additional switch states and commutations
“OUl”, and “OU2”, respectively.
applying the active NPC switches are discussed. Their influ-
ence on the loss distribution within the inverter ’is explained. During the “+”-state T6 should be turned on to guarantee an
Based on this analysis a novel loss-balancing scheme is equal voltage sharing between T3 and T4. Analogously TS
proposed which is capable of increasing the inverter output should be turned on during the “-“-state. Thus, additional bal-
power by 20%. This is achieved solely by a better loss distri- ancing resistors can be saved. The distribution of conduction
bution within the inverter. Simulation results prove the losses during the zero state can be controlled by the selection
superior performance of the loss-balanced inverter compared of the upper or lower NPC path. The conduction losses in the
to the conventional three-level NPC VSI. states “+“ and “-“can not be influenced.

- .

Fig. 3. Three-level NPC VSI with active NPC switches

1136
 TABLE II
SWITCH STATES OF THE DIODE-CLAMPED THREE-LEVEL NPc VsI
I ,TI..
11
-
T
122
-T3
13
-T4
14
I

State “+“ 1 1 0 0
State “0‘ 0 1 1 0
I write ‘ -*‘ I nn l nn l 1i l 1i l

TABLE III
SWITCH STATES OF THE THREE-LEVEL VsJ APPLYING ACTIVE NPC SWITCHES

Fig. 4. Commutations to the upper NPC path at positive phase

current (+ t)0, + t)0U2, + t)OU1)
State “OL2“ 1
State “-“ 1 0 1 0 1 1 1 1 1 1 1 0

B . Commutations
The commutations to or from the new states “OUT’, “OUl”,
“OLI” and “OL2” determine the distribution of the switching
losses. All commutations take place between one active
switch and one diode. Even if more than two devices turn on
or off, only one active switch and one diode experience
essential switching losses. The other devices that are toggled
do not simultaneously take over blocking voltage and carry
current during the commutation.
The conventional commutation + + 0 without use of the Fig. 5. Commutations to the lower NPC path at positive phase
current (+ t+ 0L2, + ++ OL1)
active NPC switches is recapitulated first. As an example
assume an operating condition with a positive phase current
turning off T2 slightly delayed to T I the entire phase current is
and positive output voltage. The inverter phase leg is
forced to the lower path of the neutral tap (which is already
switched from the positive dc rail (state ”+”) to the neutral tap
conducting) without significant additional losses (see Fig. 5).
(zero states). In the conventional diode-clamped inverter TI is
During the commutation + + OL1 the phase current also
turned off and T3 is turned on after a dead time. The current
commutates to the lower NPC path. In contrast to the
commutates from TI to D5. The switches T2 and T4 stay on
commutation described before TI remains in on-state. Only T2
and off, respectively. Essential switching losses occur in TI
is turned off and T3 is turned on after a dead time. The phase
(see Fig. 4).
current commutates directly to the lower NPC path. Switch T2
The four possible forced commutations from “+” to the experiences switching losses (see Fig. 5).
zero states utilizing the active NPC switches are investigated
For a better understanding the natural commutations from
subsequently. During the commutation + + OU2 the phase
the zero states back to “+” are also explained briefly. During
current commutates to the upper path of the neutral tap. First
all forced commutations described above only one active
T6 has to be turned off, then TI is turned off and finally (after
switch is subject to essential switching losses. During the
a dead time) T5 is turned on. As in the conventional commu-
natural commutations one active switch and one diode experi-
tation, TI experiences switching losses (see Fig. 4). The com-
ence essential switching losses. All switching transitions take
mutation + + OU1 differs from the commutation + + OU2
place in reverse order. During the commutation OU2 + + the
only by the additional lossless turn-on of T4. This additional
switch TS is turned off first. The phase current commutates to
switching transient does not yield any positive effect. There-
the positive dc rail after the turn-on of T,. Finally T6 is turned
fore the commutation is not used.
on. Switching losses occur in TI and DS. The commutation
By the commutation + + OL2 the phase current is OU1 4 + is initiated by the turn-off of T4 and T5. Following
commutated to the lower path of the neutral tap. TI is turned TI and T6 are turned on after a dead time. This commutation
off and T3 is turned on after a dead time. Since T6 is in on- is only used at the transition from the modulation of a nega-
state the current commutates to both upper and lower path of tive voltage to the modulation of a positive voltage. Switching
the neutral tap. TI experiences notable turn-off losses. By losses occur also in T1 and D5.

1137
 TABLE IV Junction temperatures
of all semiconductors
DEVICE SWITCHING LOSSES IN THE THREE-LEVEL VsI APPLYING ACTIVE Semiconductor Thermal
NPc SWITCHES loss converter
approximations model

4 4
PWM-
Modulator
Switch
vector_
7
Temperature
and switch
control unit -4
- On-line
calculation
of switching and
conduction losses
--c
On-line
calculation
of junction
temperatures
-

t tt t
Gate sianals of all I DC-link
1 Cooling
water
semiconductors 4 currents 1 I voltages I temperature

Fig. 6. B l o c k diagram of the loss-balancing system

A loss-balancing system to achieve the desired goal is

depicted in Fig. 6. Semiconductor losses and junction tem-
peratures are calculated on-line based on built-in loss and
thermal models [3]. As phase currents, dc-link voltages and
cooling water temperature are monitored anyway, no addi-
tional sensors are necessary. The temperature and switch
control unit realizes a given voltage vector, commanded by
the overlaid PWM or DTC control. It selects appropriate zero
During the commutation OL2 + + the switch T2 is turned states and commutations to achieve an optimal junction
on first, followed by turn-off of T3. Not till the final turn-on of temperature distribution and it generates the corresponding
TI the phase current commutates back to the positive dc rail. gate signals. The entire control system can be implemented
Essential switching losses occur in T I and D3. The commuta- using only two additional components. A micro controller is
tion OL1 + + is started by the turn-off of T3. The current well suited for all on-line calculations. Time critical tasks as
commutates after T2 is turned on. Switching losses occur in T2 the generation of the gate signals are taken over by an
and Dj. additional FF'GA.
Summarizing the above descriptions one can distinguish An algorithm for selecting the most suitable commutations
between three different types of commutations with respect to and zero states as a function of the junction temperatures is
losses. Switching losses occur in TI and D5 during the given in Table V. It ensures that the semiconductor with the
commutation + H OU2 (type 1). Utilizing the commutation highest instantaneous junction temperature is not stressed
+ H OL2 instead, switching losses are shifted from the NPC with significant switching losses. Conduction losses are not
diode D5 to the inner inverse diode D3 (type 2). Furthermore, reflected in this algorithm. If the conduction losses are much
the switching losses of TI can be shifted to T2 applying the larger than the switching losses, e.g. at zero speed with low
commutation + w OL1 (type 3). Analogously the mechanism switching frequency, this algorithm may fail to relieve the
of these three types of commutations applies for all operating hottest device. However, in all operating conditions where the
conditions. Table IV shows the distribution of switching conduction losses alone do not heat up one device to the
losses for all commutations. highest junction temperature, the algorithm yields the most
equal junction temperature distribution possible. The algo-
111. ACTIVELOSS-BALANCING
SYSTEM rithm requires a fast computation and decision making for
every second commutation. This can be accomplished by
The different commutations and zero states can be used to today's micro controllers, but is not required necessarily. As
distribute losses more evenly. Specifically, in cases 1 and 3 of an alternative one could define two discrete factors giving the
Table I, where the outer devices are most critical, junction ratio for the use of the three different types of commutations.
temperatures of the outer and inner devices can be equalized Slowly computed average junction temperatures can adapt
by alternately utilizing type 1- and type 3-commutations. In these factors.
cases 2 and 4, where the inner or NPC devices face the
highest losses, their junction temperatures can be equalized The proposed principle can be applied to virtually all
by alternately utilizing the type 1- and type 2-commutations. modulation schemes. The modulation itself, i.e. output volt-
Thus, always the hottest device is held as cool as possible. It age, zero sequence, current ripple etc., are not affected.
shall be noted, that the intention is not to save total inverter Hence, the modulation can be optimized with respect to other
losses, but to equally distribute losses. Total losses remain important constraints, e.g. torque ripple or dc-link capacitor
nearly unchanged. voltage balancing. On-line calculation of semiconductor

1138
 TABLE V
without loss balancing
DECISION CHART FOR COMMUTATIONS TO THE ZERO STATES

vlodulation Phase Junction temperatures E r 0 State /applying loss balancing

current 60
Positive iPll > 0
55
voltage
(+ + 0) 50
45

40
37

Negative Fig. 7 . Average junction temperatures at max. modulation depth M

voltage with and without loss balancing (Eupec 3.3kV 1200A IGBTs,
(- + O )
u&=34Oov, Ir",~600A,f~1050HZ, M=l. 15, pF=I, 6az37Oc)

70

i?/q without loss balancing\

60

55

50
losses and junction temperatures with similar goals is also 45
known from [4] and [5]. In [4] a reduction of the switching
frequency and/or the phase current is proposed in case the 40
junction temperature of one device exceeds its limit. A 37
combination of the loss-balancing system with this approach Toui Dout Tin Dm Tnpc Dnpc
is the logical and straightforward solution for optimally
Fig. 8. Average junction temperatures at low modulation depth M
utilized NPC inverters. with and without loss balancing (Eupec 3.3kV 1200A IGBTs,
ud,=3400v, I,~600A,f,=1050H~,M a . 0 1 , f F = l , &=37OC)
RESULTS
IV. SIMULATION
in Fig. 7 and the NPC diodes D, in Fig. 8, is larger in the
To verify the analytical considerations and to quantify the case of low modulation depth (Fig. 8). This yields a particu-
benefits of the proposed system extensive simulations were larly high improvement at zero speed.
performed for a typical industrial inverter with Uu=2.3kV
and Zr,,=600A utilizing Eupec 3.3kV, 1200A IGBTs. A single The control system is especially advantageous for IGBT
inverter phase with loss-balancing system was implemented in inverters, in which the output power is limited by thermal
MATLAB. A natural-sampled sine-triangle modulation with constraints and not by current turn-off capability. The
co-phasal carrier signals (PD PWM [ 6 ] )was assumed. Pa- balanced loss distribution enables a substantially increased
rameters given in the IGBT datasheet [7] were used, together output power without any additional semiconductor expense.
with a Eupec heatsink KW51 (R,hh-o=6K/kW at a water flow Fig. 9 shows the junction temperatures at rated operation with
rate of vM~6.21iter/min). an increased phase current of Zr,,=720A as a function of time.
As expected, the devices observed experience losses during
For applications with repetitive cyclic duty, reliability con- the positive half wave of the phase current and cool down
straints limit the maximum junction temperature rise of the during the negative half wave. The commutations of type 1
IGBTs to ATJ=30K [8]. Hence, an ambient temperature (TI-Ds) and type 3 (T2-D3) occur alternately. The average
&,=37"C yields a maximum average junction temperature of junction temperature of TI and T2 is fij=67"C. The maximum
1!l.,,,,,=67~C. junction temperature ripple at h,=,=SOHzdoes not exceed 6K.
Fig. 7 and 8 show the balanced junction temperature distri- If the phase current is limited by the semiconductor current
bution at the operating points of Fig. 1 and 2. One can easily turn-off capability still a large increase of switching frequency
observe that the junction temperature of the hottest device is is beneficial. The effective improvements are summarized in
reduced at the expense of the alternative switching device. Fig. 10. An overall increase of the output power by 20% can
The relief of the hottest devices, that are the outer IGBTs To,, be achieved. Alternatively an increase of switching frequency

1139
 800 1

.-
0 10 20 time I ms 40 Conventional Loss-balanced
inverter operation
1 Fig. 10. Gain of achievable rms phase current in a 2.3kV inverter
utilizing Eupec 3.3kV 1200A IGBTs due to active loss balancing
0.5
performance at negligible additional cost. Nevertheless, its
application is not limited to these cases. Installation of addi-
0
tional active NPC switches together with the proposed loss-
balancing system is a very attractive solution also in IGCT
-0.5
inverters for MVD applications where high torque at zero
speed is required, such as in hot or cold rolling mills.
-1

0 10 20 time I ms 40
ACKNOWLEDGMENT
Fig. 9. Junction temperatures vs. time applying loss balancing The authors thank R. Teichmann of Dresden University of
(Eupec 3.3kV 1200A IGBTs, Udc=3400V, 1 , ” ~ 7 2 0 Af,~ 1 0 5 0 H z , Technology for valuable advice and discussion.
fJlfo=21, M = l . l , PF=I, &=37”C)

from 1050Hz (frequency ratiofJ’=21) to 1950Hz (fslIf0=39)is REFERENCES

possible. The improvements at zero speed are even larger. For A. Nabae, I. Takahashi, H. Akagi, “A new neutral-point-clamped
operation at rated switching frequency the maximum output PWM inverter,” IEEE Trans. Ind. Applications, vol. 17, no. 5, 198 I
power is more than doubled. Applying a reduced switching A. Mertens, M. Bruckmann, R. S o w e r , “Medium voltage inverter
frequency of lOOHz the rated current of a conventional three- using high-voltage IGBTs,” EPE Conf. Rec., Lausanne, 1999
level NPC VSI is reached. A derating is no longer necessary. F. Blaabjerg, J. K. Pedersen, S. Sigurjbnsson, A. E l k j a , “An extended
model of power losses in hard-switched IGBT-inverters,” IAS Annual
Meeting Conf. Rec., San Diego, 1996
V. CONCLUSION V. Blasko, R. Lukaszewski, R. Sladky, “On line thermal model and
thermal management strategy of a three phase voltage source
The paper investigates the use of active NPC switches in inverter,” IAS Annuul Meeting Con$ Rec., Phoenix, 1999
the three-level NPC voltage source inverter. The analysis R. Kriimmer, T. Reimann, G. Berger, J Petzoldt, L. Lorenz, On-line
“

shows that the distribution of junction temperatures among calculation of the chip temperature of power modules in voltage
the semiconductors can be balanced applying optimum switch source conveners using the microcontroller,” EPE Con5 Rec.,
Lausanne, 1999
states and commutations. Based on this a loss-balancing
B. P. McGrath, D.G. Holmes, “A comparison of multicamer PWM
system is introduced featuring a substantial increase of the strategies for cascaded and neutral point clamped multilevel
inverter output power or switching frequency. In the example inverters,” PESC Conf. Rec., Galwayilreland, 2000
being examined a 20% higher output power or 85% higher -, Datasheet I 2 1200 R 33 -2. Tech. Informarion IGBT-Modules,
switching frequency can be achieved. Where active NPC Eupec, 1999
switches are already built in (like in many IGBT inverters) the Y. Shakweh, “Critical assessment of HV power devices for MV PWM
proposed control system will notably improve the converter VSI converters,” EPE Conf. Rec., Lausanne, 1999

1140