Introduction to

CMOS VLSI
Design

Logical Effort Part B

Original Lecture by Jay Brockman
University of Notre Dame Fall 2008
Modified by Peter Kogge Fall 2010,2011,2015, 2018
Based on lecture slides by David Harris, Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html

Logical Effort B Slide 1

Review: Motivating Example

 Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a 16x32 register file. A[3:0] A[3:0]
32 bits
4:16 Decoder

16 words

 Decoder specifications: Register File

16

– 16 word register file

– Each word is 32 bits wide
– Each file bit presents load of 3 unit-sized transistors
– Both true & complementary address inputs A[3:0] available
– Each address input may drive 10 unit-sized transistors
 Ben needs to decide:
– How many stages to use in decoder driver output buffers?
– How large should each gate be?
– How fast can decoder operate?

Logical Effort B CMOS VLSI Design Slide 2

1
Review: Ideal Gate Delay 
 Imagine ideal unit inverter (no parasitic diffusion
capacitance & unit on resistance) driving identical
inverter

2C
X
2 2C 2 R 2C

C
1 1C
X 1 R
C

 = 3RC = Ideal Inverter Delay

Logical Effort B CMOS VLSI Design Slide 3

Review: Linear Delay Model

delay d = p + f = p + hg
Prior delay had two parts
 p: Parasitic delay due to internal diffusion capacitance of gate
– 3RC for inverter
– Independent of load = sum of diffusion caps
 f: Effort delay due to load capacitance of gates being driven
– 3h RC when driving h unit inverters
– Proportional to total load capacitance
 = h*g if driving identical circuits (copies of itself)
– h = # of copies of gate (also called “Fanout”)
– g = “Logical Effort” (function of gate complexity)
• 3RC for inverter
Logical Effort B CMOS VLSI Design Slide 4

2
Review: Normalized Linear Delay
 Remember
– 3RC = parasitic delay of unit inverter
– 3RC + 3hRC = delay if driving h inverter copies

 Normalized delay: divide delay by 3RC

– Measure of how much “slower” a circuit is than
an inverter
–=1 + h for inverter driving h identical inverters

Logical Effort B CMOS VLSI Design Slide 5

Determining Logical Effort

 Logical effort g: ratio of input capacitance of a gate
to input capacitance of an inverter delivering the
same output current (pullup/down resistance).
 Measured from delay vs. fanout plots
 Or estimate by counting transistor widths
– AND divide by 3 to “normalize” to unit inverter
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3

Question: does g change if we scale all the transistors wided?

Logical Effort B CMOS VLSI Design Slide 6

3
 Summary: (p.156)
Number of inputs
Gate Type 1 2 3 4 N
Inverter 3 1 1
NAND 4 2 4/3 5 3 5/3 6 4 6/3 N+2 N (N+2)/3
NOR 5 2 5/3 7 3 7/3 9 4 9/3 2N+1 N (2N+1)/3
TriState/mux 2 2 4 2 6 2 8 2 2N 2
XOR, XNOR 4 4,4 6 6,12,6 8 8,16,16,8
(x,y,z) = Input Cap,  p,  g

All inputs are not the same!

Parasitic: delay driving 0 load (divided by 3RC)
Logical effort: Input Cap of gate / Input Cap of inverter of same current

Logical Effort A CMOS VLSI Design Slide 7

Delay Plots
d =f+p
= gh + p Inverter
6
Normalized Delay: d

4 g =1
p =1
3 d =h + 1
Lets take our invertor:
•d=h+1 2 Effort Delay: f

• p = 1 (y-intercept) 1
Parasitic Delay: p
• g = 1 (slope) 0
0 1 2 3 4 5

Electrical Effort:
h = Cout / Cin

What does “Normalized Delay” mean to designer?

Logical Effort B CMOS VLSI Design Slide 8

4
 2 input NAND
Remember we normalize
d =f+p by unit inverter 3RC
2-input
= gh + p NAND Inverter
6

Normalized Delay: d
g=
5 p=
d=
4 g=1
p=1
3 d=h+1
2

0
0 1 2 3 4 5

Electrical Effort:
h = Cout / Cin

Logical Effort B CMOS VLSI Design Slide 9

More 2 input NAND

d =f+p
2-input
= gh + p NAND Inverter
6
g = 4/3
NormalizedDelay:d

5 p=2
d = (4/3)h + 2
4 g=1
p=1
3 d = h +1

2 EffortDelay:f

1
Parasitic Delay: p
0
0 1 2 3 4 5

ElectricalEffort:
h = Cout / Cin

Logical Effort B CMOS VLSI Design Slide 10

5
 3 Input NAND

Logical Effort B CMOS VLSI Design Slide 11

Eg: Ring Oscillator (p.158)

 Estimate the frequency of an N-stage ring oscillator
– N odd

Each Stage:
Logical Effort: g=1
31 stage ring oscillator
Electrical Effort:
h=1
• 65nm process (3ps delay) = 2.7GHz
Parasitic Delay:p=1
• 0.6 m process ~ 200 MHz
Stage Delay: d = (1 + h) = (1 + 1) = 2
Total delay: Nd = 2N (normalized)
= 2Dτ (in seconds)
Overall Frequency: fosc = 1/(2Nτ)

Logical Effort B CMOS VLSI Design Slide 12

6
 Example: FO4 Inverter
 Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g=
Electrical Effort: h=
Parasitic Delay: p=
Stage Delay: d=

Logical Effort B CMOS VLSI Design Slide 13

Example: FO4 Inverter

 Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g=1

Electrical Effort: h=4
The FO4 delay is approximately
Parasitic Delay: p=1
• 200 ps in 0.6 m process
Stage Delay: d=5
• 60 ps in a 180 nm process
• f/3 ns in an f m process

Logical Effort B CMOS VLSI Design Slide 14

7
 Drive (p.159)
 Most libraries have multiple versions of common gates
– Named <gate-type>_#x
 Versions differ by “size” of transistors
– Denoted by # in name
– Called the gate version’s drive
• Relative to unit inverter
 Drive x = Cin / g
 Thus delay = Cout / x + p
 Question: what’s speed difference between
– nand2_1x
– nand2_3x

Logical Effort B CMOS VLSI Design Slide 15

(p. 160) (180 nm process)

_1 delay driving h _1 inverters

= 20 + 3.6*h*3.45 ps

XL=“Low Power” = 20 + 12.4h ps

Xi = drive of i

Input
cap Parasitic delay = (25.3 + 14.6)/2 = 20ps

τ = 12.4ps
pinv = 20ps = (20/12.4)τ
= 1.6 in normalized terms
Average (4.53+2.37)/2 = 3.45ns/pf

Logical Effort B CMOS VLSI Design Slide 16

8
 (p. 160) (180 nm process)
• Lets look at A input
• Parasitic delay = (31.3+19.5)/2
= 25.4ps
• Cin = 4.2fF
• Kload = (4.53+2.84)/2 ns/pF
= 3.69 ns/pF
= 3.69 ps/fF
• tpd = 25.4 +4.2*3.69*h ps
= 25.4 + 15.5*h ps Input Cap
Why the difference?
• Normalizing by inverter 12.4ps
• p = 25.4/12.4 = 2.05
• g = 15.5/12.4 = 1.25
• versus 4/3 = 1.33 from model

Logical Effort B CMOS VLSI Design Slide 17

(p. 161)
Limitations to Linear Delay Model
 Input & output slopes:
– not square
 Input arrival times: complex interactions
– when 2 or more inputs change at same time
 Velocity Saturation:
– We assume N transistors in series must be N times wider
– But series transistors see less velocity saturation
• & hence less resistance
 Voltage Dependencies:
– τ ~ V* VDD/(VDD – VT)α
 Gate/Source Dependencies:
– We assumed gate caps terminate on a fixed rail
– In reality to “middle” of channel
 Bootstrapping:
– Transistors have “gate to drain” capacitance
– Causes input to output “lifting”

Logical Effort B CMOS VLSI Design Slide 18

9
 Bootstrapping
Real-world: some cap from gate to drain

Logical Effort B CMOS VLSI Design Slide 19

Delay in
Multi-Stage Circuits

Logical Effort B CMOS VLSI Design Slide 20

10
A Sample Multi Stage Circuit

B
45
A
p=2 Table C
Lookup
90
g=4/3
h=15/4 Why?
Number of inputs
Gate Type 1 2 3 4 N
Inverter 3 1 1
NAND 4 2 4/3 5 3 5/3 6 4 6/3 N+2 N (N+2)/3
NOR 5 2 5/3 7 3 7/3 9 4 9/3 2N+1 N (2N+1)/3
TriState/mux 2 2 4 2 6 2 8 2 2N 2
XOR, XNOR 4 4,4 6 6,12,6 8 8,16,16,8

(x,y,z) = Input Cap,  p,  g
Logical Effort B CMOS VLSI Design Slide 21

Scaling Transistors
 What if all transistors in gate G got wider by k?
– Denote as gate “G(k)”
 Parasitic delay of G(k): delay of unloaded gate
– Diffusion capacitance increases by k
– Resistance decreases by k
– Result: No change
 Effort delay: ratio of load cap to input cap
– If drive same # of G(k) as before, no change
– If drive same # of G(1) as before, decrease by 1/k
– If drive k times as many G(1), no change
 Result: fanout to type G(1) gates increases by k
 YOU CAN DRIVE MORE GATES AT SAME SPEED!
– OR DRIVE SAME GATES FASTER
Logical Effort B CMOS VLSI Design Slide 22

11
 Design Question
 Given a signal path thru multiple gates
– Of different types
– And different #s on each output
 How do we select transistor scale factors?

 Answer: analyze/select “input capacitance”

– And then adjust transistor scaling to give you that
value

Logical Effort B CMOS VLSI Design Slide 23

MultiStage Logic Networks

(p. 163)
Relative Input Capacitance
(based on gate design & transistor size)

FIG 4.29

gi = logical effort to drive a gate of type i = input cap/cap of inverter

hi = fanout of gates of type i = load cap/input cap

Logical Effort B CMOS VLSI Design Slide 24

12
 Question
 If delay thru one gate is p + hg,

 Can we simplify multistage to

something like P+HG?

Logical Effort B CMOS VLSI Design Slide 25

Overall Delay
 delay thru circuit = ∑delay(i)
– where delay(i) = delay thru i’th “stage” of logic
 delay(i) = pi + hi * gi
– pi function only of gate type at stage i
– gi function only of gate type at stage i
• input cap/cap of inverter
– hi depends on connected gates at stage i+1
• total load on output of gate i/input cap of gate i
 Thus delay = ∑(pi + hi * gi ) = ∑(pi ) + ∑(hi * gi )
 Clearly P = ∑(pi )
 Can we write ∑(hi * gi ) as some H*G?

Logical Effort B CMOS VLSI Design Slide 26

13
 (p. 164)
Definitions
 Path Logical Effort G 
g i

 Path Electrical Effort Cout-path

H
Cin-path
 Path Effort F  f i   gi hi

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

Question: Can we write F = GH?

Logical Effort B CMOS VLSI Design Slide 27

Can We State F =GH?

Branch point
 No! Consider paths that branch:
– Not all load at one stage is on path to
output 15
90
 Individual terms
5
g1 = g2 = 1 (inverters)
h1 = (15 +15) / 5 = 6 15 Output
90
h2 = 90 / 15 = 6
 Path Terms
G = Πgi = 1x1 = 1 Question: What
H = Cout/Cin = 90 / 5 = 18 did GH overlook?
Thus GH = 18
Versus F = g1h1g2h2 = 36 = 2GH != GH
Logical Effort B CMOS VLSI Design Slide 28

14
 Branching Effort
 Introduce Branching Effort B
– Accounts for signal branching between stages in path

Con path  Coff path

b
Con path
B   bi h i  BH

 Now we compute the Path Effort F = GBH

 Or delay = P + GBH
Logical Effort B CMOS VLSI Design Slide 29

Redo
Branch point
 Individual terms
g1 = g2 = 1 (inverters)
h1 = (15 +15) / 5 = 6 15
90
h2 = 90 / 15 = 6 5
b1 = (15+15)/15 = 2
b2 = 90/90 =1 15
90
 Path Terms
G = Πgi = 1x1 = 1
H = Cout/Cin = 90 / 5 = 18 In this case:
B = 2x1 = 2 exact match
Thus GBH = 36
Versus F = g1h1g2h2 = 36!
Logical Effort B CMOS VLSI Design Slide 30

15
 Designing Fast
Multistage Circuits

Logical Effort B CMOS VLSI Design Slide 31

Designing Fast Circuits

D   d  D  P = ∑fi + ∑pi = P + F = P + GBH
i F

 D is Path Delay
 P is Path Parasitic Delay - independent of widths
 F is Path Effort
– G = Πgi = Path Logical Effort– ind. of width
– B = Branching Factor
– H = Coutpath/Cinpath = Path Electrical Effort
 To minimize ∑fi when GBH is constant:
– MAKE EACH STAGE HAVE SAME EFFORT f^
– For N stage circuit: f^ = (GBH)1/N
 Minimum possible delay = P + Nf^!!!!
Logical Effort B CMOS VLSI Design Slide 32

16
How Do We Find Gate Sizes
to Reach this Equal Effort?
 How wide should gates be for least delay?
 Typically Cin of first gate is pre-specified
 Working backward from load,
– apply transformation to find input fˆ  gh  g CCoutin
capacitance of each gate, given the load gi Couti
it drives.  Cini 
– Use this for the load capacitance on fˆ
previous stage
 Check work by verifying input cap spec i
 Then use input cap of each gate to size
each gate

Logical Effort C CMOS VLSI Design Slide 33

Example: 3-stage path

 Select input capacitance x and y for least delay from
A to B, given capacitance on A is 8C

y
x
45
A 8
x
y B
Input cap speced at 8C:
45
• Min size NAND gives Cin = 4C
• Thus scale widths 2X
• or n-type are 2X2 = 4 wide
• p-type are also 2x2 = 4 wide
Logical Effort C CMOS VLSI Design Slide 34

17
 Compute f^ & Delay
x

y
x
45
A 8
x
y B
45

Logical Effort G=
Electrical Effort H=
Branching Effort B=
Path Effort F=
Best Stage Effort fˆ 
Parasitic Delay P=
Delay D=

Logical Effort C CMOS VLSI Design Slide 35

Compute f^ & Delay

x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2 =6
Path Effort F = GBH = 125
Best Stage Effort f^ = 1251/3 = 5
Parasitic Delay P=2+3+2=7
Delay D = Nf^ + P
= 3*5 + 7 = 22

Logical Effort C CMOS VLSI Design Slide 36

18
 Work Backwards
 Work backward for sizes using Cin[i] = Cout[i]*gi/f^
y=
x=

y
x
45
A 8
x
y B
45

Logical Effort C CMOS VLSI Design Slide 37

Work Backwards
 Work backward for sizes using Cin[i] = Cout[i]*gi/f^
y = 45 * (5/3) / 5 = 15

y
x
45
A 8
x
y B
45

Logical Effort C
CMOS VLSI Design Slide 38

19
 Work Backwards
 Work backward for sizes using Cin[i] = Cout[i]*gi/f^
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

y15
x
45
A 8
x
y15 B
45
Load = 30

Logical Effort C
CMOS VLSI Design Slide 39

Work Backwards
 Work backward for sizes using Cin[i] = Cout[i]*gi/f^
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10
A = (10+10+10)*(4/3)/5 = 8 AND IT CHECKS!

x10

y15
x10
45
A 8
x10
y15 B
45
Load = 30

Logical Effort C
CMOS VLSI Design Slide 40

20
 Size Last Gate
 Now size last stage: x = 15
– 2 input NOR has unit input cap of 5
 To get an input cap of 15=> widths 15/5 = 3X unit!
– => p-type are 3*4 = 12 wide
=> n-type are 3*1 = 3 wide

45
A 8
P: 12
15 B
N: 3 45

Logical Effort C CMOS VLSI Design Slide 41

Size Middle Gate

 Now size 2nd stage 3 input NAND
y = 10;
– unit input cap of 5 => widths 10/5 = 2X unit!
– p:n ratio of 2:3 => p-type are 2*2 = 4 wide
=> n-type are 3*2 = 6 wide

45
A 8 P: 4
10 P: 12
N: 6 15 B
N: 3 45

Logical Effort C CMOS VLSI Design Slide 42

21
 Size First Gate
 Now size 1st stage
Cin = 8; 2 input NAND has
– unit input cap of 4 => widths 8/4 = 2X unit!
– p:n ratio of 1:1 => p-type are 2*2 = 4 wide
=> n-type are 2*2 = 4 wide

45
A P: 4
8 P: 4
10
N: 4 N: 6 P: 12 B
15
N: 3 45

Logical Effort C CMOS VLSI Design Slide 43

Checking Delay
 Let’s check delay
– d1 = g1h1 + p1 = {(10+10+10)/8}*(4/3) + 2 = 7
– d2 = g2h2 + p2 = {(15+15)/10}*(5/3) + 3 = 8
– d3 = g3h3 + p3 = {45/15}*(5/3) + 2 = 7
– delay = 7 + 8 + 7 = 22
– in 65nm process τ = 3ps, so circuit is 22*3 = 66ps

45
A P: 4 P: 4
8
N: 4 10
N: 6 P: 12 B
15
N: 3 45

Logical Effort C CMOS VLSI Design Slide 44

22
 What If We Try to Tweak?
 What if we made stage 2 even bigger (to be faster)
– d2 = g2h2 + p2 = {(15+15)/15}*(5/3) + 3 = 6.3 (faster)
– but d1 = g1h1 + p1 = {(15+15+15)/8}*(4/3) + 2 = 9.5 (slower)
– and d3 = g3h3 + p3 = {45/15}*(5/3) + 2 = 7 (no change)
– delay = 9.5 + 6.3 + 7 = 22.8 > 22 – SLOWER CIRCUIT

45
A P: 4 P: 6
8
N: 4 15
N: 9 P: 12 B
15
N: 3 45

Logical Effort C CMOS VLSI Design Slide 45

Choosing Best # of Stages

 Many logic functions have multiple possible circuits
(topologies)
 Goal: select topology, est. delay, & size transistors
 We know in general
– NANDs better than NORs
– Gates with fewer inputs better than more inputs
 Typical shortcut: estimate delay by # of stages
– Assuming constant “gate delay”
– and thus shorter paths are faster
 THIS IS NOT ALWAYS TRUE!
– Eg: Adding inverters at end with increasing
sizes can speed up circuit, esp. when high load

Logical Effort C CMOS VLSI Design Slide 46

23
 Example (p. 166)
 How many stages should a path use?
– Minimizing number of stages is not always fastest
 Example: drive 64-bit datapath with unit inverter
– Each bit eqvt to unit inverter in load

InitialDriver 1 1 1 1

DatapathLoad 64 64 64 64

N: 1 2 3 4
f:
D:

Logical Effort C CMOS VLSI Design Slide 47

Best Number of Stages

 How many stages should a path use?
– Minimizing number of stages is not always fastest
 Example: drive 64-bit datapath with unit inverter
InitialDriver 1 1 1 1

8 4 2.8

H = 64
16 8
G=1
F = HG = 64 23

D = NF1/N + P DatapathLoad 64 64 64 64
= N(64)1/N + N
N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

Logical Effort C CMOS VLSI Design Slide 48

24
 General Derivation
 Consider adding inverters to end of n1 stage path
– How many give least delay?
N - n1 ExtraInverters
Logic Block:
n1 n1Stages

D  NF   pi   N  n1  pinv
1
N Path Effort F

i 1
D 1 1 1
N total stages with (N-n1)
  F ln F N  F N  pinv  0
N

N 1
Inverters
• do not change logical effort
 Define best stage effort   F N • do add parasitic delay

pinv   1  ln    0

Logical Effort C CMOS VLSI Design Slide 49

Best Stage Effort

 pinv   1  ln    0 has no closed-form solution

 Neglecting parasitics (pinv = 0), we find  = 2.718 (e)

 For pinv = 1, solve numerically for  = 3.59

 Again,
– these ρ values are best logical effort per stage

^
– when you have N = logρ F stages

Logical Effort C CMOS VLSI Design Slide 50

25
 Sensitivity Analysis
 How sensitive is delay to using exactly the best
number of stages? 1.6
1.51

D(N) /D(N)
1.4
1.26
1.2 1.15
1.0

(=6) ( =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N = actual N vs optimal N
 2.4 <  < 6 gives delay within 15% of optimal
– We can be sloppy!
– Book likes  = 4

Logical Effort C CMOS VLSI Design Slide 51

1st Example, Revisited

 Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file. A[3:0] A[3:0]
32 bits
4:16 Decoder

16 words

 Decoder specifications: 16
Register File

– 16 word register file

– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
 Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?

Logical Effort C CMOS VLSI Design Slide 52

26
 What Does This Mean?
 16 word register file
– There are 16 separate row lines
– Branching factor of 16 at end
 Each word is 32 bits wide & each bit presents load
of 3 unit-sized transistors
– The load on each row line is 32*3 = 96
 True and complementary address inputs A[3:0]
– Any address input needed for only 8 row lines
 Each input may drive 10 unit-sized transistors
– Total input capacitance from 1st stage gates on
inputs = 10

Logical Effort C CMOS VLSI Design Slide 53

Number of Stages
 Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8

 If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8

Number of Stages: N = log4F = 3.1

 Try a 3-stage design

Logical Effort C CMOS VLSI Design Slide 54

27
 3 Stage Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 2*8*9.6 =154
Stage Effort: fˆ  F 1/ 3  5.36
Path Delay: D  3 fˆ  1  4  1  22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10
Inverter=>NAND=>Inverter

y z word[0]

96 units of wordline capacitance

y z word[15]

Logical Effort C CMOS VLSI Design Slide 55

Comparison
 Compare many alternatives with a spreadsheet

Design N G P D
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
Fastest
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

Logical Effort C CMOS VLSI Design Slide 56

28
 Review of Definitions

Term Stage Path

number of stages 1 N
logical effort g G   gi
Cout-path
electrical effort h Cout
Cin
H Cin-path
Con-path Coff-path
branching effort b Con-path B   bi
effort f  gh F  GBH

effort delay f DF   f i

parasitic delay p P   pi
delay d f p D   d i  DF  P

Logical Effort C CMOS VLSI Design Slide 57

Method of Logical Effort

1) Compute path effort
F  GBH
2) Estimate best number of stages
3) Sketch path with N stages N  log 4 F
4) Estimate least delay 1

5) Determine best stage effort D  NF N  P

fˆ  F N
1

6) Find gate sizes gi Couti

Cini 
fˆ

Logical Effort C CMOS VLSI Design Slide 58

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 Limits of Logical Effort
 Chicken and egg problem
– Need path to compute G
– But don’t know number of stages without G
 Simplistic delay model
– Neglects input rise time effects
 Interconnect
– Iteration required in designs with wire
 Maximum speed only
– Not minimum area/power for constrained delay

Logical Effort C CMOS VLSI Design Slide 59

Summary
 Logical effort is useful for thinking of delay in circuits
– Numeric logical effort characterizes gates
– NANDs are faster than NORs in CMOS
– Paths are fastest when effort delays are ~4
– Path delay is weakly sensitive to stages, sizes
– But using fewer stages doesn’t mean faster paths
– Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
 Provides language for discussing fast circuits
– But requires practice to master

Logical Effort C CMOS VLSI Design Slide 60

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