300Mhz-To-450Mhz Low-Power, Crystal-Based Ask Transmitter: General Description Features
300Mhz-To-450Mhz Low-Power, Crystal-Based Ask Transmitter: General Description Features
300Mhz-To-450Mhz Low-Power, Crystal-Based Ask Transmitter: General Description Features
Features
2.1V to 3.6V Single-Supply Operation Low 5.3mA Operating Supply Current* Supports ASK with 90dB Modulation Depth Output Power Adjustable to More than +10dBm Uses Small Low-Cost Crystal Small 3mm 3mm 8-Pin SOT23 Package Fast-On Oscillator 220s Startup Time
MAX1472
*At 50% duty cycle (315MHz, 2.7V supply, +10dBm output power)
Applications
Remote Keyless Entry RF Remote Controls Tire Pressure Monitoring Security Systems Radio-Controlled Toys Wireless Game Consoles Wireless Computer Peripherals Wireless Sensors
PART MAX1472AKA-T
Ordering Information
TEMP RANGE -40C to +125C PINPACKAGE 8 SOT23-8 TOP MARK AEKS
Pin Configuration
XTAL1 1 GND 2
8 7
3 PAGND
MAX1472
PAGND 3 6 5 PAOUT 4
STANDBY OR POWER-UP
4 PAOUT
ENABLE 5
SOT23
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, output power is referenced to 50, VDD = 2.1V to 3.6V, VENABLE = VDD, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYSTEM PERFORMANCE Supply Voltage VDD VENABLE = VDD (Note 2) fRF = 315MHz VENABLE = VDD, VDATA = VDD VENABLE = VDD, VDATA = 0V VENABLE = VDD (Note 2) fRF = 433MHz VENABLE = VDD, VDATA = VDD VENABLE = VDD, VDATA = 0V Standby Current Frequency Range Data Rate Modulation Depth Output Power POUT ISTDBY fRF VENABLE < VIL, TA < +85C (Note 3) VENABLE < VIL TA < +125C (Note 3) (Note 1) (Note 3) ON to OFF POUT ratio (Note 4) TA = +25C, VDD = 2.7V (Notes 8, 9) TA = +125C, VDD = 2.1V (Notes 8, 9) TA = -40C, VDD = 3.6V (Notes 8, 9) Turn-On Time Transmit Efficiency with CW Transmit Efficiency at 50% Duty Cycle tON To fOFFSET < 50kHz (Note 5) To fOFFSET < 5kHz (Note 5) fRF = 315MHz (Note 6) fRF = 433MHz (Note 6) fRF = 315MHz (Note 7) fRF = 433MHz (Note 7) 7.3 3.3 300 0 90 10.3 6.0 13.7 220 450 43.6 41.3 37.6 35.1 16.2 s % % 12.8 dBm 2.1 5.3 9.1 1.5 5.7 9.6 1.7 5 2.5 350 1.7 450 100 nA A MHz kbps dB 3.6 9.2 16.4 2.1 mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current
IDD
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MAX1472
100% tested at TA = +25C. Guaranteed by design and characterization over temperature. 50% duty cycle at 10kHz data. Guaranteed by design and characterization, not production tested. Generally limited by PC board layout. VENABLE < VIL to VENABLE > VIH. fOFFSET is defined as the frequency deviation from the desired carrier frequency. VENABLE > VIH, VDATA > VIH, Efficiency = POUT/(VDD x IDD). VENABLE > VIH, DATA toggled from VIL to VIH, 10kHz, 50% duty cycle, Efficiency = POUT/(VDD x IDD). Output power can be adjusted with external resistor. Guaranteed by design and characterization at fRF = 315MHz.
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1.9 1.8 SUPPLY CURRENT (mA) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 +25C -40C VENABLE = VIH, VDATA = VIL, fRF = 315MHz +85C +125C
13
+25C
+125C +85C
2.0
2.4
2.8
3.2
3.6
2.0
2.4
2.8
3.2
3.6
2.0
2.4
2.8
3.2
3.6
+125C
14
-25C
+25C
1.8
+125C +85C
-40C
8 7 6
2.0
2.4
2.8
3.2
3.6
-65 -67 -69 REFERENCE SPUR (dBc) -71 -73 -75 -77 -79 -81 -83 -85 2.0 2.4 2.8 3.2 433MHz 315MHz
55 50 EFFICIENCY (%) 45 40 35 +85C 30 25 +125C CW OUTPUT fRF = 315MHz 2.0 2.4 2.8 3.2 -40C +25C
3.6
2.0
2.4
2.8
3.2
3.6
3.6
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MAX1472
50 -40C +25C
45
45 EFFICIENCY (%)
+25C
40 +125C 35 +85C
30 +85C 25
+125C
+125C OOK OUTPUT AT 50% DUTY CYCLE fRF = 315MHz 2.8 3.2 3.6
30
2.0
2.4
-40 -50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 -140 10 100 1k 10k fOFFSET (Hz) 100k 1M
fRF = 315MHz
12 10 8 6 4 2
10
CURRENT
10M
0.1
10
100
0 1000
EXTERNAL RESISTOR ()
AM DEMODULATION OF PA OUTPUT
MAX1472 toc17
25kHz/div
ENABLE TRANSITION FROM LOW TO HIGH START: 0s 1ms ENABLE TRANSITION FROM LOW TO HIGH START: 0s 1ms START: 0s 15%/div
2.5kHz/div
STOP: 20s
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Detailed Description
The MAX1472 is a highly integrated OOK/ASK transmitter operating over the 300MHz to 450MHz frequency range. The IC includes a complete PLL and a highly efficient PA. The device can also be easily placed into a 5nA low-power shutdown mode.
Power Amplifier
The PA of the MAX1472 is a high-efficiency, open-drain, class-C amplifier. With proper output matching network, the PA can drive a wide range of impedances, including the small-loop PC board trace antenna and any 50 antenna. The output-matching network for a 50 antenna is shown in the Typical Application Circuit. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 4), which is about 250 . When the output matching network is properly tuned, the PA transmits power with high efficiency. The Typical Application Circuit delivers 10.3dBm at 2.7V supply with 9.1mA of supply current. Thus, the overall efficiency is 44%. The efficiency of the PA itself is more than 52%.
Shutdown Mode
The ENABLE pin is internally pulled down with a 15A current source. If the pin is left floating or pulled low, the MAX1472 goes into shutdown mode, where the supply current drops to less than 5nA. When ENABLE is high, the IC is enabled and is ready for transmission after 220s (frequency settles to within 50kHz). The 220s turn-on time of the MAX1472 is mostly dominated by the crystal oscillator startup time. Once the oscillator is running, the 1.6MHz PLL loop bandwidth allows fast-frequency recovery during power-amplifier toggling.
Applications Information
Output Power Adjustment
It is possible to adjust the output power down to -10dBm with the addition of a resistor. The addition of the power-adjust resistor also reduces power consumption. See the Supply Current and Output Power vs. External Resistor and Supply Current vs. Output Power graphs in the Typical Operating Characteristics section. It is imperative to add both a low-frequency and a high-frequency decoupling capacitor as shown in the Typical Application Circuit.
Phase-Locked Loop
The PLL block contains a phase detector, charge pump, integrated loop filter, VCO, 32X clock divider, and crystal oscillator. This PLL requires no external components, other than a crystal. The relationship between the carrier and crystal frequency is given by: fXTAL = fRF / 32 The lock-detect circuit prevents the PA from transmitting until the PLL is locked. In addition, the device shuts down the PA if the reference frequency is lost.
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Output Matching to 50
When matched to a 50 system, the MAX1472 PA is capable of delivering more than +10dBm of output power at VDD = 2.7V. The output of the PA is an opendrain transistor that requires external impedance matching and pullup inductance for proper biasing. The pullup inductance from PA to VDD serves three main purposes: It resonates the capacitance of the PA output, provides biasing for the PA, and becomes a high-frequency choke to reduce the RF energy coupling into VDD. The recommended output-matching network topology is shown in the Typical Application Circuit. The matching network transforms the 50 load to a higher impedance at the output of the PA in addition to forming a bandpass filter that provides attenuation for the higher order harmonics.
MAX1472
where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. Ccase is the case capacitance. Cspec is the specified load capacitance. Cload is the actual load capacitance. When the crystal is loaded as specified, i.e., Cload = Cspec, the frequency pulling equals zero.
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Functional Diagram
DATA ENABLE AND GATE VDD
MAX1472
PA PAOUT
Chip Information
TRANSISTOR COUNT: 1430 PROCESS: CMOS
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MAX1472
SYMBOL A A1 A2 b C D E E1 L L2 e e1
MIN 0.90 0.00 0.90 0.28 0.09 2.80 2.60 1.50 0.30
MAX 1.45 0.15 1.30 0.45 0.20 3.00 3.00 1.75 0.60 0.25 BSC.
C L
C L
E1
L2 A A2 A1
SEATING PLANE C
GAUGE PLANE
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF HEEL OF THE LEAD PARALLEL TO SEATING PLANE C. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING. 5. COPLANARITY 4 MILS. MAX. 6. PIN 1 I.D. DOT IS 0.3 MM MIN. LOCATED ABOVE PIN 1. 7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP. 8. MEETS JEDEC MO178.
DETAIL "A"
21-0078
1 1
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SOT23, 8L .EPS