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Reference Material 2

The document summarizes the general register organization in a CPU. It contains 7 registers that are connected through a common bus. There are 2 multiplexers (MUX) that select a register or external data for the A and B inputs of an arithmetic logic unit (ALU). The ALU operation is selected by an operation selector. The result is directed to a destination register selected by a decoder. A control word with 14 selection bits controls the MUXes, ALU operation, and register decoder. An example shows how a register addition operation is encoded in the control word.

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Hardik Pandya
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41 views8 pages

Reference Material 2

The document summarizes the general register organization in a CPU. It contains 7 registers that are connected through a common bus. There are 2 multiplexers (MUX) that select a register or external data for the A and B inputs of an arithmetic logic unit (ALU). The ALU operation is selected by an operation selector. The result is directed to a destination register selected by a decoder. A control word with 14 selection bits controls the MUXes, ALU operation, and register decoder. An example shows how a register addition operation is encoded in the control word.

Uploaded by

Hardik Pandya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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General Register

Organization
General Register Organization
• Intermediate data are needed to be stored like pointers,
counters, return address, temp results, and partial
products.
• Cannot save them in main memory because their access
is time consuming.
• It is more efficient and faster to be stored inside
processor.
• So the solution is designing multiple registers inside
processor and connects them through a common bus
General Register
Organization Clock Input

R1
R2
R3
R4
R5
R6
R7

Bus organization for 7 CPU


Load
registers: (7 lines)
SELA MUX MUX SELB

2 MUX
3×8 A bus B bus
BUS A and BUS B decoder

ALU
SELD Arithmetic logic unit
OPR
3 X 8 Decoder (ALU)

Output
(a) Block diagram

3 3 3 5
SELA SELB SELD OPR
(b) Control word
8-2. General Register
Organization
 Bus organization for 7 CPU registers:
 2 MUX: select one of 7 register or external data input by SELA
and SELB
 BUS A and BUS B : form the inputs to a common ALU
 ALU : OPR determine the arithmetic or logic microoperation
 The result of the microoperation is available for external data
output and also goes into the inputs of all registers
 3 X 8 Decoder: select the register (by SELD) that receives the
information from ALU
General Register Organization
• An operation is selected by the ALU operation
selector (OPR).
• The result of a microoperation is directed to a
destination register selected by a decoder (SELD).
• Control word: The 14 binary selection inputs (3 bits
for SELA, 3 for SELB, 3 for SELD, and 5 for OPR)
Example 1 R1  R2  R3
Binary selector input
1)MUX A selector
(SELA) : to place the
content of R2 into BUS A
2)MUX B selector
(SELB) : to place the
content of R3 into BUS B
3) ALU operation
selector (OPR) : to
provide the arithmetic
addition R2 + R3
4) Decoder selector
(SELD) : to transfer the
content of the output bus
into R1
Encoding of Register Selection Fields:
»SELA or SELB = 000 (External Input) : MUX selects the external data
»SELD = 000 (None) : no destination register is selected but the
contents of the output bus are available in the external output
References
• Computer System Architecture by Morris Mano

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