K.

SIVASANKARAN, Lecturer, VLSI / ESD Division, SES,VIT

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In this session session

Evolution of CAD Design. Emergence & Features of HDL History Verilog HDL. g Verilog Basics Introduction to levels of Modeling.

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The first Integrated Circuit (IC) or silicon chip was fabricated in 1960s. 1960s IC chip evolution -> SSI, MSI, LSI, VLSI VLSI

Designing single chip with more than 100,000 100, transistors - VLSI. VLSI.

Complicated design processes. processes.

Traditional / conventional design method includes manual translation of design description into logical equations and then to schematic. schematic.
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Verification through bread-boarding? breadCAD (back-end) tools became critical (backcritical.

Graphic packages (PSpice, Workbench, OrCAD) for gate l level / schematic representation. l h i i Cannot handle higher complexities. P Poor portability. t bilit Poor readability for high complex designs. In all the above design methods the functional bugs cannot be identified till the design is implemented in g p hardware, and hence the design time is very long.

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Logic Simulators for verifying functionality thus removing functional bugs at an early stage in the design. g High level languages such as FORTRAN, PASCAL, C, C++, etc., are sequential in nature. , , , , q Digital designers felt the need for a standard language to describe digital systems / hardware. g g g y Hardware Description Languages (HDLs) comes into existence and these have special constructs to p model the concurrency of processes found in digital systems.

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HDL?
In electronics, a hardware description language , p g g or HDL is any language from a class of computer languages for formal description of electronic circuits. It can describe the circuit's operation, its design, and tests to verify its operation by means of simulation Popular HDLs are Verilog HDL & VHDL (for any complexity).

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Easy development, verification and debugging through HDLs. HDL descriptions are easily portable, and is also compatible to all design tools. p g HDLs can describe the digital systems at various abstraction levels & also supports hi b t ti l l l t hierarchical hi l modeling. HDL descriptions can be functionally simulated with Logic Simulators .
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Advent of Logic synthesis tools in late 1980s pushes HDLs to the forefront of digital design. Digital circuits described at Register Transfer Level (RTL) using HDLs can also be synthesized HDLs, through automated logic synthesis tools. Logic Synthesis tools can extract gate level details automatically from HDL (RTL) description. p Analog HDLs.
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Developed by Philip Moorby in 1984-1985. 1984Gateway Design Automation introduced Verilog in 1984 as their proprietary HDL. Cadence took over in 1989. Cadence made Verilog HDL public in 1990 1990. Verilog HDL becomes IEEE 1364-1995. 136412/15/2008

Verilog HDL is modeled after C language. Allows different levels of abstraction to b mixed i All diff tl l f b t ti t be i d in the same model. Easy to learn and easy to use. Almost all logic simulation & synthesis tools support Verilog. pp g Verilog HDL is an IEEE 1364 standard.
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White space Operators Comments Number specification Strings Identifiers and Ke words Keywords Escaped Identifiers
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Comprise of the white space. p p Blank spaces ---> ---> Tabs New lines ---> ---> ---> ---> \b \t \n

White space is not ignored in strings.

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Broadly classified as: unary operators. operates on a single operand. Ex: out = ~ a; p g p ; binary operators. operates on two operands. Ex: out = a && b; ternary operators operators. operates on three operands. Ex: out = s ? a : b;
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Improve readability and helps good documentation. I d bili dh l dd i Two comment structures are available in verilog: single / one line comment z = x + y; // arithmetic operation p multiple line / block comment /* this logic performs the reversal of bits */ Multiple line comments cannot be nested. / /* This is /* a wrong / comment */ structure */
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Verilog HDL is case-sensitive. caseAll the keywords in Verilog must be in lower case. Verilog constructs may be written across multiple lines, or on one line.

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Identifiers and keywords are used to define language constructs. Identifiers refer objects to be referenced in the design. Identifiers are made of alphabets ( p (both cases), ), numbers, the underscore _ and the dollar sign $. They start with an alphabetic character or underscore.
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They cannot start with a number or with $ which is reserved for system tasks. Identifiers are case sensitive i.e., identifiers differing in their case are distinct. An identifier say count is different from COUNT, COUNT count and cOuNT. cOuNT

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Count COUNT _R2_D2 R2 D2 R56_68 FIVE$ $count 12six_b 12 i b

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Example: reg sum; input data;

Illegal Illegal Ill l

Sized numbers. <size> <base format> <number> Unsized numbers. <base format> <number> <b f t> < b > <size> in decimal <base format> can be b or B, d or D, o or O and h or H. Numbers without <base format> are decimal by default. default
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Examples: Sized numbers : 4'b1111 // This is a 4-bit binary number 412'habc // This is a 12-bit hexadecimal number 1216'd255 // This is a 16-bit decimal number. 16Unsized numbers : 23456 // This is a 32-bit decimal number by default 32y 'hc3 // This is a 32-bit hexadecimal number 32o21 32'o21 // This is a 32-bit octal number
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X or x for unknown values. Z or z for high impedance values. o o g peda ce a ues. X or Z at the MSB has the self padding property.

Examples: 32 B z // this is a 32-bit high impedance number 326 h X // this is a 6-bit hex number h 612 H 13x // this is a 12-bit hex number 1212/15/2008

5037 4D2 7Hx 7H 4hz 4d4d-4 8 h 2A

5-bit octal 4-bit decimal 7-bi x (x extended), i.e. xxxxxxx bit ( d d) i 4-bit z (z extended), i.e zzzz Not l N t legal l Spaces allowed between size & character & between base and value 3 b001 Not legal: no space allowed between and base b 10b10 Padded with 0 to the left, 0000000010 3b1001_0011 is same as 3b011
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A string is a sequence of characters that are enclosed by double quotes. Verilog classes are very interesting??? Spaces are not ignored in strings. Strings cannot be on multiple lines.

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A module is a basic building block in Verilog and can specify a system of any complexity. The module definition is the same for a system of any complexity complexity. Provides functionality through its port interface. interface. It can be an element or a collection of lower-level lowerdesign (macro or leaf cells or primitive cells) blocks.

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Components of a V il Module C t f Verilog M d l

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COUNTER

Modules M d l Module / Primitive

T_FF (tff0)

T_FF (tff1)

D_FF D FF

NOT

D_FF D FF

NOT

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A module in Verilog is declared using the keyword module and a corresponding keyword endmodule must appear at the end of the module. Each module must have a module name, which acts as an identifier. A module can have an optional port list which describes the input output & inout terminals of input, the module.
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module ex1( ); endmodule

module ex2(y,a,b,c,d); ex2 y a b c d) y,a,b,c,d d) output y; input a,b,c,d; p a,b,c,d; , , , wire f1,f2; ,f2 or o1(f1,a,b) (f1 and a1(f2,c,d); (f2,c,d); xor x1(y,f1,f2); (y,f1,f2 endmodule d d l
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Module name: ex1 No. of ports: 0 No

Module name: ex2 No. of ports: 5

In Verilog nesting of modules is not permitted i.e., one module definition cannot contain another module definition within th module and d l d fi iti ithi the d l d endmodule statements. module counter(q clk, reset); counter(q, clk output [3:0]q; input clk, reset; p

module T_FF(q, clock, reset) // Illegal . endmodule endmodule

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A module provides a template from which one can create actual objects. Each object has its own name, variables, parameters and I/O interface interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. Primitives and modules can be instantiated.
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ex1 and ex2 as objects

Module ex1
module templates p

in top module

Top module Module ex1 Primitive 1 Module ex2 Primitive 2

Module ex2

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Data Types

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Value Set Nets Registers R i t Vectors

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Verilog has to model the functionality of the real hardware condition in circuits. For this we have Value Set ---- 0, 1, x/X, z/Z. , , / , / 0 --> Logic 0 / False condition --> 1 --> Logic 1 / True condition --> X --> Unknown / dont care --> Z --> High impedance value / floating state -->
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Nets represent connections / physical wires between hardware elements. Nets will not store / hold any value. Nets are declared with keyword wire. y wire. Default Size : 1-bit / scalar 1Default Value : z
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wire a; // signal a declared as wire wire out; // signal out declared as wire Ex: assign out = a | b; or o1(out, a, b); wire a, b; // signals a & b declared as wires wire d = 1b0; /*net b is fixed to logic value 0 at declaration*/ declaration /
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In Verilog registers represent data storage elements. Used to model hardware memory elements / registers. Registers can h ld / store a value. R i hold l Declared by the keyword reg. reg. Default Size : 1-bit / scalar D f lt Si 1l Default Value : x

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reg p; reg w,y; g y reg reset; g ; initial begin g reset = 1 b1; //initialize reset to 1 #100 reset = 1 b0; / after 100 times units reset b0; /* is de asserted*/ end
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Nets or register data types can be declared as vectors (more no. of bits). If bit width is not specified then the default value is 1-bit (scalar). wire a; // default scalar net value wire [7:0] bus; // 8-bit bus 8wire [31:0] busA, busB, busC; //32- bit bus //32reg clock; // scalar register(default) g reg [0:40] virtual_addr; //virtual address 41 bits
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wire [15:0]busA; [ ]; busA[9]; // bit # 9 or 10th bit of vector busA from LSB wire [0:15]busB; busB[9]; // bit # 9 or 7th bit of vector busB from LSB reg [31:0]cnt_out; cnt_out[14:7]; // group of 8 bits of a vector register [ ] g g cnt_out[7:14]; // is illegal addressing
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Integers g
Integer values are declared by the keyword g y y integer. integer. Store the values as signed quantities. Default width is host machine specific, at least 3232-bits wide. integer count;

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Reals
Real values are declared with the keyword real. y Either decimal or scientific notation can be used. When real value is assigned to an integer number the real number gets rounded off to the nearest integer. real delta;
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Times
A special time register data type is used to store the simulation time. Default width is host machine specific, at least 64 p bits wide. The $ $time captures the current simulation time, at which it has been invoked. time sim_time; initial sim_time = $time;
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Arrays y
Arrays are allowed for reg, integer, time data reg, integer, types. yp Arrays are not allowed for real variables. y A vector is a single element that is n-bits wide, narrays are multiple elements that are 1-bit or n-bits 1nwide. Multidimensional arrays are not allowed in y Verilog.
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Arrays y
Arrays declared as: data t d t type < l <element size> array name < t i > <no. of f elements> Arrays are accessed as: <array name> [< b i t>] < > [<subscript>] reg [ 0]bl k[3 0] [15:0]block[31:0]; reg [7:0]mem[1023:0]; //realizing 1KB memory
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Parameters
Used to define constants. Keyword parameter. parameter. The parameter cannot be used as variables and should not modify their value at run time. h ld dif h i l i Often the states of a FSM are parameterized. parameter PERIOD = 30; always #PERIOD clk_out = ~ clk_out;
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The operators can be : arithmetic logical relational equality bit wise reduction d i shift concatenation t ti replication conditional
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Expressions constitute operators and operands. Operators O t arithmetic operators operation i symbol b l operand d multiply divide add subtract modulus
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* / + %

binary binary binary binary binary

Eg: a * b // multiply a and b a / b // divide a by b a+b // add a and b a - b // subtract b from a a%b // modulus of a by b a=3b011 b=3b010 d=4 e=3 c=a * b // c= 3b110 c= a / b // c= 1 c= a+b // c= 3b101 +b c= a-b // c=3b001 ac=d/e // c=1
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13 % 4 // evaluates to 1. -9 % 2 // evaluates to -1 takes sign of the 1, first //operand

In arithmetic operations, if any operand bit has a value x, then the result of the entire expression is x. , p The size of the result is determined by the size of the largest operand.

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Logical operator evaluates always to a one bit value either ( ) g ) y p true(1) or false ( ) or x ( (0) (unambiguous) . If any operand bit is either x or z it is equivalent to x operation logical and logical l i l or logical not symbol && || ! operand binary binary bi unary

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a1 = 1b0; // 0 is false; a2 = 1 b1; // 1 is true 1b1; a1 && a2 is 0 (false) 1 2 i (f l ) a1 || a2 is 1 (true) !a2 is (f l ) ! 2 i 0 (false) For vector operands, a non-zero vector is treated nonas logical 1.
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eg: a=10 b=00 a 10 b 00 a && b !a // evaluates to 0 ( 1 && 0) l t t // evaluates to 0 (not of 1)

a=2b1x b=2b11 a || b // is unknown, evaluates to x.

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Relational operations return logical 0 or 1. If there is any x or z bit in operand then it will return x. operation
greater less_than greater_ than_or_equal_to less_than _or_equal_to

symbol
> < >= <=

operand
binary binary binary binary

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a = 5 b = 6 c = 21x a >b // evaluates to 0 a <= b // evaluates to 1 b >= c // evaluates to x

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Equality operators are the following operation logical equality logical inequality case equality lit case inequality symbol == != === !== operand binary binary binary bi binary

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Equality operator can return 1 or 0. Logical equality operator (== !=) will return x if any of the operand bit has x. Case equality operator compares both operand bit by bit including x and z bit If it matches then returns 1 or bit. else it returns 0. It doesnt return x. doesn t

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Contd Contd
a=3; b=5; c=3b100; d=3b101; e=4b1xxx; f=4b1xxx; g=3b1xxz a !=b // evaluates to 1. e===f // evaluates to 1. g f===g // evaluates to 0. d == e // evaluates to x

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Bitwise operations are performed on each bit of the operand operation bitwise and bitwise or bitwise negation bitwise bit i xor bitwise xnor
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symbol & | ~ ^ ~^ or ^~

operand binary binary unary binary bi binary

module fulladd_1(sum,carry,a,b,c); input a,b,c; a b c; output sum,carry; wire sum,carry; assign sum = (a^b )^ c; assign carry = (a&b) | (b&c) | (c&a); endmodule
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a = 3b111; c c c c c = = = = = ~a; a & b; a & b; a ^ b; a|d d;

b = 3b101; d = 3b1x1;

// c = 3b000 // c = 3b101 // c = 3 b111 3b111 // c = 3b010 // c = 3b1 1 3b1x1

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Reduction operators are unary operators operation symbol operand i b l d reduction and & unary reduction nand ~& unary reduction or | unary reduction nor ~| unary reduction xor d ti ^ unary reduction xnor ~^ or ~^ unary
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x = 4b01100 c = &x c = |x // c= 0 & 1&1&0&0 // c= 0|1|1|0|0 c=0 c=1 c=0

c = ^x // c=0^1^1^0^0

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Shift operator can be shift left or shift right

operation
shift right shift left hf l f

symbol
>> <<

operand
unary unary

eg: a = 4b1011; y = a >> 2; // y =4b0010, 0s filled in MSB y = a << 2; // y = 4b1100, 0s filled in LSB
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Concatenation operator is used to append multiple operands. lti l d The operand must be sized. sized. a=3b101; b=3b111; y = {a,b}; // y = 6b101111 y = {a,b,3b010}; // y =101111010

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Replication operator is used to concatenate same number. b a=3 b101 a=3b101 b =2 b10 =2b10 y = {2{a}}; // result of y is 6b101101 6 b101101 y = {2{a},2{b} }; // result of y is 10b1011011010 y = { 2{a} 2b10}; // result of y is 6 b10110110 2{a},2 b10}; 6b10110110

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Conditional operator ? : format: o at at: format: conditional_expr ? true expr : false expr; eg: assign out = control ? I1 : l2; control 1 0
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out I1 I2

module mux_con(out,s0,s1,i); input s0,s1; i t 0 1 input [3:0]i; output out; wire out; assign out = s1 ? ( s0 ? i[3]:i[2]) : (s0 ? i[1]:i[0]) ; endmodule
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+-~! */% +<< >> < <= > >= & ~& ^ ~^ ^ | ~| && || ?:

unary arithmetic binary shift relational reduction and , nand d ti reduction exor, exnor reduction or , nor logical and logical or conditional

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A design block needs to be tested for its functionality by applying stimulus and checking results.

For testing the design block, a stimulus block or test bench can be created in Verilog itself.

In the test bench we provide some stimulus to the corresponding inputs of the design module module.

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Stimulus Block Instantiates Design Block

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Levels Le els of Modeling

Data Flow Modeling. Behavioral Modeling g Structural Modeling

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Levels Le els of Modeling

Behavioral or algorithmic level:
This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming programming.

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Contd Contd
Dataflow level
At this level the module is designed by level, specifying the data flow. The designer is aware of how data flows between hardware registers g and how the data is processed in the design.

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Contd Contd
Gate level
The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a g g design in terms of a gate-level logic diagram. gate-

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