M27V160

16 Mbit (2Mb x8 or 1Mb x16)

Low Voltage UV EPROM and OTP EPROM

■ 3V to 3.6V LOW VOLTAGE in READ

OPERATION
■ ACCESS TIME: 100ns
■ BYTE-WIDE or WORD-WIDE
44
CONFIGURABLE 42

■ 16 Mbit MASK ROM REPLACEMENT

1 1
■ LOW POWER CONSUMPTION
FDIP42W (F) SO44 (M)
– Active Current 30mA at 8MHz
– Standby Current 60µA
■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V
■ PROGRAMMING TIME: 50µs/word
■ ELECTRONIC SIGNATURE
42
– Manufacturer Code: 20h
– Device Code: B1h 1

PDIP42 (B)
DESCRIPTION
The M27V160 is a low voltage 16 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and Figure 1. Logic Diagram
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage. It is organised as either 2 Mbit
words of 8 bit or 1 Mbit words of 16 bit. The pin-out
is compatible with a 16 Mbit Mask ROM.
VCC
The M27V160 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
20
of the battery or an increase in the time between Q15A–1
battery recharges. A0-A19
15
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex- Q0-Q14
pose the chip to ultraviolet light to erase the bit pat- E M27V160
tern. A new pattern can then be written rapidly to
the device by following the programming proce- G
dure.
For applications where the content is programmed BYTEVPP
only one time and erasure is not required, the
M27V160 is offered in PDIP42 and SO44 packag-
es.
VSS
AI01898

March 2000 1/15

M27V160

Figure 2A. DIP Connections Figure 2B. SO Connections

NC 1 44 NC
A18 1 42 A19
A18 2 43 A19
A17 2 41 A8
A17 3 42 A8
A7 3 40 A9
A7 4 41 A9
A6 4 39 A10
A6 5 40 A10
A5 5 38 A11
A5 6 39 A11
A4 6 37 A12
A4 7 38 A12
A3 7 36 A13
A3 8 37 A13
A2 8 35 A14
A2 9 36 A14
A1 9 34 A15
A1 10 35 A15
A0 10 33 A16
M27V160 A0 11 34 A16
E 11 32 BYTEVPP M27V160
E 12 33 BYTEVPP
VSS 12 31 VSS
VSS 13 32 VSS
G 13 30 Q15A-1
G 14 31 Q15A-1
Q0 14 29 Q7
Q0 15 30 Q7
Q8 15 28 Q14
Q8 16 29 Q14
Q1 16 27 Q6
Q1 17 28 Q6
Q9 17 26 Q13
Q9 18 27 Q13
Q2 18 25 Q5
Q2 19 26 Q5
Q10 19 24 Q12
Q10 20 25 Q12
Q3 20 23 Q4
Q3 21 24 Q4
Q11 21 22 VCC
Q11 22 23 VCC
AI01899
AI01900

Table 1. Signal Names DEVICE OPERATION

A0-A19 Address Inputs The operating modes of the M27V160 are listed in
the Operating Modes Table. A single power supply
Q0-Q7 Data Outputs is required in the read mode. All inputs are TTL
Q8-Q14 Data Outputs compatible except for VPP and 12V on A9 for the
Electronic Signature.
Q15A–1 Data Output / Address Input Read Mode
E Chip Enable The M27V160 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
G Output Enable signal level on the BYTEVPP pin. When BYTEVPP
BYTEVPP Byte Mode / Program Supply is at VIH the Word-wide organisation is selected
and the Q15A–1 pin is used for Q15 Data Output.
VCC Supply Voltage When the BYTEVPP pin is at VIL the Byte-wide or-
ganisation is selected and the Q15A–1 pin is used
VSS Ground
for the Address Input A–1. When the memory is
NC Not Connected Internally logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at VIL the
lower 8 bits of the 16 bit data are selected and with
A–1 at VIH the upper 8 bits of the 16 bit data are
selected.

2/15
 M27V160

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes

Mode E G BYTEVPP A9 Q15A–1 Q14-Q8 Q7-Q0

Read Word-wide VIL VIL V IH X Data Out Data Out Data Out

Read Byte-wide Upper VIL VIL VIL X VIH Hi-Z Data Out

Read Byte-wide Lower VIL VIL VIL X VIL Hi-Z Data Out

Output Disable VIL V IH X X Hi-Z Hi-Z Hi-Z

Program VIL Pulse V IH V PP X Data In Data In Data In

Verify VIH VIL V PP X Data Out Data Out Data Out

Program Inhibit VIH V IH V PP X Hi-Z Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z Hi-Z

Electronic Signature VIL VIL V IH V ID Code Codes Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8
Identifier A0 and and and and and and and and Hex Data
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h

Device Code VIH 1 0 1 1 0 0 0 1 B1h

The M27V160 has two control functions, both of the output pins independent of device selection.
which must be logically active in order to obtain Assuming that the addresses are stable, the ad-
data at the outputs. In addition the Word-wide or dress access time (tAVQV) is equal to the delay
Byte- wide organisation must be selected. from E to output (tELQV). Data is available at the
Chip Enable (E) is the power control and should be output after a delay of tGLQV from the falling edge
used for device selection. Output Enable (G) is the of G, assuming that E has been low and the ad-
output control and should be used to gate data to dresses have been stable for at least tAVQV-tGLQV.

3/15
M27V160

Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit

1.3V
High Speed

3V 1N914

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit
Input Capacitance (except BYTEVPP) VIN = 0V 10 pF
C IN
Input Capacitance (BYTEVPP) VIN = 0V 120 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

Standby Mode a. the lowest possible memory power dissipation,

The M27V160 has a standby mode which reduces b. complete assurance that output bus contention
the active current from 20mA to 20µA with low volt- will not occur.
age operation VCC ≤ 3.6V, see Read Mode DC For the most efficient use of these two control
Characteristics table for details.The M27V160 is lines, E should be decoded and used as the prima-
placed in the standby mode by applying a CMOS ry device selecting function, while G should be
high signal to the E input. When in the standby made a common connection to all devices in the
mode, the outputs are in a high impedance state, array and connected to the READ line from the
independent of the G input. system control bus. This ensures that all deselect-
Two Line Output Control ed memory devices are in their low power standby
Because EPROMs are usually used in larger mode and that the output pins are only active
memory arrays, this product features a 2 line con- when data is required from a particular memory
trol function which accommodates the use of mul- device.
tiple memory connection. The two line control
function allows:

4/15
 M27V160

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ V CC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL, G = VIL, IOUT = 0mA,

30 mA
f = 8MHz, V CC ≤ 3.6V
ICC Supply Current
E = VIL, G = VIL, IOUT = 0mA,
20 mA
f = 5MHz, V CC ≤ 3.6V

ICC1 Supply Current (Standby) TTL E = VIH 1 mA

ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V, VCC ≤ 3.6V 60 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.2VCC V

VIH (2) Input High Voltage 0.7V CC VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA 2.4 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.

System Considerations put control and by properly selected decoupling

The power switching characteristics of Advanced capacitors. It is recommended that a 0.1µF ceram-
CMOS EPROMs require careful decoupling of the ic capacitor is used on every device between VCC
supplies to the devices. The supply current ICC and VSS. This should be a high frequency type of
has three segments of importance to the system low inherent inductance and should be placed as
designer: the standby current, the active current close as possible to the device. In addition, a
and the transient peaks that are produced by the 4.7µF electrolytic capacitor should be used be-
falling and rising edges of E. The magnitude of the tween VCC and VSS for every eight devices. This
transient current peaks is dependent on the ca- capacitor should be mounted near the power sup-
pacitive and inductive loading of the device out- ply connection point. The purpose of this capacitor
puts. The associated transient voltage peaks can is to overcome the voltage drop caused by the in-
be suppressed by complying with the two line out- ductive effects of PCB traces.

5/15
M27V160

Table 8. Read Mode AC Characteristics (1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
M27V160

Symbol Alt Parameter Test Condition -100 (3) -120 -150 Unit

Min Max Min Max Min Max

tAVQV tACC Address Valid to Output Valid E = VIL , G = VIL 100 120 150 ns

tBHQV tST BYTE High to Output Valid E = VIL , G = VIL 100 120 150 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL 100 120 150 ns

Output Enable Low to Output

tGLQV tOE E = VIL 50 60 60 ns
Valid

tBLQZ (2) tSTD BYTE Low to Output Hi-Z E = VIL , G = VIL 45 50 50 ns

tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 45 0 50 0 50 ns

Output Enable High to Output

tGHQZ (2) tDF E = VIL 0 45 0 50 0 50 ns
Hi-Z
Address Transition to Output
tAXQX tOH E = VIL , G = VIL 5 5 5 ns
Transition
tBLQX tOH BYTE Low to Output Transition E = VIL , G = VIL 5 5 5 ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed measurement conditions.

Figure 5. Word-Wide Read Mode AC Waveforms

A0-A19 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q15

AI00741B

Note: BYTEV PP = VIH.

6/15
 M27V160

Figure 6. Byte-Wide Read Mode AC Waveforms

A–1,A0-A19 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q7

AI00742B

Note: BYTEV PP = VIL.

Figure 7. BYTE Transition AC Waveforms

A0-A19 VALID

A–1 VALID

tAVQV tAXQX

BYTEVPP

tBHQV

Q0-Q7 DATA OUT

tBLQX
Hi-Z
Q8-Q15 DATA OUT

tBLQZ

AI00743C

Note: Chip Enable (E) and Output Enable (G) = VIL.

7/15
M27V160

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V)
Symbol Parameter Test Conditio n Min Max Unit
ILI Input Leakage Current 0 ≤ V IN ≤ VCC ±1 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

V IL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.4 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –2.5mA 3.6 V

VID A9 Voltage 11.5 12.5 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.

Table 10. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Valid to Chip Enable Low 2 µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

tVPHAV tVPS VPP High to Address Valid 2 µs

tVCHAV tVCS VCC High to Address Valid 2 µs

tELEH tPW Chip Enable Program Pulse Width 45 55 µs

tEHQX tDH Chip Enable High to Input Transition 2 µs

tQXGL tOES Input Transition to Output Enable Low 2 µs

tGLQV tOE Output Enable Low to Output Valid 120 ns

tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns

Output Enable High to Address

tGHAX tAH 0 ns
Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Programming cations. Although only ’0’s will be programmed,

The M27V160 has been designed to be fully com- both ’1’s and ’0’s can be present in the data word.
patible with the M27C160. As a result the The only way to change a ’0’ to a ’1’ is by die expo-
M27V160 can be programmed as the M27C160 sure to ultraviolet light (UV EPROM). The
on the same programming equipments applying M27V160 is in the programming mode when Vpp
12.75V on VPP and 6.25V on VCC by the use of the input is at 12.5V, G is at VIH and E is pulsed to VIL.
same PRESTO III algorithm. When delivered (and The data to be programmed is applied to 16 bits in
after each erasure for UV EPROM), all bits of the parallel to the data output pins. The levels required
M27V160 are in the ’1’ state. Data is introduced by for the address and data inputs are TTL. VCC is
selectively programming ’0’s to the desired bit lo- specified to be 6.25V ± 0.25V.

8/15
 M27V160

Figure 8. Programming and Verify Modes AC Waveforms

A0-A19 VALID

tAVEL

Q0-Q15 DATA IN DATA OUT

tQVEL tEHQX

BYTEVPP

tVPHAV tGLQV tGHQZ

VCC

tVCHAV tGHAX

tELEH tQXGL

PROGRAM VERIFY
AI00744

Figure 9. Programming Flowchart PRESTO III Programming Algorithm

The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 52.5 seconds. Pro-
VCC = 6.25V, VPP = 12.5V
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9).
n=0 During programing and verify operation a MAR-
GIN MODE circuit is automatically activated to
guarantee that each cell is programed with enough
E = 50µs Pulse
margin. No overprogram pulse is applied since the
NO verify in MARGIN MODE at VCC much higher than
3.6V provides the necessary margin to each pro-
++n NO
= 25 VERIFY ++ Addr grammed cell.
Program Inhibit
YES YES
Programming of multiple M27V160s in parallel
with different data is also easily accomplished. Ex-
Last NO cept for E, all like inputs including G of the parallel
FAIL Addr M27V160 may be common. A TTL low level pulse
YES applied to a M27V160’s E input and VPP at 12.5V,
will program that M27V160. A high level E input in-
CHECK ALL WORDS hibits the other M27V160s from being pro-
BYTEVPP =VIH grammed.
1st: VCC = 5V Program Verify
2nd: VCC = 3V
A verify (read) should be performed on the pro-
AI00901B grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
at VIH and G at VIL, VPP at 12.5V and VCC at
6.25V.

9/15
M27V160

On-Board Programming ERASURE OPERATION (applies to UV EPROM)

The M27V160 can be directly programmed in the The erasure characteristics of the M27V160 is
application circuit. See the relevant Application such that erasure begins when the cells are ex-
Note AN620. posed to light with wavelengths shorter than ap-
Electronic Signature proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
The Electronic Signature (ES) mode allows the
wavelengths in the 3000-4000 Å range. Research
reading out of a binary code from an EPROM that shows that constant exposure to room level fluo-
will identify its manufacturer and type. This mode
rescent lighting could erase a typical M27V160 in
is intended for use by programming equipment to
about 3 years, while it would take approximately 1
automatically match the device to be programmed
week to cause erasure when exposed to direct
with its corresponding programming algorithm.
sunlight. If the M27V160 is to be exposed to these
The ES mode is functional in the 25°C ± 5°C am-
types of lighting conditions for extended periods of
bient temperature range that is required when pro-
time, it is suggested that opaque labels be put over
gramming the M27V160. To activate the ES mode,
the M27V160 window to prevent unintentional era-
the programming equipment must force 11.5V to
sure. The recommended erasure procedure for
12.5V on address line A9 of the M27V160, with
M27V160 is exposure to short wave ultraviolet
VPP = VCC = 5V. light which has a wavelength of 2537 Å. The inte-
Two identifier bytes may then be sequenced from grated dose (i.e. UV intensity x exposure time) for
the device outputs by toggling address line A0 erasure should be a minimum of 30 W-sec/cm2.
from VIL to VIH. All other address lines must be The erasure time with this dosage is approximate-
held at VIL during Electronic Signature mode. ly 30 to 40 minutes using an ultraviolet lamp with
Byte 0 (A0 = VIL) represents the manufacturer 12000 µW/cm2 power rating. The M27V160
code and byte 1 (A0 = V IH) the device identifier should be placed within 2.5cm (1 inch) of the lamp
code. For the STMicroelectronics M27V160, these tubes during the erasure. Some lamps have a filter
two identifier bytes are given in Table 4 and can be on their tubes which should be removed before
read-out on outputs Q7 to Q0. Note that the erasure.
M27V160 and M27C160 have the same identifier
bytes.

10/15
 M27V160

Table 11. Ordering Information Scheme

Example: M27V160 -100 X M 1 TR

Device Type
M27

Supply Voltage
V = 3V to 3.6V

Device Function
160 = 16 Mbit (2Mb x 8 or 1Mb x 16)

Speed
-100 (1) = 100 ns
-120 = 120 ns
-150 = 150 ns

V CC Tolerance
blank = 3.3V ± 10%
X = 3.3V ± 5%

Package
F = FDIP42W (2)
B = PDIP42
M = SO44 (2)

Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C

Optio ns
TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

2. Packages option available on request. Please contact STMicroelectronics local Sales Office.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.

11/15
M27V160

Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A – 5.72 – 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 54.41 54.86 2.142 2.160
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 14.50 14.90 0.571 0.587
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 4.10 0.125 0.161
S 1.52 2.49 0.060 0.098
K 9.40 – – 0.370 – –
K1 11.43 – – 0.450 – –
α 4° 11° 4° 11°
N 42 42

Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline

A2 A3 A

A1 L α
B1 B e1 C
eA
D2
eB
D
S
N

K E1 E

1 K1
FDIPW-b

Drawing is not to scale.

12/15
 M27V160

Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.25 – 0.010 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.53 0.015 0.021
B1 1.27 1.65 0.050 0.065
C 0.20 0.36 0.008 0.014
D 52.20 52.71 2.055 2.075
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 0.86 1.37 0.034 0.054
α 0° 10° 0° 10°
N 42 42

Figure 11. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale.

13/15
M27V160

Table 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010
A2 2.25 2.35 0.089 0.093
B 0.50 0.020
C 0.10 0.25 0.004 0.010
D 28.10 28.30 1.106 1.114
E 13.20 13.40 0.520 0.528

e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° – – 3° – –
N 44 44
CP 0.10 0.004

Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Drawing is not to scale.

14/15
 M27V160

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

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