Basics of Semiconductor Devices

Dinesh Sharma
EE Department, IIT Bombay
September 9, 2021

chapterBasics of Semiconductor Devices In this booklet, we review the fundamentals of Semi-

conductor Physics and basics of device operation. We shall concentrate largely on elemental
semiconductors such as silicon or germanium, and most numerical values used for examples are
specific to silicon.

1 Semiconductor fundamentals
A semiconductor has two types of mobile charge carriers: negatively charged electrons and pos-
itively charged holes. We shall denote the concentrations of these charge carriers by n and p
respectively. The discussions in this booklet apply to elemental semiconductors (like silicon)
which belong to group IV of the periodic table. We can intentionally add impurities from groups
III and V to the semiconductor. These impurities are called dopants. Impurities from group III
are called acceptors while those from group V are called donors. Each donor atom has an extra
electron, which is very loosely bound to it. At room temperature, there is sufficient thermal
energy present, so that the loosely bound electron breaks free from the donor, leaving the donor
positively charged. This contributes an additional electron to the free charge carriers in the
semiconductor, and a positive ionic charge at a fixed location in the semiconductor. Similarly,
an acceptor atom captures an electron, thus producing a mobile hole and becoming negatively
charged itself. A semiconductor without any dopants is called intrinsic. An unperturbed semi-
conductor must be charge neutral as a whole. If we denote the concentration of ionised donors
by Nd+ and the concentration of ionised acceptors by Na− , we can write for the net charge density
at any point in the semiconductor as:

ρ = q(Nd+ − Na− + p − n) (1)

where q is the absolute value of the electronic charge. In an unperturbed semiconductor, ρ will
be zero everywhere. Electrons and holes are generated thermally - the availability of energy
equal to the band gap of the semiconductor results in the generation of an electron - hole pair.
Simultaneously, electrons and holes can recombine to annihilate each other, giving out energy
which is equal to the band gap of the semiconductor. Thus we have the reversible reaction:

e− + h+ ⇀
↽ Eg

Where Eg is the band gap energy of the semiconductor.

Applying the law of mass action to the above reaction, we can write for the equilibrium concen-

1
tration of holes and electrons:
n · p = constant
The above relation applies to doped as well as intrinsic semiconductors. But for an intrinsic
semiconductor,
n = p ≡ ni
Therefore, the constant in the equation connecting n and p must be n2i . Thus, for a semicon-
ductor in equilibrium,
n · p = n2i (2)
Since n and p are not independent, but are constrained by the above relation, we can define a
single independent variable, the Fermi potential by
KB T p KB T ni
ΦF ≡ ln = ln (3)
q ni q n
Where KB is the Boltzmann constant, T is the absolute temperature and q is the absolute value
of the electronic charge. At room temperature, KB T /q is approximately 26 mV and ni is of the
order of 1010 /cm3 for silicon. Now electron and hole concentrations are given by:
qΦF
−K
n = ni e BT
qΦF
p = ni e KB T (4)

To simplify these relations, we define a dimensionless Fermi potential by:

qΦF
uF ≡ = ln(p/ni ) = ln(ni /n)
KB T
then:

n = ni e−uF
p = ni euF (5)

Generally, a semiconductor will be doped with only one kind of impurity. A semiconductor
doped with donors will have many more electrons than holes. This type of semiconductor is called
N type, and electrons are the majority carriers in this type of semiconductor. Similarly, holes
are the majority carriers in a semiconductor doped with acceptors and it is termed P type. If
both types of dopants are present, the one present in higher concentration determines the ‘type’
of the semiconductor. The net doping is defined as the difference in the concentrations of the
more abundant and the less abundant dopants.
In most practical cases, the ratio of majority to minority carriers is very high. The concentra-
tion of majority carriers is very nearly equal to the net dopant concentration. To take a typical
example, consider P type silicon with boron concentration of 1016 atoms/cm3 . This gives:

p = Na = 1016 /cm3
n = n2i /p ≈ 1020 /1016 /cm3 = 104 /cm3
p/n ≈ 1012 !

2
1.1 Band Diagrams
The above concepts are often visualised with the help of band diagrams. The arrangement
of atoms in a semiconductor results in certain electron energies which are not permitted. Thus,
the energy range is divided into bands of permitted energy values alternating with forbidden gaps.

The highest such band which is nearly filled with electrons is called the valance band. Unoc-
cupied levels in this band correspond to holes. For stability, electrons seek the lowest energy level
available. If a vacancy is available at a lower energy - an electron at a higher energy will drop
to this level. The vacancy thus bubbles up to a higher level. Therefore, holes seek the highest
electron energy available.

The band just above the valance band is called the conduction band. In a semiconductor,
this is partially filled. Conduction in a semiconductor is caused by electrons in the conduction
band (which are normally to be found at the lowest energy in the conduction band) and holes in
the valance band - (found at the highest electron energy in the valance band).

EC

-qφF Ei
EF
EV

Figure 1: Semiconductor Bands

Band diagrams are plots of electron energies as a function of position in the semiconductor.
Typically, the top of the valance band (corresponding to minimum hole energy) and the bottom of
the conduction band are plotted. We can show the Fermi potential and the corresponding Fermi
energy(= -qΦF ) in the band diagram of silicon as a level in the band gap. We use the halfway
point between the conduction and the valence band as the reference for energy and potential.
When n = p = ni , the Fermi potential is 0 (from eq. 3) and correspondingly, the Fermi energy
lies at the intrinsic Fermi level halfway in the band gap. (Actually, this level can be slightly away
from the middle of the band gap depending on the density of allowed states in the conduction
and valance bands - but for now, we’ll ignore this). When holes are the majority carriers, ΦF is
positive and the Fermi energy (= -q ΦF ) lies below the mid gap level, as shown in figure 1. When
electrons are the majority carriers, ΦF is negative, and the Fermi energy lies above the mid gap
level.

1.2 A semiconductor in the presence of an electric field

In the presence of an electric field, the electrostatic potential is different at different positions.
The energy of an electron has an extra component = −qφ where φ is the electrostatic potential.
Consequently in the band diagram the conduction, valance and intrinsic levels are bent. In
equilibrium, the Fermi level is still straight. (We shall see later that in the absence of a current,
the slope of the Fermi level must vanish). Relations for n and p must now take the electrostatic
potential as well as the Fermi potential into account and the electron and hole concentrations

3
 V

EC

Energy Ei
-qφF
EF
EV

x
Figure 2: Potential distribution and Band Diagram in the presence of a field

are not uniform over the semiconductor. If we represent the concentrations of electrons and
holes without any applied field by n0 and p0 respectively, then in the presence of a field (but in
equilibrium),
qφ
n = n0 e KB T
− KqφT
p = p0 e B (6)

where φ is the electrostatic potential.

If we define a dimensionless electrostatic potential by:
qφ
u≡ (7)
KB T
we can write the above relations as:

n = n0 eu = ni e(u−uF )
p = p0 e−u = ni e−(u−uF ) (8)

Since there is equilibrium, even though electron and hole concentration is not uniform, the
product of n and p is still constant and equal to n2i everywhere.

1.3 Non-equilibrium case

The above relations assume a semiconductor in equilibrium. It is possible to create excess carriers
in the semiconductor over those dictated by equilibrium considerations. For example, if we shine
light on a semiconductor, electron-hole pairs will be created. Since the value of n as well as
that of p goes up, the np product will exceed n2i , till the equilibrium is restored after the light is
turned off (by enhanced recombination). If the number of excess carriers is small compared to the
majority carriers, we may assume that the carrier concentrations are still described by relations
like those given above. However, the concentrations of electrons and holes are not constrained by
relation(2) any more. Therefore, we cannot use the same value of uF for describing electron as
well as hole concentrations. We now have separate values of ΦF for electrons and holes. These are

4
called quasi Fermi levels (or imrefs) for electrons and holes, ΦFn and ΦFp , defined by the relations

n = ni e(u−uFn )
p = ni e−(u−uFp ) (9)

Where uFn and uFp are the dimensionless versions of quasi Fermi levels ΦFn and ΦFp defined as in
equation(7)). The np product is now given by

np = n2i e(uFp −uFn ) (10)

and is no longer constant. Because the number of additional carriers is assumed to be small
compared to the majority carriers, the concentration of majority carriers and hence its quasi
Fermi level is very close to the equilibrium value. The relative change in the concentration of
minority carriers could, however, be large and consequently the minority carrier quasi Fermi level
could be substantially different from the equilibrium Fermi level.

2 The p-n diode

We shall analyse the abrupt pn junction, in reverse and forward bias. We assume that the doping

Xdp Xdn

P N

N
Ec
EF
Ei
P
Ev

Figure 3: The abrupt p-n junction

density is constant and its value = Na on the P side and Nd on the N side, changing abruptly at
the metallurgical junction as shown. Because there is a strong concentration gradient for electrons
and holes at the junction, there will be a diffusion current of holes towards the N side and of
electrons towards the P side. As these carriers leave behind ionised dopants, small regions on
either side of the junction acquire a charge. The P side, from where positively charged holes have
left, (leaving behind negatively charge acceptor ions), acquires a negative potential. Similarly, the
N side becomes positively charged. The regions from where mobile charges have left, are called
depletion regions. The potential difference resulting from this charge redistribution (called the
built-in voltage) opposes further diffusion of carriers. A dynamic equilibrium is reached when the
drift current due to this potential difference and the diffusion current due to the concentration
gradient become equal and opposite. In equilibrium, The electron as well as hole currents must be
zero individually (principle of detailed balance). Writing the electron and hole current densities

5
as sums of their respective drift and diffusion current densities:
∂φ ∂n
Jn = nqµn (− ) + qDn
∂x ∂x
∂φ ∂p
Jp = pqµp (− ) − qDp (11)
∂x ∂x
From equation(9)

∂n ∂
= ni e(u−uFn ) (u − uFn )
∂x ∂x
∂p ∂
= ni e(uFp −u) (uFp − u)
∂x ∂x
or
∂n q ∂
= n (φ − ΦFn )
∂x KB T ∂x
∂p q ∂
= p (ΦFp − φ)
∂x KB T ∂x
Using Einstein relations ( KBq T D = µ), and Substituting in the relations for Jn and Jp ,

∂φ ∂
Jn = −nqµn ( ) + nqµn (φ − ΦFn )
∂x ∂x
∂φ ∂
Jp = −pqµp ( ) − pqµp (ΦFp − φ)
∂x ∂x
Which leads to
∂ΦFn
Jn = −nqµn ;
∂x
∂ΦFp
Jp = −pqµp ; (12)
∂x
When there is no flow of current, ΦFn = ΦFp = ΦF . according to the relations derived above, the
derivative of ΦF must vanish everywhere for zero current. Thus, the Fermi level is constant and
the same at the two sides of the junction. The Fermi potentials before being put in contact were:
KB T
ΦF = q
ln(Na /ni) P side : x < 0
ΦF = − KBq T ln(Nd /ni) N side : x > 0
 
KB T Nd N a
The Fermi potential difference was, therefore, q
ln n2i
. Since after being put in contact,
the Fermi levels have equalised on the two sides, the built in voltage must be equal and opposite
to this potential, taking the P side to a negative potential and the N side to a positive potential.
We can write for the magnitude of the built in voltage:
!
KB T Na Nd
Vbi = ln (13)
q n2i

6
2.1 pn Diode in Reverse Bias
The diode is reverse biased when we apply a voltage such that the n side is more positive as
compared to the p side. In this case, the applied voltage is in the same direction as the built-in
field, which opposes the movement of majority carriers and widens the depletion regions on either
side of the junction. We analyse the reverse biased diode by making the depletion approximation.
We assume that in reverse bias, the depletion regions have zero carrier density, and the field is
completely confined to depletion regions. Solving Poisson’s equation in P region (x < 0) and the
N region (x > 0)
∂2φ
2
= qNǫsi
a
(for x < 0)
∂x
∂2φ
= − qN
ǫsi
d
(for x > 0)
∂x2
Integrating with respect to x
∂φ
= qNǫsi
a
x + c1 (for x < 0)
∂x
∂φ
= − qN
ǫsi
d
x + c2 (for x > 0)
∂x
where c1 and c2 are constants of integration, which can be evaluated from the condition that the
field vanishes at the edge of the depletion regions at -Xdp and at Xdn . This leads to
∂φ
= qNǫsi
a
(x + Xdp ) (for x < 0)
∂x
∂φ
= − qN
ǫsi
d
(x − Xdn ) (for x > 0) (14)
∂x
Since the value of the field must match at x = 0;

Na Xdp = Nd Xdn (15)

Integrating equation (14) once again with respect to x, we get

 
qNa x2
φ = ǫsi 2
+ Xdp x + c3 (for x < 0)
 
x2
φ = − qN d
ǫsi 2
− Xdn x + c4 (for x > 0)

Where the constants of integration c3 and c4 can again be evaluated from the boundary conditions
at -Xdp and Xdn . If we require that the potential is 0 at -Xdp and V at Xdn ,
qNa 2
c3 = X
2ǫsi dp
qNd 2
c4 = V − X
2ǫsi dn
Substituting these values, we get:
 
qNa x2 +Xdp
2
φ = ǫsi 2
+ Xdp x (for x < 0)
 
qNd x2 +Xdn
2
φ =V − ǫsi 2
− Xdn x (for x > 0) (16)

7
Since the potential at x = 0 should be continuous,
qNa 2 qNd 2
Xdp = V − X
2ǫsi 2ǫsi dn
q 2 2
so, V = (Na Xdp + Nd Xdn ) (17)
2ǫsi
making use of equation (15), we can write
2
qNa Xdp
V = (Nd + Na )
2ǫsi Nd
2
qNd Xdn
= (Nd + Na )
2ǫsi Na
which leads to
s
2ǫsi V Nd
Xdp =
q(Nd + Na ) Na
s
2ǫsi V Na
Xdn = (18)
q(Nd + Na ) Nd
From which the total depletion width can be calculated as:
s s s !
2ǫsi V Nd Na
Xd ≡ Xdp + Xdn = +
q(Nd + Na ) Na Nd
which gives
s
2ǫsi V 1 1
 
Xd = + (19)
q Na Nd
The voltage V in the above expressions is the total voltage across the junction. Since there is a
reverse bias of Vbi for a zero applied voltage, that will add (in magnitude) to the applied reverse
voltage. Using equation(13) we can write:
!
KB T Na Nd
V = Vbi + Vappl = Vappl + ln (20)
q n2i

2.2 The pn diode in forward bias

If we apply an external voltage, such that the P side is made positive with respect to the N
side, the applied voltage will reduce the built in voltage across the junction. The magnitude of
the built-in voltage is such that it balances the drift and diffusion currents, resulting in zero net
current. But if the voltage across the junction is reduced, a net current will flow through the diode.
This is the forward mode of operation. Because of this flow of current, electrons are injected into
the P side and holes into the N side. Consequently, the concentration of carriers is no longer
at the equilibrium value. We denote the equilibrium value of electron and hole concentrations
on P and N side by np0 , nn0 , pp0 , pn0 respectively. Since the majority carrier concentration in
equilibrium is equal to the doping density, we have:

nn0 ≈ Nd , pp0 ≈ Na and np0 = n2i /Na , pn0 = n2i /Nd

8
According to equation(10)
np = n2i e(uFp −uFn )
As we make the potential of P type more positive compared to N type, the np product in forward
bias is greater than n2i . From relations(12), we see that the change in quasi Fermi levels is small
wherever the carrier concentration is high. Thus, we can assume that the quasi Fermi levels of
the majority carriers at either side of the junction remain at their equilibrium values. Hence the
voltage across the junction is given by

V = φFp − φFn

and therefore the non-equilibrium np product is given by

 
qV

np = n2i e KB T

therefore,
   
n2i qV
KB T
qV
KB T
np = e = np0 e
pp
   
n2i qV
KB T
qV
KB T
pn = e = pn 0 e (21)
nn
(22)

The continuity equation for any particle flow can be written as

∂
∇.(particle current density) = − (particle concentration)
∂t
Applying it to electron and hole currents in 1 dimension on the n side,
!
∂ Jn
=U
∂x −q
!
∂ Jp
=U
∂x q

where U is the net recombination rate. Using relation(11), we have

!
∂ ∂φ ∂nn
nn µn − Dn = U
∂x ∂x ∂x
!
∂ ∂φ ∂pn
pn µ p + Dp = U
∂x ∂x ∂x
or
∂nn ∂φ ∂2φ ∂ 2 nn
µn + µn nn 2 − Dn 2 = U
∂x ∂x ∂x ∂x
∂pn ∂φ ∂2φ ∂ 2 pn
µp + µ p p n 2 + Dp 2 = U
∂x ∂x ∂x ∂x

9
Assuming the regions outside the small depletion regions to be charge neutral,

(nn − nn0 ) ≈ (pn − pn0 )

We define ambipolar diffusion and lifetime by the relations

nn + pn
Da ≡ (23)
nn /Dp + pn /Dp
pn − pn 0 nn − nn0
τa ≡ = (24)
U U
multiplying the electron continuity equation with µp pn and the hole continuity equation with
µn nn and combining, we get

pn − pn 0 ∂ 2 pn nn − pn ∂pn ∂φ
− + Da 2 + =0 (25)
τa ∂x nn /µp + pn /µn ∂x ∂x

If we make the low injection assumption (pn << nn ≈ nn0 ), this reduces to

pn − pn 0 ∂ 2 pn ∂pn ∂φ
− + Dp 2 + µp =0 (26)
τp ∂x ∂x ∂x
∂φ
In the neutral region, ∂x
is zero, so the above simplifies further to

∂ 2 pn pn − pn 0
− =0 (27)
∂x2 Dp τp

This can be solved with the boundary condition given by relation(21) and noting that pn =
pn0 at x = ∞ to give:  qV  x−x
n
pn − pn0 = pn0 e KB T − 1 e Lp (28)

where q
Lp ≡ Dp τp (29)
Evaluating the hole current at Xdn , we get
∂pn qDp pn0 qV
 
Jp = −qDp = e KB T − 1 (30)
∂x Lp

Similarly, we can evaluate the electron current on the p side as

∂np qDn np0 qV
 
Jn = qDn = e KB T − 1 (31)
∂x Ln
which gives the total current density as
 qV

J = Jp + Jn = Js e KB T
−1 (32)
qDp pn0 qDn np0
Where Js ≡ + (33)
Lp Ln

10
3 The MOS Capacitor
It is important to understand the MOS capacitor in order to understand the behaviour of the
the MOS transistor. Before we describe the MOS structure, it is useful to review the basic
electrostatics as applied to parallel plate capacitors. We shall then go on to analyse the MOS
structure.

3.1 The Parallel Plate Capacitor

The parallel plate capacitor consists of two parallel metallic plates of area A, separated by an
insulator of thickness ti and dielectric constant ǫ. If we place a charge Q on the upper plate, it
attracts charges of opposite sign in the bottom plate, while repelling charges of the same sign.
If the bottom plate is connected to ground, the repelled charge flows to ground. Now the two

+ + + + + + + + Q
ti
− − − − − − − − −Q

Figure 4: The parallel Plate capacitor

capacitor plates hold equal and opposite charge. This charge resides just next to the insulator
on either side of it. This is true, whatever the quantity or sign of charge placed on the upper
plate. The inducing and induced charge are always separated by the thickness of the insulator,
ti . Therefore this structure has a constant capacitance given by:
Aǫ
Ctotal =
ti
Since there are no charges inside the dielectric, the electric field in the insulator is constant and
the electrostatic potential changes linearly from one plate to the other.

3.2 The MOS capacitor

In a MOS capacitor, we replace the lower plate by a semiconductor. Unlike a metal, a semicon-
ductor can have charges distributed in its bulk. For the sake of an example, let us consider a
P type semiconductor (Si) doped to 1016 atoms /cm3 . As we know, holes outnumber electrons
in this semiconductor by an extremely large factor. If we place a negative charge on the upper
plate, holes will be attracted by this charge, and will accumulate near the silicon-insulator in-
terface. This situation is analogous to the parallel plate capacitor and thus, the capacitance will
be the same as that for a parallel plate capacitor. If, however, we place a positive charge on
the upper plate, negative charges will be attracted by it and positive charges will be repelled.
In a P type semiconductor, there are very few electrons. The negative charge is provided by
the ionised acceptors after the holes have been pushed away from them. But the acceptors are
fixed in their locations and cannot be driven to the edge of the insulator. Therefore, the distance
between the induced and inducing charges increases - so the capacitance is lower as compared to
the parallel plate capacitor. As more and more positive charge is placed on the upper plate, holes

11
 Metal
Insulator (Oxide)

Depletion region
Semiconductor

Metal

Figure 5: The MOS structure

Accumulation Inversion

Depletion
Capacitance

Figure 6: Low frequency capacitance for a MOS capacitor

from a thicker slice of the semiconductor are driven away, and the incremental induced charge
is farther from the inducing charge. Thus the capacitance continues to decrease. This does not,
however, continue indefinitely. We know from the law of mass action that as hole density reduces,
the electron density increases. At some point, the hole density is reduced and electron density
increased to such an extent that electrons now become the “majority” carriers near the interface.
This is called inversion. Beyond this point, more positive charge on the upper plate is answered
by more electrons in the semiconductor. But the electrons are mobile, and will be attracted to
the silicon insulator interface. Therefore, the capacitance quickly increases to the parallel plate
value.

3.3 Quantitative Analysis

Consider a one dimensional representation of the MOS structures as shown in the figure below.
The origin is assumed to be at the silicon-oxide interface and the positive x direction is into the
bulk of silicon. Using a one dimensional analysis, we want to relate the semiconductor charge to
the applied gate voltage. In a practical case, there is a potential difference between two dissimilar
materials in contact. Also, the silicon - oxide interface will have some fixed charge sitting there.
However, we consider the ideal case first - where there is no built in contact potential between
the semiconductor and the metal, and there is no interface charge.

12
 M O S M

o
X

Figure 7: co-ordinate system used for analysis

3.3.1 Ideal Case

Let the back surface of Si be at zero potential and the voltage applied to the gate terminal be
Vg . Let the electrostatic potential at any point x be denoted by φ(x) and let the potential at the
silicon-oxide interface be φs .

M O S M

Gaussean Box

We construct a Gaussian box passing through the interface and extending to +∞. According
to Gauss law, the integral of the outward pointing D vector around the box should be equal to
the charge contained inside. The only boundary where D is non zero is the one passing through
the interface. Therefore,
φ s − Vg
Area × ǫox = Total Charge in silicon
tox
If we define Qsi to be the semiconductor charge per unit area, and Cox to be the parallel plate
capacitance per unit area, we get
Qsi
Vg = φ s −
Cox
Thus, the surface potential and the applied gate voltage can be related to each other. If the
surface potential is known, we can evaluate the semiconductor charge by integrating the Poisson’s
equation in the semiconductor, once.
We can write the Poisson’s equation in the semiconductor as

∇·D=ρ

or
∂2φ
−ǫsi = q(Nd+ − Na− + p − n)
∂x2
13
Since the electrostatic potential is dependent only on x, we can change partial derivatives to total
derivatives.
d2 φ
!
d dφ d
− 2 = − = (E)
dx dx dx dx
where E is the electrostatic field. Changing the variable from x to φ.
d2 φ
!
dE dφ d d 1 d  2
− 2 = = (E) = −E (E) = − E
dx dx dx dφ dφ 2 dφ
If we define
q
u ≡ βφ where β ≡
KB T
We get
d2 φ 1 d  2 β d  2
− = − E = − E (34)
dx2 2 dφ 2 du
The right hand side of the Poisson’s equation represents the charge density. In the absence of an
applied voltage, this must be zero everywhere. Therefore,

q(Nd+ − Na− + p0 − n0 ) = 0

where p0 and n0 represent the hole and electron density in the absence of an applied field.
therefore,
Nd+ − Na− = −(p0 − n0 )
Substituting equation(34) and the above in the Poisson’s equation,
βǫsi d  2 
− E = q [p − p0 − (n − n0 )]
2 du
so " #
d  2 2qp0 p n0 n

E =− −1− −1
du βǫsi p0 p0 n0
From equation(8)
n = n0 eu and p = p0 e−u
So, " #
d  2 2qp0 −u n0
E =− e − 1 − (eu − 1)
du βǫsi p0
This can be integrated from x = ∞ (where E = 0 and u = 0) to x to give
" #
2qp0 u n0
Z
2
E = −e−u
+ 1 + (eu − 1) du
βǫsi 0 p0
Integrating and putting limits at 0 and u, we get
" #
2 2qp0 −u n0
E = e − 1 + u + (eu − 1 − u)
βǫsi p0
Therefore s " #1
2qp0 −u n0 2
E=± e − 1 + u + (eu − 1 − u)
βǫsi p0

14
And thus, the displacement vector D can be evaluated as:
s " #1
2qp0 ǫsi −u n0 2
D = ǫsi E = ± e − 1 + u + (eu − 1 − u) (35)
β p0

This equation permits us to calculate D, given the value of u. In particular, the value of D at
the surface (which is required for integration over the Gaussean box), can be evaluated from us .
In fact if u is very small, the exponentials in u can be expanded to second order. The first
two terms cancel with 1 and u, leaving
s " #1
2qp0 ǫsi 2 n0 2
D = ǫsi E = ± u /2 + (u2 /2)
β p0
s !
∂u qβp0 n0
≃∓ 1+ u
∂x ǫsi p0
ǫsi
q
This leads to exponential solutions for u with a characteristic length LD = qβp 0
. This implies
that small local perturbations in potential tend to decrease exponentially, with this characteristic
length. This length is known as the extrinsic Debye Length.

For the p doped semiconductor under consideration,

n0
p0
<< 1, so (1 + np00 ) ≃ 1. In this case, the characteristic length (known as the extrinsic Debye
q
ǫsi
Length) is LD = qβp 0
.
(In the intrinsic case, n0 = p0 , so 1 + np00 = 2).
Thus, in the intrinsic case, we get an additional factor of 2 in the denominator under the square
root.)

By putting u = us in eq. 35, we get the D vector at the surface. We construct a Gaussean
box passing through the interface and enclosing the semiconductor (as described in section 3.3.1)
The charge contained in the box is then the integral of the outward pointing D vector over the
surface of the box. D is non zero only at the interface. The outward pointing D is along the
negative x axis. Therefore by application of Gauss theorem,

Sem. Charge = Area × (−D)

Hence the charge in the semiconductor per unit area is:

√ " #1
2ǫsi −us n0 us 2
Qsi = ∓ e − 1 + us + (e − 1 − us ) (36)
βLD p0
where us ≡ βφs
q
β ≡
K T
sB
ǫsi
and LD ≡ = The Extrinsic Debye Length
qβp0

Notice that Qsi is the charge in the semiconductor per unit area. In this treatment, we shall use
symbols of the type Q and C with various subscripts to denote the corresponding charges and

15
capacitance values per unit area. Qsi consists of mobile as well as fixed charge. The mobile charge
is contributed by holes when us < 0 and by electrons when us > 0 (for a P type semiconductor).
As we shall see later, the mobile electron charge is substantial only when the positive surface
potential exceeds a threshold value.

The fixed charge is contributed by the depletion charge when the surface potential is positive.
The depletion charge per unit area can be calculated by the depletion formula.
q
Qdepl = −qNa Xd = 2qNa ǫsi φs (φs > 0)

A somewhat more accurate expression for depletion charge accounts for slightly lower charge
density at the edge of the depletion region by subtracting KB T/q from φs .
q
Qdepl = −qNa Xd = 2qNa ǫsi (φs − KB T /q) (φs > KB T /q) (37)

1e−05
Abs. Sem. Charge (C/cm2 )

Maj. Carrier
1e−06 Charge
Q
total
1e−07

Q
Depl.
1e−08

1e−09
−0.4 −0.2 0 0.2 0.4 0.6 0.8 1
Gate Voltage (V)

Figure 8: semiconductor charge as a function of surface potential

Calculated values for the total semiconductor charge per unit area (ie. inclusive of depletion
and mobile charge) and just the depletion charge per unit area have been plotted in figure 8
for a P type semiconductor doped to 1016 /cm3 . For small positive surface potential, the total
semiconductor charge contains only depletion charge. However, beyond a surface potential near
2ΦF , the total charge exceeds the depletion charge very rapidly. This additional charge is due
to mobile minority carriers (in this case, electrons).

3.3.2 Practical case

A practical MOS structure will differ from the ideal case assumed above in a few respects. There
is a built-in potential difference between the metal used and Si, due to the difference between their
work functions. This shifts the relationship between Vg and φs . Also, there is a fixed oxide charge
which resides essentially at the silicon-oxide interface. Thus, the total charge in the Gaussian

16
box includes this fixed charge and the semiconductor charge. These two non-idealities can be
accounted for by modifying the relationship between Vg and φs to be
Qsi + Qox
Vg = Φms + φs − (38)
Cox
Where Φms is the metal to semiconductor work function difference.

1.0

0.8
Surface Potential (V)

0.6

0.4
0.2

0.0

−0.2
−4.0 −2.0 0.0 2.0 4.0
GATE VOLTAGE (V)
Figure 9: Surface potential as a function of gate voltage

Figure 9 shows the surface potential as a function of applied voltage for a MOS capacitor with
oxide thickness of 22.5 nm, substrate doping of 1016 /cc, oxide charge of 4 × 1010 q and aluminium
as the gate metal. The surface potential changes quite slowly as a function of gate voltage in the
accumulation and inversion regions.
The absolute value of semiconductor charge has been plotted as a function of applied gate voltage

1e−06
Q
Abs. Sem. Charge (C/cm )

total
2

Q
1e−07 inv
Q
depletion
1e−08

1e−09
−2 −1 0 1 2 3 4 5
Gate Voltage (V)

Figure 10: Semiconductor charge as a function of gate voltage

in figure 10. (The charge is actually negative for positive gate voltages). As one can see, for
small positive gate voltages, the entire semiconductor charge is depletion charge. As the voltage
exceeds a threshold voltage, the total charge becomes much larger than the depletion charge. The
excess charge is provided by mobile electron charges. This is the inversion region of operation,
where electrons become the majority carriers near the surface in a p type semiconductor. Notice
that the depletion charge is practically constant in this region. This region begins when the
surface potential exceeds 2ΦF .

17
4 The MOS Transistor
Inversion converts a p type semiconductor to n type at the surface. We can use this fact to
construct a transistor. We place semiconductor regions strongly doped to N type on either side
of a MOS capacitor made using P type silicon. Now if we try to pass a current between these

Metal Gate

n+ n+
P type Si
Figure 11: A MOS Transistor

two N regions when inversion has not occurred, we encounter series connected NP and PN diodes
on the way. Whatever the polarity of the voltage applied to pass current, one of these will be
reverse biased and practically no current will flow.
However, after inversion, the intervening P region would have been converted to N type. Now
there are no junctions as the whole surface region is n type. Current can now be easily passed
between the two n regions. This structure is an n channel MOS transistor. pMOS transistors
can be similarly made using P regions on either side of a MOS capacitor made on n type silicon.
When current flows in an n channel transistor, electrons are supplied by the more negative of
the two n+ contacts. This is called the source electrode. The more positive n+ contact collects
the electrons and is called the drain. The current in the transistor is controlled by the metal
electrode on top of the oxide. This is called the gate electrode.

4.1 I-V characteristics of a MOS transistor

A quantitative derivation of the current-voltage characteristics of the MOS device is complicated
by the fact that it is inherently a two dimensional device. The vertical field due to the gate voltage
sets up a mobile charge density in the channel region as seen in figure 10. The horizontal field
due to source-drain voltage causes these charges to move, and this constitutes the drain current.
Therefore, a two dimensional analysis is required to calculate the transistor current, which can be
quite complex. However, reasonably simple models can be derived by making several simplifying
assumptions.

4.2 A simple MOS model

We make the following simplifying assumptions:

• The vertical field is much larger than the horizontal field. Then, the resultant field is
nearly vertical, and the results derived for the 1 dimensional analysis for the MOS capacitor
can be used to calculate the point-wise charge density in the channel. This is known as
the gradual channel approximation. Accurate numerical simulations have shown that this
approximation is valid in most cases.

• The source is shorted to the bulk.

18
 • The gate and drain voltages are such that a continuous inversion region exists all the way
from the source to the drain.

• The depletion charge is constant along the channel.

• The total current is dominated by drift current.

• The mobility of carriers is constant along the channel.

Figure 12 shows the co-ordinate system used for evaluating the drain current. The x axis points

W
Y
S D

X dy
Figure 12: Coordinate system used for analysing the MOS transistor

into the semiconductor, the y axis is from source to the drain and the z axis is along the width of
the transistor. The origin is at the source end of the channel. We represent the channel voltage
as V(y), which is 0 at the source end and Vd at the drain end. We assume the current to be made
up of just the drift current. Since we are carrying out a quasi 2 dimensional analysis, all variables
are assumed to be constant along the z axis. Let n(x,y) be the concentration of mobile carriers
(electrons for an n channel device) at the position x,y (for any z). The drift current density at a
point is

J = no. of carriers × charge per carrier × velocity

!
∂V (y)
= n(x, y) × (−q) × µ × −
∂y
∂V (y)
= µn(x, y)q
∂y

Integrating the current density over a semi-infinite plane at the channel position y (as shown in
the figure 12) will then give the drain current.
W ∂V (y)
Z ∞ Z
Id = µn(x, y)q dzdx
x=0 z=0 ∂y

19
Since there is no dependence on z, the z integral just gives a multiplication by W. Therefore,
∂V (y)
Z ∞
Id = µW q n(x, y) dx
x=0 ∂y
the value of n(x,y) is non zero in a very narrow channel near the surface. We can assume that
∂V (y)
∂y
is constant over this depth. Then,

∂V (y)
Z ∞
Id = µW q n(x, y)dx
∂y x=0
R
but q x=0
∞
n(x, y)dx = −Qn (y) where Qn (y) is the electron charge per unit area in the semicon-
ductor at point y in the channel. (Qn (y) is negative, of course). therefore

∂V (y)
Id = −µW Qn (y)
∂y
(39)

Integrating the drain current along the channel gives

Z L Z L ∂V (y)
Id dy = −µW Qn (y) dy
0 0 ∂y
Z Vd
Id × L = −µW Qn (y)dV (y)
0
W Z Vd
So, Id = −µ Qn (y)dV (y)
L 0
We now use the assumption that the surface potential due to the vertical field saturates around
2ΦF if we are in the inversion region. Therefore, the total surface potential at point y is V(y) +
2 ΦF . Now, by Gauss law and continuity of normal component of D at the interface,
 
Cox Vg − ΦMS − φs = − (Qsi + Qox )

therefore,  
−Qsi = Cox Vg − ΦMS − V (y) − 2ΦF + Qox /Cox
However,
Qsi = Qn + Qdepl
So

−Qn (y) = −Qsi (y) + Qdepl

 
= Cox Vg − ΦMS − V (y) − 2ΦF + (Qox + Qdepl )/Cox

We have assumed the depletion charge to be constant along the channel. Let us define
(Qox + Qdepl )
VT ≡ ΦMS + 2ΦF −
Cox
then
−Qn (y) = Cox (Vg − VT − V (y))

20
and therefore,
W Vd
Z
Id = µCox (Vg − VT − V (y))dV (y)
L 0
W 1
= µCox [(Vg − VT )Vd − Vd2 ] (40)
L 2
This derivation gives a very simple expression for the drain current. However, it requires a lot of
simplifying assumptions, which limit the accuracy of this model.
If we do not assume a constant depletion charge along the channel, we can apply the depletion
formula to get its dependence on V(y).
q
Qdepl = − 2ǫsi qNa (V (y) + 2ΦF )

then,
  q
−Qn = Cox Vg − ΦMS − V (y) − 2ΦF + Qox − 2ǫsi qNa (V (y) + 2ΦF )

which leads to
W Qox 1
 
Id = µCox Vg − ΦMS − 2ΦF + Vd − Vd2
L Cox 2
√ #
2 2ǫsi qNa 
3/2 3/2

− (Vd + 2ΦF ) − (2ΦF )
3 Cox
This is a more complex expression, but gives better accuracy.

4.3 Modeling the saturation region

The treatment in the previous section is valid only if there is an inversion layer all the way from
the source to the drain. For high drain voltage, the local vertical field near the drain is not
adequate to take the semiconductor into inversion. Several models have been used to describe
the transistor behaviour in this regime. The simplest of these defines a saturation voltage at
which the channel just pinches off at the drain end. The current calculated for this voltage by
the above models is then supposed to remain constant at this value for all higher drain voltages.
The pinch-off voltage is the drain voltage at which the channel just vanishes near the drain end.
Therefore, at this point the gate voltage Vg is just less than a threshold voltage above the drain
voltage Vd . Thus, at this point,
Vdsat = Vg − VT
The current calculated at Vdsat will be denoted as Idss . Thus,
W 1
Idss = µCox [(Vg − VT )2 − (Vg − VT )2 ]
L 2
for the simple transistor model. Thus
1 W
Idss = µCox (Vg − VT )2 (41)
2 L
The drain current is supposed to remain constant at this Vd independent value for all drain
voltages > Vg − VT .

21
4.3.1 Early Voltage approach
Assuming a constant current in the saturation region leads to an infinite output resistance. This
can lead to exaggerated estimates of gain from an amplifier. Therefore, we need a more realistic
model for the transistor current in the saturation region. One of these is a generalisation of the
model proposed by James Early for bipolar transistors. This model is not strictly applicable to
MOS transistors. However, due to its numerical simplicity, it is often used in compact models
for circuit simulation.

A geometrical interpretation of the Early model states that the drain current increases lin-
early in the saturation region with drain voltage, and if saturation characteristics for different
gate voltages are produced backwards, they will all cut the drain voltage axis at the same (neg-
ative) drain voltage point. The absolute value of this voltage is called the Early Voltage VE .

The current equations in saturation mode now become:

Idss ≡ Id (Vg , Vdss )
Vd + VE
Id = Idss For Vd > Vdss (42)
Vdss + VE
Any model can be used for calculating the drain current for Vd < Vdss . The value of Vdss will
be determined by considerations of continuity of the drain current and its derivative at the
changeover point from linear to saturation regime. For example, if we use the simple model
described in eq. 40,
∂Id W
= µCox (Vg − VT − Vd ) For Vd ≤ Vdss
∂Vd L
∂Id Idss
And = For Vd ≥ Vdss
∂Vd Vdss + VE
W 1 2
 
Where Idss ≡ µCox (Vg − VT ) Vdss − Vdss
L 2
∂Id
On matching the value of ∂Vd
on both sides of Vdss , we get
s 
2 (Vg − VT )
Vdss = VE  1 + − 1
VE
In practice, VE is much larger than Vg − VT . If we expand the above expression, we find that
to first order the value of Vdss remains the same as the one used in the simple model - that is,
Vg − VT . Expansion to second order gives
Vg − VT
 
Vdss ≃ (Vg − VT ) 1 − (43)
2VE

4.3.2 Simulation Model

Since the value of Vdss does not change substantially from the ideal saturation case, a simpler
approach can be tried. The drain current is calculated using the ideal saturation model and its
value is multiplied by a correction factor = (1 + λVd ) in saturation as well as in linear regime.
This automatically assures continuity of Id and its derivative. λ is a fit parameter, whose value
is ≈ 1/VE . This approach is used in SPICE, a popular circuit simulation program.

22
5 MOS Device Scaling
Since the transistor current depends on W/L, it is interesting to see what happens if we reduce
both W and L, keeping their ratio constant. We have to adjust other parameters as well, in
order to ensure that the transistor works without problems.

Due to technological constraints, we cannot reduce lateral geometries without reducing layer
thicknesses. To define finer lateral dimensions through etching etc., we need the layers to be
thinner. Thus all dimensions, vertical or lateral, need to be scaled by the same factor. To ensure
that higher fields in the device do not cause breakdown, we have to scale down all the voltages
by the same factor as L. (This is known as constant field scaling).

We also need to scale depletion widths in the same ratio as W and L. This is essential in order
to scale down the separation between transistors and to control channel length modulation due
to drain voltage. This requires doping densities to be scaled up by the same factor as the one
used to scale down W and L.

So we define a scaling factor S, and reduce W, L, junction depths and oxide thicknesses etc.
by this factor. Doping densities need to be increased by factor S. All working voltages and the
Threshold voltage VT need to be scaled down by S. Once this scaling is done, we are interested
in evaluating the impact on the circuit performance.

5.1 Consequences of Scaling

We assume classical or Constant Field scaling in the following.

Device Area: Since W reduces by ↓ S and L reduces by ↓ S, the area reduces by ↓ S 2 .

Packing Density: For a given chip area, the number of devices which can be packed in this
chip will go up by ↑ S 2 .
Cox : The gate capacitance per unit area is given by ǫ/tox . Since tox scales down by ↓ S, Cox
increases by ↑ S. Cox determines the transconductance, so this increase is good.
Load capacitance: All dimensions, including depletion widths have been scaled down by ↓ S.
Total capacitance = ǫA/t. Now A reduces by ↓ S 2 , while the dielectric thickness (be
it oxide or depletion width) reduces by ↓ S. The net effect is that total capacitance
= ǫArea ↓ S 2 /t ↓ S reduces by ↓ S.
Voltages: All voltages such as VDS , VGS , VT etc. are scaled down by ↓ S to keep the field
constant.
Drain current: IDS is given by µCox (W/L)f (VDS , VGS , VT ). Since all voltages are scaled down
by ↓ S and f is a square function of voltages both in linear mode and saturation, f will
scale down as ↓ S 2 . Thus,

IDS = µCox (↑ S)(W ↓ S/L ↓ S)f (VDS , VGS , VT )(↓ S 2 )

So combining all dependences, IDS ↓ S.

23
Slew Rate: Slew rate is the rate of change of voltage at any node. Since I = C dV
dt
, the slew
rate goes as I(↓ S)/C(↓ S). Thus slew rate remains unchanged with scaling.

Delay: Delay is given by the total voltage change divided by dV

dt
. Since all voltages are scaled
dV
down by ↓ S, while dt remains unchanged, the delay reduces as ↓ S.

Static Power: It is given by V × I . So it scales as (↓ S)(↓ S), that is ↓ S 2 .

Dynamic Power: Dynamic power is given by Ctotal V 2 f . This scales as (↓ S)(↓ S 2 )(↑ S). Thus
dynamic power reduces as ↓ S 2 even when the frequency of operation is increased by ↑ S
to take advantage of shorter delays, which scale down by (↓ S).

With all dimensions and voltages divided by the factor S(> 1), We can summarise the impact
of using constant field Scaling as follows:
Device area ∝ W × L : (↓ S)(↓ S) ↓ S2
Cox ǫox /tox : const/(↓ S) ↑S
Ctotal ǫA/t : (↓ S 2 )/(↓ S) ↓S
VDS , VGS , VT Voltages : (↓ S) ↓S
Id µCox (W/L)(∝ V 2 ) :
(↑ S)(const)(↓ S 2 ) ↓S
dV
Slew Rate dt I/Ctotal : (↓ S)/(↓ S) const.
Delay V / dV
dt
: (↓ S)/(const) ↓S
Static Power V × I : (↓ S)(↓ S) ↓ S2
dynamic power Ctotal V 2 f : (↓ S)(↓ S 2 )(↑ S) ↓ S2
Power delay product delay × power(↓ S)(↓ S 2 ) ↓ S3
Power density power/area : (↓ S 2 )/(↓ S 2 ) const.

Thus, scaling leads to:

• Improved packing density: ↑ S 2

• Improved speed: delay ↓ S

• Improved power consumption: ↓ S 2

So, circuit performance improves dramatically with transistor scaling. This provides the motiva-
tion for making transistors as small as possible.

What are the limits on scaling?

These come from processing technology limitations, device limitations and circuit considera-
tions such as reduced signal to noise ratio due to reduced supply voltages.

5.2 Moore’s “Law”

In 1965, Gordon Moore, the co-founder of Fairchild Semiconductor as well as Intel, described a
doubling every year in the number of components per integrated circuit. It is an observation
of a trend and an empirical relationship – not a physical or natural law! However, given the

24
prominence of Gordon Moore, it is widely referred to as Moore’s Law.

In 1975, Moore modified his observation for the rate of device scaling and predicted a doubling
of device density every two years. It is remarkable that this trend has continued over several
decades. It is only in the last decade that the rate of doubling has slowed down remarkably, as
we hit several physical limits.

Device scaling started initially as an empirical observation. The theoretical basis of constant
field device scaling was laid down in a landmark paper in 1974 from a group of scientists from IBM.

R.H. Dennard, F. H. Gaensslen, Hw A-Nien Yu, V. L. Rideout, E. Bassous, and A. R, LeBlanc,

“Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions”, IEEE Journal of
Solid-State Circuits, Vol. SC-9, No. 5, pp. 256-268, 1974.

This is one of the most quoted papers in this field. I strongly recommend that you read it –
for its contents, but also to learn from its style of technical writing.

5.3 The technology road map

The incredible rate of increase in circuit performance has been possible through careful planning.
The semiconductor industry used Moore’s prediction for setting specific targets for development
in process technology, processing equipment and for research and development in critical areas
of device Physics. The result of this planning was the creation of an International Technology
Roadmap for Semiconductor Scaling – or ITRS. ITRS has been revised every year till recently.
A new ITRS has not been issued after 2016.

It is hard to track and scale the optimum size of numerous structures on an Integrated circuit.
As discussed earlier, it is common to describe feature sizes in units of a parameter called λ. Now
sizes of various structures can be described in units of λ. As we scale technologies, we just scale
the value of λ. Feature sizes remain the same in units of λ, which is convenient.

The smallest feature on a chip is the contact window. The value of λ is so defined that the
smallest feature size is 2λ. The smallest registration rule – for example the extent to which a
contact window must be inside a diffused region – is λ.

As a result of careful planning and the considerable financial rewards of improved MOS tech-
nology, feature sizes have been continually scaled. The table below gives the commonly used
channel lengths by the year in various decades.

1971 10 µm 1974 6 µm 1977 3 µm

1981 1.5 µm 1984 1 µm 1987 800 nm
1990 600 nm 1993 350 nm 1996 250 nm 1999 180 nm
2001 130 nm 2003 90 nm 2005 65 nm 2007 45 nm 2009 32 nm
2012 22 nm 2014 14 nm 2017 11 nm

25
The scaling rate has slowed down after 2010. This is because feature sizes had already reached
about 20 nm – about 3% of the wavelength of sodium light!

5.4 Demand from Processing Technology

Circuit performance improves dramatically with transistor scaling. This provides the motivation
for making transistors as small as possible.
What demands does it place on processing technology?

• Scaling requires much higher resolution in defining geometries. Size of the finest patterns
in the state of the art technologies is about 10nm. This is about a fiftieth of the wavelength
of sodium light!

• Advanced photo-lithographic techniques need to be used to define such fine geometries. We

need deep UV lithography and even XRay lithography to define such fine structures.

• Etching techniques have to be improved to define such fine structures. Dry etching using
plasma or reactive ion etching is used rather than wet chemical etching to define such fine
structures

5.5 Limits of scaling

Scaling is being limited now due to several reasons.

• We are reaching limits of resolution possible with photo-selective processes and etching etc.

• Traditional Device Physics is not valid any more for such small structures.

Remember, the lattice constant of Silicon is ≈ 0.5 nm. So there are as few as 20 atoms between
source and drain of a 10 nm channel MOSFET. Clearly, conduction models based on statistics
will not hold here.

Indefinite voltage scaling is not possible. If the voltage is scaled down drastically,

• signal to noise ratio will become poor,

• leakage currents will become dominant as KT /q has not been scaled and current equations
of junctions involve qV /KT .

• System considerations such as interconnect delay will limit performance gain.

• At low voltages, supplying power requires higher currents. Feeding such high currents
through IC pins becomes impractical.

26
 Metal Gate

n+ n+
P type Si
Figure 13: Sideways diffusion from source drain regions

5.6 Short Channel Effects

Several effects become prominent once transistor dimensions are made very small. The classical
model for MOS transistors assumed a uniform doping in the channel region. However, because
of heavy doping in the source/drain region, there is a sideways diffusion of impurities into the
channel. If the channel length is quite short, the region of non-uniform doping becomes a large
fraction of the channel length. This results in considerable deviations from the transistor model.

Threshold voltage of a long channel transistor is independent of channel length. As we scale

down channel length, the threshold voltage becomes dependent on channel length. (Short chan-
nel effect on VT ).

Also, as the drain comes closer to the source, the field due to the drain channel junction
reaches the source channel junction. This reduces the barrier to carrier injection from the source
into the channel. This is known as Drain Induced Barrier Lowering or DIBL.

5.7 Narrow Channel Effects

As we scale down devices, channel widths as well as channel lengths are reduced. The threshold
voltage becomes dependent on channel width as well as channel length for scaled down devices.
This is because the depletion charge on the sides of the channel is no more negligible compared
to the charge directly under the gate. For uniformly doped devices, VT increases as the channel
is made narrower. However, the dependence is more complex when doping is non-uniform.

6 Breakdown Phenomena
6.1 Avalanche Breakdown
The drain channel junction is reverse biased. In saturation region, there is high field region next
to the gate. If the field exceeds some critical value, carrier multiplication will occur, leading to
avalanche breakdown. Multiplication produces excess electron-hole pairs. Electrons are attracted
towards the positively biased drain. Holes drift towards the source and constitute a “base current”
for the parasitic lateral npn transistor.
Carrier multiplication near drain can result in a sharp increase in drain current. This is the
avalanche breakdown of the transistor. It is also possible that the parasitic bipolar turns on, due

27
 GATE

SOURCE p DRAIN
n+ e- n+
-
h+ e+
h

S D Parasitic NPN
Bipolar Transistor
Channel

Figure 14: Avalanche breakdown at high fields

to the base current provided by the drifting holes from the drain junction, adding its current
to the drain current. The additional current due to the bipolar action, combined with carrier
multiplication near the drain can result in early breakdown of the transistor.

6.2 Punch Through

If the channel is very short, at high drain voltages, the depletion region due to the drain-substrate
junction can reach the source. Due to the drain field, the source/substrate junction will get for-
ward biased and will inject current into the channel, even if the gate voltage is below VT . This is
an extreme case of drain induced barrier lowering and results in heavy current even though the
transistor is supposed to be ‘OFF’. This is known as “Punch Through”.

7 Parasitic Devices
7.1 Field transistors
As we make the devices needed for the desired circuit, several other devices get formed. The
most common of these is the field transistor. A MOS like structure exists between unrelated
diffusion areas due to metal lines crossing over unrelated diffusion areas.

7.2 Latch up due to parasitic pnpn structures

Fig.16 shows the lay out of an inverter. (As we shall learn later, this is a bad layout!). While the
lay out does form an inverter as desired, it also forms a parasitic latch-up structure which can
turn on, shorting VDD to ground and destroying the IC due to the resulting heavy current.
A vertical pnp transistor is formed by

1. the p+ source of a pMOS transistor connected to VDD (which becomes the emitter),

2. the n well (which becomes the base), and

3. the p substrate (which becomes the collector of this transistor).

28
 Field

Diffusion Line

Diffusion Line
Oxide

TOP VIEW

Metal Line

Cross Section Metal Line

Field
Oxide
Diffusion Diffusion

Parasitic Field Transistor

Figure 15: Parasitic Field transistor in MOS technology

nMOS pMOS n Well

Output
(Metal)
VDD Input

Poly Poly
Input Output
VDD (Metal)
(Metal) cross section
through this line
Gnd
VDD Substrate
Contact nMOS source pMOS source Well Contact
R well
Vertical PNP

p+ n+ p n p+ n+
Vertical PNP

p substrate n Well
Horizontal
NPN Horizontal
p substrate
NPN

Figure 16: Formation of a parasitic latch up structure in an inverter

The n well is connected to VDD through a resistive path, which represents the resistance of the
n well to the well contact.
This can also be seen in Fig.17. A horizontal npn transistor is formed by

1. the n+ source of an nMOS transistor connected to ground (which becomes the emitter),

2. the p substrate, (which becomes the base), and

3. the n well, (which becomes the collector).

Since the collector of the npn and the base of the pnp are both formed by the n well, these two
are connected. Similarly, the collector of the pnp and the base of the npn are formed by the p
substrate, so these are connected too.

29
 Substrate contact n source p source Well contact
Gnd Gnd VDD VDD

p+ n+ n+ p+ p+ n+
n well
p substrate

Rwell
Vertical pnp

horizontal npn Rsub

Figure 17: Circuit for the parasitic latch up circuit

30
 From the equivalent circuit given in Fig.18, we can see that it forms a positive feedback
circuit.

• An increase in the base current of the pnp will be amplified by its βp and a large part of it
will flow through the base emitter junction of the npn transistor.

• This part will be amplified by the βn of the npn and a substantial part of it will go through
the base emitter junction of the pnp transistor.

VDD

Vertical pnp
Rwell

Horizontal
npn
Rsub

Figure 18: Positive feed back in the latch-up structure

If the product of the two amplification factors βp and βn and the current division ratios between
the resistors and the base emitter junctions exceeds 1, the currents will keep increasing due to
this feedback, till there is a dead short between VDD and ground. This is called latch up.

7.3 Preventing Latch up

To prevent latch up, we must reduce the β of the parasitic bipolar transistors, and make sure
that most of the collector current of either transistor is directed to the resistor and not to the
base-emitter junction of the other transistor.

This can be done through process steps as well as through layout design rules.

The doping gradient of the n well should be made retrograde. (Doping should increase as we
go deeper). This kills the current gain βp of the pnp transistor.
The n well should have a guard ring connected to VDD , which will collect any current which could
form the base current of the pnp.

In layout, substrate and well contacts should be placed frequently, to reduce the value of
Rwell and Rsubstrate . n channel transistors should be placed far from the edge of the n well. This
increases the base width of the npn transistor and kills its current gain. p channel transistors
should also be placed far from the well edge and the n well should be deep to kill the gain of the
pnp transistor.

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