Scribd
Upload
105 views2 pages

K.Ramakrishnan College of Engineering: Samayapurm, Trichy-621 112

This document outlines the topics and sections to read for a VLSI Design course across 5 units. Unit 1 focuses on MOS transistor operation, I-V characteristics, scaling, and delay models. Unit 2 covers dynamic and static CMOS logic, power considerations, and different logic families. Unit 3 discusses latches, registers, pipelining and timing. Unit 4 examines multipliers, adders, memory cores, and peripherals. Finally, Unit 5 presents design for testing techniques, FPGA architectures and DFM/boundary scan. Key concepts are MOSFET operation, static and dynamic power, latches, multipliers, memory architectures, and FPGA building blocks.

Uploaded by

Manimegalai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
105 views2 pages

K.Ramakrishnan College of Engineering: Samayapurm, Trichy-621 112

This document outlines the topics and sections to read for a VLSI Design course across 5 units. Unit 1 focuses on MOS transistor operation, I-V characteristics, scaling, and delay models. Unit 2 covers dynamic and static CMOS logic, power considerations, and different logic families. Unit 3 discusses latches, registers, pipelining and timing. Unit 4 examines multipliers, adders, memory cores, and peripherals. Finally, Unit 5 presents design for testing techniques, FPGA architectures and DFM/boundary scan. Key concepts are MOSFET operation, static and dynamic power, latches, multipliers, memory architectures, and FPGA building blocks.

Uploaded by

Manimegalai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

K.

RAMAKRISHNAN COLLEGE OF ENGINEERING


SAMAYAPURM,TRICHY-621 112
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
EC8095- VLSI DESIGN

S.NO TOPIC
UNIT1
Must Read Reference Pages
1 MOS transistor operation. Sec 1.2.4
2 Long Channel I-V Characteristics. Sec 1.7
3 Non-Ideal IV Effects. Sec 1.9
4 Layout design rules, Gate layout and Stick diagrams. Sec 1.4, 1.5 and 1.6
Sec 1.13 to 1.13.3 (Few parameters), 1.13.4, 1.13.6.3
5 Scaling.
and 1.13.6.5
Other important Topics
6 Delay models (Elmore model, RC, Linear model, Parasitic delay, Logical effort) Sec 1.11.1 to 1.12.1

7 C-V Characteristics. Sec 1.8


8 DC Transfer characteristics Sec 1.10.1 to 1.10.3

UNIT 2
Must Read
1 Dynamic logic, Domino logic and dual rail domino logic Sec 2.4, 2.4.1, 2.4.2
Sec 2.7, 2.7.1.1, 2.7.1.2, 2.7.1.3, 2.7.1.3
2 Dynamic and Static power
Sec 2.7.2 until 2.7.2.4
3 Low power architecture Sec 2.7.3

Sec 2.2, 2,2,1 to 2.2.5,


4 Static CMOS
Optimization techniques defn - 2.2.8
Other important Topics

5 Circuit Pitfalls Sec 2.6

Each logic family - Operation and


6 Ratioed circuits, CVSL, PT, TG, DPL, CPL, DCVSPG
circuit diagram with example logic gates

UNIT 3

Must Read
1 Static and dynamic latches/registers. Sec 3.2, 3,2.1, 3,2.2, 3.2.3, 3.3 full
2 Pipelining. Sec 3.6 full
3 Timing classification and synchronous design Sec 3.10.1, 3.10.2, 3.10.2.4, 3.10.2.5
Other Important Topics
4 Pulse register, Schmitt trigger, Monostable and Astable sequential circuits Sec 3.4, 3.7, 3.8, 3.9
5 Sense amplifier based register Sec 3.5 full
UNIT 4

Must Read
1 Power-speed tradeoffs Sec
Sec 4.7, 4.7.1Sec
4.4 and and 4.7.2
4.4.1 - Booth

2 Multipliers Sec 4.4.2, 4.4.2.1, 4.4.2.3 -- Wallace and Array


Sec 4.3.3.4 - Look ahead

Sec 4.3.3.1, 4.3.3.2 - Carry bypass, Linear carry select


Adders
Sec 4.3.1, 4.3.2.1, 4.3.2.2, 4.3.2.4 - Binary, Static, Mirror
and Manchester
3

Sec 4.10.3 - SRAM and DRAM

4 Memory core Sec 4.10.1 and Sec 4.10.2 - ROM, Non-volatile

Other important Topics


Sec 4.5 and Sec 4.6
5 Shifters, ALUs

6 Memory peripheral circuitry Sec 4.11


7 Memory architectures Sec 4.9.1 to 4.9.4
UNIT 5

Must Read
1 Design for testing - DFT, Adhoc, Scan design, BIST, IDDQ testing Sec 5.7 to 5.7.4
Sec 5.4 - Actel or Xilinx or Altera MAX (Any one
2 FPGA Building block architectures
FPGA architecture)
3 DFM and Boundary scan Sec 5.7.5 and 5.8
Other Important Topics
Sec 5.5 (Any two of Actel or Xilinx or Altera
4 FPGA Interconnect Routing Procedures
Interconnect Architectures)

You might also like