RISC AND CISC PROCESSORS

CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) are two forms of CPU
design

What is RISC?
It is a computer that only uses simple commands that can be divided into several instructions that achieve low-
level operation within a single CLK cycle, as its name proposes “Reduced Instruction Set”.

Its main function is to reduce the time of instruction execution by limiting as well as optimizing the number of
commands. Hence, it is mainly used to execute several difficult commands by merging them into simpler ones.
So each command cycle uses a single clock cycle where every clock cycle includes three parameters namely
fetch, decode & execute.

RISC Architecture
This is a small or reduced set of instructions. Here, every instruction is
expected to attain very small jobs. In this machine, the instruction
sets are modest and simple, which help in comprising more complex
commands. Each instruction is of a similar length; these are wound
together to get compound tasks done in a single operation. Most
commands are completed in one machine cycle. This pipelining is a
crucial technique used to speed up RISC machines.

Characteristics
The characteristics of RISC include the following.

1. One cycle execution time: For executing each instruction in a computer, the RISC processors require
one CPI (Clock per cycle). And each CPI includes the fetch, decode and execute method applied in
computer instruction.

2. Pipelining technique: The pipelining technique is used in the RISC processors to execute multiple parts
or stages of instructions to perform more efficiently.

3. A large number of registers: RISC processors are optimized with multiple registers that can be used to
store instruction and quickly respond to the computer and minimize interaction with computer
memory.

4. It supports a simple addressing mode and fixed length of instruction for executing the pipeline.

5. It uses LOAD and STORE instruction to access the memory location.

6. Simple and limited instruction reduces the execution time of a process in a RISC.

Advantages
The advantages of the RISC processor include the following.

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  The performance of this processor is good because of the easy & limited no. of the instruction set.
 This processor uses several transistors in the design so that making is cheaper.
 RISC processor allows the instruction to utilize open space on a microprocessor due to its simplicity.
 It is very simple as compared with another processor due to this; it can finish its task within a single
clock cycle.

Disadvantages
The disadvantages of a CISC processor include the following.

 The performance of this processor may change based on the executed code because the next
commands may depend on the earlier instruction for their implementation within a cycle.
 The complex instruction is frequently used by the compilers and programmers
 These processors need very quick memory to keep different instructions that use a huge collection of
cache memory to react to the command within less time.

What is CISC?
This processor includes a huge collection of simple to complex instructions. These instructions are specified in
the level of assembly language level and the execution of these instructions takes more time.

A complex instruction set computer is a computer where single instructions can perform numerous low-level
operations like a load from memory, an arithmetic operation, and a memory store or are accomplished by
multi-step processes or addressing modes in single instructions, as its name proposes “Complex Instruction
Set”. So, this processor moves to decrease the number of instructions on every program & ignore the number
of cycles for each instruction.

CISC Architecture
The CISC architecture helps reduce program code by embedding
multiple operations on each program instruction, which makes the
CISC processor more complex. The CISC architecture-based
computer is designed to decrease memory costs because large
programs or instruction required large memory space to store the
data, thus increasing the memory requirement, and a large
collection of memory increases the memory cost, which makes
them more expensive.

Characteristics
The main characteristics of the RISC processor include the following.

1. The length of the code is shorts, so it requires very little RAM.

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 2. CISC or complex instructions may take longer than a single clock cycle to execute the code.

3. Less instruction is needed to write an application.

4. It provides easier programming in assembly language.

5. Support for complex data structure and easy compilation of high-level languages.

6. It is composed of fewer registers and more addressing nodes, typically 5 to 20.

7. Instructions can be larger than a single word.

8. It emphasizes the building of instruction on hardware because it is faster to create than the software.

Advantages
The advantages of CISC include the following.

 This processor will create a procedure to handle the usage of power that regulates the speed of clock
& voltage.
 In the CISC processor, the compiler needs a small effort to change the program or statement from
high-level to assembly otherwise machine language.
 A single instruction can be executed by using different low-level tasks
 It doesn’t use much memory due to a short length of code.
 CISC utilizes less instruction set to execute the same instruction as the RISC.
 The instruction can be stored within RAM on every CISC.

Disadvantages
The disadvantages of CISC include the following.

 The existing instructions used by the CISC are 20% within a program event.
 As compared with the RISC processor, CISC processors are very slow while executing every instruction
cycle on every program.
 This processor use number of transistors as compared with RISC.
 The pipeline execution within the CISC will make it difficult to use.
 The machine performance reduces because of the low speed of the clock.

Difference between RISC and CISC

The main difference between the two can be shown in detail in the table below.

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 Difference between RISC and CISC Architecture

RISC: CISC:

1.RISC stands for Reduced Instruction Set Computer. 1. CISC stands for Complex Instruction Set Computer.
2. RISC processors have simple instructions taking 2. CSIC processor has complex instructions that take up
about one clock cycle. The average clock cycle per multiple clocks for execution. The average clock cycle
instruction (CPI) is 1.5 per instruction (CPI) is in the range of 2 and 15

3. Performance is optimized with more focus on 3. Performance is optimized with more focus on
software. hardware.
4. It has no memory unit and uses separate hardware 4. It has a memory unit to implement complex
to implement instructions.. instructions
5. It has a hard-wired unit of programming. 5. It has a microprogramming unit.

6. The instruction set is reduced i.e. it has only a few 6. The instruction set has a variety of different
instructions in the instruction set. Many of these instructions that can be used for complex operations.
instructions are very primitive.

7. The instruction set has a variety of different 7. CISC has many different addressing modes and can
instructions that can be used for complex operations. thus be used to represent higher-level programming
language statements more efficiently.
8. Complex addressing modes are synthesized using 8. CISC already supports complex addressing modes
the software.

9. Multiple register sets are present 9. Only has a single register set

10. RISC processors are highly pipelined 10. They are normally not pipelined or less pipelined

11. The complexity of RISC lies with the compiler that 11. The complexity lies in the microprogram
executes the program

12. Execution time is very less 12. Execution time is very high

13. Code expansion can be a problem 13. Code expansion is not a problem

14. The decoding of instructions is simple. 14. Decoding of instructions is complex

15. It requires external memory for calculations 15. It does not require external memory for calculations

16. The most common RISC microprocessors are 16. Examples of CISC processors are the System/360,
Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power VAX, PDP-11, Motorola 68000 family, AMD, and Intel
Architecture, and SPARC. . x86 CPUs

17. RISC architecture is used in high-end applications 17. CISC architecture is used in low-end applications
such as video processing, telecommunications, and such as security systems, home automation, etc
image processing.

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The advantages of RISC over CISC

In the current developments of computer processors, the RISC (reduced instruction set computer)
microprocessor is the most frequently used and significant one. Beneath certain conditions, the devices based
on this processor will offer important benefits over CISC (complex instruction set computer). In the above, a
brief comparison between both the processors is discussed.

The RISC processor performance is two to four times higher as compared with CISC processors due to the basic
instruction set. The architecture of this processor uses very little space because of the decreased instruction
set and this will make additional functions such as memory management or floating-point arithmetic units on a
similar chip. The example demonstrates yet the problems associated with the CISC technology’s complex
instructions, which directly influence the complexity of the CU.

Figure 1 is a schematic visual representation of the CISC

instruction lengths. The first part in the schematic figure, the
Opcode of the first instruction is one byte while for the second Figure 2 depicts the schematic RISC technology principles. There
and third instructions it is two bytes. The next field or fields are are four different instructions in which the Opcode is always one
the instructions’ operands. In the first instructions, both operands byte and each instruction has two operands each one occupies
occupy one byte each. In the second instruction, there is just one two bytes.
operand that requires two bytes. In the third instruction, there
are two operands, the first needs three bytes and the second just
one byte.

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PIPELINE

Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing
and executing instructions in an orderly process. It is also known as pipeline processing. Pipelining is a
technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and
these stages are connected with one another to form a pipe like structure. Instructions enter from one end
and exit from another end.

In pipeline system, each segment consists of an input register followed by a combinational circuit. The register
is used to hold data and combinational circuit performs operations on it. The output of combinational circuit is
applied to the input register of the next segment.

Pipeline system is like the modern day assembly line setup in factories. For example in a car manufacturing
industry, huge assembly lines are setup and at each point, there are robotic arms to perform a certain task,
and then the car moves on ahead to the next arm.

Types of Pipeline

i) Arithmetic Pipeline

Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations,
multiplication of fixed point numbers etc. For example:
The input to the Floating Point Adder pipeline is:

𝑋 = 𝐴 ∗ 2^𝑎 Here 𝐴 and 𝐵 are mantissas (significant digit of floating

𝑌 = 𝐵 ∗ 2^𝑏 point numbers), while 𝑎 and 𝑏 are exponents.

The floating point addition and subtraction is done in 4 parts:

1. Compare the exponents.
2. Align the mantissas.
3. Add or subtract mantissas
4. Produce the result.
Registers are used for storing the intermediate results between the above operations.

ii) Instruction Pipeline

In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an
instruction cycle. This type of technique is used to increase the throughput of the computer system.
An instruction pipeline reads instruction from the memory while previous instructions are being executed in
other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will
be more efficient if the instruction cycle is divided into segments of equal duration.

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VECTOR PROCESSING

A Scalar processor is a normal processor, which works on simple instruction at a time, which operates on
single data items. But in today's world, this technique will prove to be highly inefficient, as the overall
processing of instructions will be very slow.

There is a class of computational problems that are beyond the capabilities of a conventional computer.
These problems require vast number of computations on multiple data items that will take a conventional
computer (with scalar processor) days or even weeks to complete.

Such complex instructions, which operates on multiple data at the same time, requires a better way of
instruction execution, which was achieved by Vector processors.
Vector processor, not only use Instruction pipeline, but it also pipelines the data, working on multiple data at
the same time.

A normal scalar processor instruction would be ADD A, B, which leads to addition of two operands, but what
if we can instruct the processor to ADD a group of numbers(from 0 to n memory location) to another group
of numbers(let’s say, n to k memory location). This can be achieved by vector processors.
In vector processor a single instruction, can ask for multiple data operations, which saves time, as instruction
is decoded once, and then it keeps on operating on different data items.

A vector processor implements better with higher vectors because of the foundation delay in a pipeline.
Vector processing decrease the overhead related to maintenance of the loop-control variables which creates
it more efficient than scalar processing.

Applications of Vector Processors:

Computer with vector processing capabilities are in demand in specialized applications. The following are
some areas where vector processing is used:

1. Petroleum exploration.
2. Medical diagnosis.
3. Data analysis.
4. Weather forecasting.
5. Aerodynamics and space flight simulations.
6. Image processing.
7. Artificial intelligence.

Pipelining Hazards

Whenever a pipeline has to stall due to some reason it is called pipeline hazards. Below we discuss four
pipelining hazards.

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 I. Data Dependency

A difficulty that may cause a degradation of performance in an instruction pipeline is due to possible collision
of data or address. A data dependency occurs when an instruction needs data that are not yet available. An
address dependency may occur when an operand address cannot be calculated because the information
needed by the addressing mode is not available.

Pipelined computers deal with such conflicts between data dependencies in a variety of ways
a) Hardware interlocks: an interlock is a circuit that detects instructions whose source operands are
destinations of instructions farther up in the pipeline. This approach maintains the program
sequence by using hardware to insert the required delays.

b) Operand forwarding: uses special hardware to detect a conflict and then avoid it by routing the data
through special paths between pipeline segments. This method requires additional hardware paths
through multiplexers as well as the circuit that detects the conflict.

c) Delayed load: the compiler for such computers is designed to detect a data conflict and reorder the
instructions as necessary to delay the loading of the conflicting data by inserting no-operation
instructions.

II. Memory Delay

When an instruction or data is required, it is first searched in the cache memory if not found then it is a cache
miss. The data is further searched in the memory which may take ten or more cycles. So, for that number of
cycle the pipeline has to stall and this is a memory delay hazard. The cache miss, also results in the delay of
all the subsequent instructions.

III. Branch Delay

Suppose the four instructions are pipelined I1, I2, I3, I4 in a sequence. The instruction I1 is a branch
instruction and its target instruction is Ik. Now, processing starts and instruction I1 is fetched, decoded and
the target address is computed at the 4th stage in cycle t3.
But till then the instructions I2, I3, I4 are fetched in cycle 1, 2 & 3 before the target branch address is
computed. As I1 is found to be a branch instruction, the instructions I2, I3, I4 has to be discarded because the
instruction Ik has to be processed next to I1. So, this delay of three cycles 1, 2, 3 is a branch delay

IV. Resource Limitation

If the two instructions request for accessing the same resource in the same clock cycle, then one of the
instruction has to stall and let the other instruction to use the resource. This stalling is due to resource
limitation. However, it can be prevented by adding more hardware.

Advantages of Pipelining:

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  The cycle time of the processor is reduced; increasing the instruction throughput. Pipelining doesn't
reduce the time it takes to complete an instruction; instead it increases the number of instructions that
can be processed simultaneously ("at once") and reduces the delay between completed instructions
(called 'throughput'). The more pipeline stages a processor has, the more instructions it can process "at
once" and the less of a delay there is between completed instructions. Every predominant general
purpose microprocessor manufactured today uses at least 2 stages of pipeline up to 30 or 40 stages.

 If pipelining is used, the CPU Arithmetic logic unit can be designed faster, but more complex.

 Pipelining in theory increases performance over an un-pipelined core by a factor of the number of
stages (assuming the clock frequency also increases by the same factor) and the code is ideal for
pipeline execution.

 Pipelined CPUs generally work at a higher clock frequency than the RAM clock frequency, (as of 2008
technologies, RAMs work at a low frequencies compared to CPUs frequencies) increasing computers
overall performance.

Disadvantages of Pipelining:

Pipelining has many disadvantages though there are a lot of techniques used by CPUs and compilers
designers to overcome most of them; the following is a list of common drawbacks:

 The design of a non-pipelined processor is simpler and cheaper to manufacture, non-pipelined

processor executes only a single instruction at a time. This prevents branch delays (in Pipelining, every
branch is delayed) as well as problems when serial instructions being executed concurrently.

 In pipelined processor, insertion of flip flops between modules increases the instruction latency
compared to a non-pipelining processor.

 A non-pipelined processor will have a defined instruction throughput. The performance of a pipelined
processor is much harder to predict and may vary widely for different programs.

 Unfortunately, not all instructions are independent. In a simple pipeline, completing an instruction may
require 5 stages. To operate at full performance, this pipeline will need to run 4 subsequent
independent instructions while the first is completing. Any of those 4 instructions might depend on the
output of the first instruction, causing the pipeline control logic to wait and insert a stall or wasted
clock cycle into the pipeline until the dependency is resolved. Fortunately, techniques such as
forwarding can significantly reduce the cases where stalling is required.

 Self-modifying programs may fail to execute properly on a pipelined architecture when the instructions
being modified are near the instructions being executed. This can be caused by the instructions may
already being in the Prefetch Input Queue, so the modification may not take effect for the upcoming
execution of instructions. Instruction caches make the problem even worse.

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Reference

[1] Yadin, A. (2020). Computer Systems Architecture (Chapman & Hall/CRC Textbooks in

Computing) (1st ed.). Routledge.

[2] Difference Between RISC and CISC - javatpoint. (2015). Www.Javatpoint.Com.

https://www.javatpoint.com/risc-vs-cisc

[3] Vishwa, A. (2013b). Computer Organization and Architecture (0 ed.). I K International

Publishing House.

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