Si3443BDV

Vishay Siliconix

P-Channel 2.5-V (G-S) MOSFET

PRODUCT SUMMARY FEATURES

VDS (V) RDS(on) (Ω) ID (A)
• Halogen-free According to IEC 61249-2-21
Definition
0.060 at VGS = - 4.5 V - 4.7 • TrenchFET® Power MOSFET
- 20 0.090 at VGS = - 2.7 V - 3.8 • 100 % Rg Tested
0.100 at VGS = - 2.5 V - 3.7
• Compliant to RoHS Directive 2002/95/EC

TSOP-6 (4) S
Top V iew

1 6

3 mm (3) G
2 5

3 4

2.85 mm
(1, 2, 5, 6) D
Ordering Information: Si3443BDV-T1-E3 (Lead (Pb)-free)
Si3443BDV-T1-GE3 (Lead (Pb)-free and Halogen-free)
Part Marking Code: 3B P-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5s Steady State Unit
Drain-Source Voltage VDS - 20
V
Gate-Source Voltage VGS ± 12
TA = 25 °C - 4.7 - 3.6
Continuous Drain Current (TJ = 150 °C)a ID
TA = 70 °C - 3.8 - 2.8
A
Pulsed Drain Current IDM - 20
Continuous Source Current (Diode Conduction)a IS - 1.7 - 0.9
TA = 25 °C 2.0 1.1
Maximum Power Dissipationa PD W
TA = 70 °C 1.3 0.7
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit
t≤5s 50 62.5
Maximum Junction-to-Ambienta RthJA
Steady State 90 110 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 30 36
Notes
a. Surface Mounted on FR4 board, t ≤ 5 s.

For SPICE model information via the Worldwide Web: www.vishay.com/www/product/spice.htm

Document Number: 72749 www.vishay.com

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Si3443BDV
Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.6 - 1.4 V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 12 V ± 100 nA
VDS = - 20 V, VGS = 0 V -1
Zero Gate Voltage Drain Current IDSS µA
VDS = - 20 V, VGS = 0 V, TJ = 70 °C -5
On-State Drain Currenta ID(on) VDS = - 5 V, VGS = - 4.5 V - 15 A
VGS = - 4.5 V, ID = - 4.7 A 0.048 0.060
Drain-Source On-State Resistance a RDS(on) VGS = - 2.7 V, ID = - 3.8 A 0.070 0.090 Ω
VGS = - 2.5 V, ID = - 1 A 0.080 0.100
Forward Transconductancea gfs VDS = - 10 V, ID = - 4.7 A 11 S
a VSD IS = - 1.7 A, VGS = 0 V - 0.8 - 1.2 V
Diode Forward Voltage
Dynamicb
Total Gate Charge Qg 6 9
Gate-Source Charge Qgs VDS = - 10 V, VGS = - 4.5 V, ID = - 4.7 A 1.4 nC
Gate-Drain Charge Qgd 1.9
Gate Resistance Rg f = 1 MHz 5 9.5 16.2 Ω
Turn-On Delay Time td(on) 22 35
Rise Time tr VDD = - 10 V, RL = 10 Ω 35 55
Turn-Off Delay Time td(off) ID ≅ - 1.0 A, VGEN = - 4.5 V, Rg = 6 Ω 45 70
ns
Fall Time tf 25 40
Source-Drain Reverse Recovery
trr IF = - 1.7 A, dI/dt = 100 A/µs 25 50
Time
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

20 20
VGS = 5 V thru 3.5 V TC = - 55 °C
3V

16 16 25 °C
ID - Drain Current (A)

125 °C
ID - Drain Current (A)

12 12
2.5 V

8 8

2V
4 4

1.5 V
0 0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

www.vishay.com Document Number: 72749

2 S-09-0660-Rev. C, 20-Apr-09
 Si3443BDV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.20 1000

0.16 800
R DS(on) - On-Resistance (Ω)

C - Capacitance (pF)
VGS = 2.7 V Ciss
0.12 600
VGS = 2.5 V

0.08 400

VGS = 4.5 V
Coss
0.04 200

Crss
0.00 0
0 4 8 12 16 20 0 4 8 12 16 20

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current Capacitance

5 1.6
ID = 4.7 A
ID = 4.7 A
1.5
VGS - Gate-to-Source Voltage (V)

4 1.4
RDS(on) - On-Resistance

VDS = 10 V 1.3
VGS = 10 V
(Normalized)

3 1.2

1.1

2 1.0

0.9

1 0.8

0.7

0 0.6
0 1 2 3 4 5 6 7 8 - 50 - 25 0 25 50 75 100 125 150
Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)
Gate Charge On-Resistance vs. Junction Temperature

30 0.20

0.16
R DS(on) - On-Resistance (Ω)

TJ = 150 °C TJ = 25 °C
IS - Source Current (A)

10 ID = 1 A
0.12

ID = 4.7 A

0.08

0.04

1 0.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4 5
VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

Document Number: 72749 www.vishay.com

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Si3443BDV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.6 50

0.4 40

ID = 250 µA
VGS(th) Variance (V)

30

Power (W)
0.2

0.0 20

- 0.2 10

- 0.4 0
- 50 - 25 0 25 50 75 100 125 150 10- 3 10- 2 10- 1 1 10 100 600

TJ - Temperature (°C) Time (s)

Threshold Voltage Single Pulse Power

100
IDM Limited
Limited by R(DS)on*

10
ID - Drain Current (A)

P(t) = 0.001 s
1
ID(on) P(t) = 0.01 s
Limited
P(t) = 0.1 s
TA = 25 °C P(t) = 1 s, 10 s
0.1 Single Pulse
DC
BVDSS Limited
0.01
0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2
Notes:

0.1
0.1 PDM

0.05 t1
t2
t1
1. Duty Cycle, D =
0.02 t2
2. Per Unit Base = RthJA = 90 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10-4 10-3 10-2 10-1 1 10 100 600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient

www.vishay.com Document Number: 72749

4 S-09-0660-Rev. C, 20-Apr-09
 Si3443BDV
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2

0.1
0.1
0.05

0.02

Single Pulse
0.01
10-4 10-3 10-2 10-1 1 10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72749.

Document Number: 72749 www.vishay.com

S-09-0660-Rev. C, 20-Apr-09 5
 Package Information
Vishay Siliconix

TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C

e1 e1

5 4 6 5 4

E1 E E1 E

1 1
2 3 2 3
-B- -B-

e b 0.15 M C B A e b 0.15 M C B A

5-LEAD TSOP 6-LEAD TSOP

-A- 4x 1
D 0.17 Ref
R c

A2 A R L2
Gauge Plane

Seating Plane Seating Plane

L
0.08 C -C- A1
(L1)
4x 1

MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.91 - 1.10 0.036 - 0.043
A1 0.01 - 0.10 0.0004 - 0.004
A2 0.90 - 1.00 0.035 0.038 0.039
b 0.30 0.32 0.45 0.012 0.013 0.018
c 0.10 0.15 0.20 0.004 0.006 0.008
D 2.95 3.05 3.10 0.116 0.120 0.122
E 2.70 2.85 2.98 0.106 0.112 0.117
E1 1.55 1.65 1.70 0.061 0.065 0.067
e 0.95 BSC 0.0374 BSC
e1 1.80 1.90 2.00 0.071 0.075 0.079
L 0.32 - 0.50 0.012 - 0.020
L1 0.60 Ref 0.024 Ref
L2 0.25 BSC 0.010 BSC
R 0.10 - - 0.004 - -
0 4 8 0 4 8

1 7 Nom 7 Nom
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540

Document Number: 71200 www.vishay.com

18-Dec-06 1
 AN823
Vishay Siliconix

Mounting LITTLE FOOTR TSOP-6 Power MOSFETs

Surface mounted power MOSFET packaging has been based on Since surface mounted packages are small, and reflow soldering
integrated circuit and small signal packages. Those packages is the most common form of soldering for surface mount
have been modified to provide the improvements in heat transfer components, “thermal” connections from the planar copper to the
required by power MOSFETs. Leadframe materials and design, pads have not been used. Even if additional planar copper area is
molding compounds, and die attach materials have been used, there should be no problems in the soldering process. The
changed. What has remained the same is the footprint of the actual solder connections are defined by the solder mask
packages. openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.

The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package A final item to keep in mind is the width of the power traces. The
outline drawing see http://www.vishay.com/doc?71200 and see absolute minimum power trace width must be determined by the
http://www.vishay.com/doc?72610 for the minimum pad footprint. amount of current it has to carry. For thermal reasons, this
In converting the footprint to the pad set for a power MOSFET, you minimum width should be at least 0.020 inches. The use of wide
must remember that not only do you want to make electrical traces connected to the drain plane provides a low impedance
connection to the package, but you must made thermal connection path for heat to move away from the device.
and provide a means to draw heat from the package, and move it
away from the package.
REFLOW SOLDERING
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated Vishay Siliconix surface-mount packages meet solder reflow
circuit, typical connections would be made with traces that are reliability requirements. Devices are subjected to solder reflow as a
0.020 inches wide. Since the drain pins serve the additional test preconditioning and are then reliability-tested using
function of providing the thermal connection to the package, this temperature cycle, bias humidity, HAST, or pressure pot. The
level of connection is inadequate. The total cross section of the solder reflow temperature profile used, and the temperatures and
copper may be adequate to carry the current required for the time duration, are shown in Figures 2 and 3.
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.

Figure 1 shows the copper spreading recommended footprint for

the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25

Ramp-Up Rate +6_C/Second Maximum

0.074
Temperature @ 155 " 15_C 120 Seconds Maximum
1.875
0.014 0.122
0.35 3.1 Temperature Above 180_C 70 − 180 Seconds
0.026 Maximum Temperature 240 +5/−0_C
0.65
Time at Maximum Temperature 20 − 40 Seconds

0.049 0.049 0.010 Ramp-Down Rate +6_C/Second Maximum

1.25 1.25 0.25

FIGURE 1. Recommended Copper Spreading Footprint FIGURE 2. Solder Reflow Temperature Profile

Document Number: 71743 www.vishay.com

27-Feb-04 1
AN823
Vishay Siliconix

10 s (max)
255 − 260_C

1X4_C/s (max) 3-6_C/s (max)

217_C
140 − 170_C

60 s (max)

3_C/s (max) 60-120 s (min) Reflow Zone

Pre-Heating Zone

Maximum peak temperature at 240_C is allowed.

FIGURE 3. Solder Reflow Temperature and Time Durations

THERMAL PERFORMANCE

A basic measure of a device’s thermal performance is the On-Resistance vs. Junction Temperature
junction-to-case thermal resistance, Rqjc, or the 1.6
junction-to-foot thermal resistance, Rqjf. This parameter is VGS = 4.5 V
measured for the device mounted to an infinite heat sink and ID = 6.1 A
1.4
is therefore a characterization of the device only, in other
rDS(on) − On-Resiistance

words, independent of the properties of the object to which the

device is mounted. Table 1 shows the thermal performance
(Normalized)

1.2
of the TSOP-6.

1.0
TABLE 1.
Equivalent Steady State Performance—TSOP-6
0.8
Thermal Resistance Rqjf 30_C/W

0.6
−50 −25 0 25 50 75 100 125 150
SYSTEM AND ELECTRICAL IMPACT OF TJ − Junction Temperature (_C)
TSOP-6
FIGURE 4. Si3434DV
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).

www.vishay.com Document Number: 71743

2 27-Feb-04
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR TSOP-6

0.099
(2.510)
(3.023)

(1.626)
0.064
0.119

(0.699)
0.028

0.039 0.020 0.019

(1.001) (0.508) (0.493)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index
Return to Index
APPLICATION NOTE

www.vishay.com Document Number: 72610

26 Revision: 21-Jan-08
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