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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Efficient CVSL based Full Adder Realizations

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Kirti Gupta', Shrey Bagga2 and Neeta Pandel
, Electronics and Communication, Bharati Vidyapeeth 's College ofEngineering, Delhi, India
3 Electronics and Communication, Delhi Technological University, Delhi, India
E-mail: [email protected] [email protected] [email protected]

Abstract-This paper proposes new circuit realizations performance. The proposed realization contain only two
for full adder in cascade voltage switch logic (CVSL) style. levels of the NMOS transistor in the PDN instead of the
The basic CVSL based realization of the full adder use four four levels in basic CVSL logic which results in speed
levels of transistors resulting in increased delay value. So, in
enhancement [2].
order to improve the delay performance, three different
The paper first presents an introduction to the basics
circuit realizations involving only two levels of NMOS
transistors is proposed. The first proposed circuit realization
of CVSL style and explains the realization of the different
XOR gate based, the second one is XNOR gate based while logic functions in the style in section 11. Thereafter, the
the third one is XOR-XNOR based. The proposed full adder proposed circuit realizations are presented in Section III.
circuits are functionally verified in SyMICA by using 180 nm The functional verification along with their performance
technology CMOS technology parameters. Their comparison is carried out in Section IV. Lastly, the
performance is compared with the basic one shows a speed conclusion are drawn in Section V.
improvement by a factor more than 7. Also it is found that
the third circuit realization shows the maximum speed 11. BASICS OF CVSL STYLE
enhancement over the other two proposed realizations.
Although, the proposed circuits consume more power than A cascode voItage switch logic (CVSL) style is a
the basic architecture by a factor of 1.48. ratioed logic style that has the characteristics of rail-to-rail
Keywords-Digital; Full Adders; Cascade Voltage Switch output and static currents elimination in the circuit. It is a
Logic; High Speed logic style which requires inputs in the true and
complementary form and consequently produces output in
I. INTRODUCTION
both true and complementary form. These gates maintain a
Now a day, there is an increasing demand of portable positive feedback through cross-coupled PMOS load
devices; as a resuIt the semiconductor industry is transistors to ensure that the load is completely OFF when
perpetually improving the circuit design in terms of it is not required. A general structure a CVSL gate is
lowering the power, increasing speed or reducing the depicted in Fig. 1. The PMOS load transistors MI and M2
silicon chip area. The cascade voItage swing logic helps to form a latch which stores data. The pull down network
address these problems by eliminating the static power (PDN) has two complementary block wherein one branch
consumption and the providing the true and complement implements the logic function F while the other
form of the outputs in a single gate only. Some of the implements the F. As there exists complementary
advantages offered by the CVSL style includes based less branches in the PDN, only one of the network is active at a
number of transistors, reduced delay and area. Moreover, given time, so only one of the path is available for VDD to
CVSL has been found to offer performance advantage of drop down to OV. These outputs are preserved using the
up to 4X compared to CMOS primitive logic families latch mentioned above [1, 2].
Vdd
while maintaining the low power characteristics. As the
number of PMOS is significantly reduced, the PMOS to
NMOS spacing can be relaxed, which reduces the device/
process complexity burden for CVSL design [1].
In this paper, the implementation of fulI adders in the
CVSL is addressed. A full adder is one the most versatile Q _-----1---.../
'----1--,-- Q
circuit element used ahnost in all computing elements
ranging from simple circuits subtracters, multipliers and Differential
Inputs
division circuits to more complex circuits like comparator,
parity checkers, compressors, multi-rate filter bank (used
in biomedical engineering), etc. The conventional CVSL
based architecture of full adders employs the arran gement
of NMOS transistor in four levels which resuIts in Gnd
increased delay values. This paper proposes, three
Fig. I: Basic Block Diagram of CVSL Circuit
different circuit realizations to improve the delay

978-1-4673-8587-9/16/$31.00 ©2016 IEEE [1]

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Based on these observations for logic function Based on this method, the implementation of a full
realization in CVSL style, the circuits of a two input adder is drawn. A basic full adder is a combinational
exclusive-OR (XOR) gate and a 2: 1 multiplexer (MUX) is circuit that adds three inputs namely, A, B and carry (CIN)
shown in Fig. 2 and Fig. 3 respectively [3]. Both the that produces SUM and COUT as the outputs [5]. The
circuits has two levels of NMOS transistors in their PDN. Boolean expression for the Sum is the XOR of the three
The XOR circuit in Fig. 2 has two inputs A and B where inputs which is expanded as the sum of products in eq.
the PDN is implemented by (5).This is done to facilitate the implementation in the
F=Ä-B+B·A (1) CVSL style.
F = (A+B) . (B+Ä) (2) SUM=AEElBEElCIN (5)
The complement of this function is implemented (F) SUM = A· B· eIN +,4. B· eIN +,4. B· eIN + A· B· eIN
is implemented on the corresponding stack. Both of the (6)
NMOS stacks consists of two levels. The circuit generates COUT =A . B + CIN (AEElB)• (7)
both XOR and XNOR output. COUT =A . B+A . B . CIN +Ä . B . CIN (8)
The implementation of the above equation in CVSL
style is shown in Fig. 4. It infers stacking of fOUf NMOS
in the pull down network (PDN). Similarly, the Boolean
expression for the COUT is represented in eq. (7) in the sum
of product. On closer examination, the CVSL
Q-----1 t---- Q implementation will again have fOUf levels of NMOS
transistors in the PDN. The arrangement of transistors in
the fOUf levels adds to the delay by increasing the overall
I-A contribution of the parasitic transistor capacitance at the
output node [6]. To reduce the delay and hence to increase
�8 the speed of the full adder operation in CVSL style, three
circuit realizations are proposed in the paper. These
realizations are described in further detail in the following
section.

Gnd

Fig. 2: CVSL based 2-input XOR Gate

Vdd

Q ----i

(a)

Gnd

Fig. 3: CVSL based 2: 1 MUX

For a 2:1 MUX, the inputs were A, B and S (Select

Line) and the outputs were Q and Q. The functionality of
the MUX is expressed as:
Y = 10, S+ 11 . S (3)
Y = (Tc; + S) . (� + S) (4)
Even in this circuit, we have implemented the
complement of Y in the adjacent stack, which leads to a (b)

two level stacking in both PDN [4]. Fig. 4: Conventional CVSL Full Adder a) Sum Circuit b) Carry Circuit

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

III. PROPOSED CVSL BASED FULL ADDERS A

In this section three different circuit realizations to SUM

implement high speed full adders in CVSL style are
proposed.
C" �-----11-�
A. Proposed circuit realization-i (PC-i)
The first circuit realization, the use of two 2-input
2:1
XOR gates and 2: 1 multiplexer is proposed. The block MUX
1---- Co",

diagram of the proposed circuit is shown in Fig. 5. The

logical realization of the same can be explained. Consider
a variable X whose value is equal to A EB B. Now using
Fig. 6: Block Diagram of Proposed Circuit Realization-2
this let us see how we can implement the equations given
in eq. (5) and eq. (7). These equations are modified as C. Proposed Circuit Realisation-3 (PC-3)
folIows:
SUM X EB CIN = (9) In this circuit realization we utilize the characteristics
feature of CVSL of providing the true and the complement
COUT A . X+CIN . X
= (10)
forms of the function. The implementation of PC-3 is
So, in order to generate SUM, we cascade two XOR
shown in Fig. 7. The logical expression for the same is as
gates and COUT is generated by using 2: 1 MUX whose
folIows:
select line is the output of the first XOR gate [7]. The
MOS schematics of the XOR gate and MUX in Fig. 2 and SUM X EB CIN= (13)
Fig. 3 are used for the purpose. SUM X·CIN + X·CIN
= (14)
COUT A .
= X+ CIN . X (15)
A This is same as expression of PC-l but, here we use
SUM
two 2:1 MUX and XOR and XNOR gates. Although as we
are using CVSL based circuits, we have used one XOR
gate instead of two, because CVSL based circuits provide
�" �-------;---. us with complementary outputs. Hence, there is a
reduction of hardware used [7]. The key difference in this
architecture is that here we have used a MUX to
2:1
MUX
1----- COUT implement SUM, where its inputs are XOR and XNOR of
A and B and the select line is CIN. As a result, in this
architecture we have used one, two input XOR gate, one
two input XNOR gate and two, 2:1 multiplexers for
Fig. 5: Block Diagram of the Proposed Circuit Realization-l
generation of desired outputs of SUM and COUT.
A
B. Proposed Circuit Realization-2 (PC-2)
2:1
1--- SUM
The second proposed circuit realization (PC-2) is MUX

similar to circuit realization-l (PC-l) except that XOR

gate is replaced with XNOR gate. But as we are using
CVSL logic style, we can use the same XOR gate because
C" -11----+--.....---'
we get bot true and complementary outputs. This increases
the reusability of the circuit. The logical expression for I,

PC-2 can be realized using the equations given below, 2:1

MUX 1----- Co",
provided we assume that A EB B is equal to X [7].
SUM X EB CIN = (11)
COUT A . X+CIN . X
= (12)
These same equations are represented in the block
Fig. 7: Block Diagram of Proposed Circuit Realization-3
diagram shown in Fig. 6. The main difference comes in
the inputs to 2: 1 MUX where input A goes in I1 because X
,
IV. RESULTS
is the output from the first XNOR circuit. So, when X is
high, A should be the output of the multiplexer, therefore In this section the functional verification of the
A is the input to 11• Similarly, CIN is the input to 10 which proposed circuit realization is put forward which is
is the reverse of what we had in PC-I. followed by performance comparison All the circuits

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

(Basic and the proposed circuit 1-3) are simulated on E. Performance Comparison
SyMICA Design Environment tool using 180 nm CMOS
The delay performance of the basic CVSL adder (as
technology parameter. All the circuits are simulated with a
given in Fig. 4) is compared with proposed circuits (PCl-
power supply of 1.8 V and the length of all MOSFET is
3). The results are compiled in Table 11. The ratio of delay
kept at minimum feature size. The width of transistors is
between the basic CVSL full adder and different proposed
calculated so as to keep the aspect ratio of PMOS to aspect
circuits is surnm arized in Table III. The ratio of delay of
ratio of NMOS as two. basic architecture to PC- 1 is given by "B: 1". Similarly,
D. Functional Verification "B:2" and "B:3" denoted ratio of basic CVSL based
architecture to PC- 2 and PC- 3 based architectures,
For functional verification of the proposed circuit, the respectively. It is found that the proposed full adder
truth table of the full adder is drawn in Table I. The circuits are advantageous over basic CVSL counterpart as
simulation waveforms obtained for the SUM and COUT of they use cascaded stages of two input XOR gate rather
PC-l is shown in Fig. 8 and Fig. 9 respectively. On than a single stage of three input XOR gate. Along with
comparison of desired result from the truth table, it is the cascaded stages, we use a MUX to generate COUT
observed that the output is exactIy as expected. Therefore, (Carry_out). As a resuIt, we get a significant speedup in
PC-l conforms the functionality of full adder. The same the full adder circuit. Out of the three proposed circuits it
can be observed that the PC-3 show the fastest
resuIts were obtained for the rest of the two proposed
performance in terms of the SUM circuit whereas of COUT
circuits (PC-2 and PC-3) and are not shown for the sake of
PC-2 and PC-3 shows comparable resuIts. Hence it can be
brevity. concluded that PC-3 can be used to realize high speed
TABLE 1: TRUTH TABLE FOR FULL ADDER CVSL full adders.
A B C SUM COUT
TABLE 2: DELAy RESULTS (ps)
0 0 0 0 0
Output Basic PC-l PC-2 PC-3
0 0 1 1 0
Sum 3475 465 465 460
0 1 0 1 0
Cout 990 495 475 480
0 1 1 0 1
1 0 0 1 0 TABLE 3: DELAy RAnON
1 0 1 0 1
Output B:l B:2 B:3
1 1 0 0 1
Sum 7.47 7.47 7.55
1 1 1 1 1
Cout 2 2.08 2.06

Power measurements of basic and proposed

realization circuits were performed. The dynamic power
of basic CVSL based full adder, PC- 1, PC- 2 and PC-3
are 8.25f.!W, 12.28f.!W, 12.28f.!W and 12.29f.!W
respectively. As the ratio of power consumption of basic
CVSL based full adder to the proposed architectures is
approximately 1.48, there exists a tradeoff between power
and delay. This tradeoff can be used to get an optimum
design according to application.
Fig. 8: Output Waveform of Sum V. CONCLUSION

In this paper three different circuit realizations for

CVSL full adder are proposed. These realization propose
three different ways to realize a CVSL full adder having
two levels of NMOS transistors in contrast to the four
levels in basic CVSL full adder realization. This
modification in the realization leads to significant speed
improvement with marginal increase in power
consumption over the basic counterpart which has been
validated through simulations in SyMICA design
environment by using 180 nm technology CMOS
Fig. 9: Output Waveform of C OUT technology parameters.

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

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