Integrated Circuits and Its Applications - Unit 5 - WWW - Rgpvnotes.in

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Department of Electronics and Communication Engineering

Subject Name: Integrated Circuits and its Applications Subject Code: EC4003
UNIT-V Subject Notes
OP-AMP AS FILTERS: Characteristics of filters, Classification of filters, Magnitude and frequency response,
Butterworth 1st and 2nd order Low pass, High pass and band pass filters, Chebyshev filter characteristics, Band
reject filters, Notch filter; all pass filters, self-tuned filters, AGC, AVC using OP-AMP.
TIMER: IC-555 Timer concept, Block pin configuration of timer. Monostable, Bistable and astable Multivibrator
using timer 555-IC, Schmitt Trigger, Voltage limiters, Clipper and clampers circuits, Absolute value output circuit,
Peak detector, Sample and hold Circuit, Precision rectifiers, Voltage-to-current converter, Current-to-voltage
converter.
Voltage Regulator: simple OP-AMP Voltage regulator, Fixed and Adjustable Voltage Regulators, Dual Power
supply, Basic Switching Regulator and characteristics of standard regulator ICs.
OP-AMP AS FILTERS (ACTIVE FILTERS):

Filter is a frequency selective circuit that passes a specific band of frequencies and blocks the frequencies outside
this band. Depending on the type of elements used in their construction, filters are classified as active or passive.
Passive filters used passive components such as resistors, capacitors and inductors whereas active filters used
active components such as transistors or op-amps in addition to resistors and capacitors. The type of elements
used dictates the operating frequency of the filter. RC filters are used for low or audio frequency operation,
whereas LC filters are used for RF or high frequency operation. In audio frequencies, inductors are not used
because they are very large, costly and dissipate more power. Inductors also produce magnetic fields.
Advantage of active filter over passive filter:
1. Gain and frequency adjustment flexibility: Active filter containing active components such as op-amp, is
capable of providing a gain, hence the input signal is not attenuated as in passive filter. In addition, active filter is
easier to tune or adjust.
2. No loading problems: Because of high input impedance and low output impedance of op-amp, active filter does
not cause loading of source or load.
3. Cost: Because of absence of inductors and use of cheaper op-amp in filter circuit, active filters are more
economical than passive filters.
TYPES OF FILTERS:
Most commonly type of active filter used are:
(1)Low-pass filter (2) High-pass filter (3) Band-pass filter (4) Band-reject filter (5) All-pass filter
MAGNITUDE AND FREQUENCY RESPONSE OF FILTERS:

All these filters use op-amp as the active element and resistors and capacitors as passive elements. Active element
improves the filter performance through their increased slew rates and higher unity gain-bandwidths.
Gain Gain
Ideal Response
Ideal Response
1 1
Pass Band Stop Band Stop Band Pass Band

fH Frequency fL Frequency
Figure 6.01: Low pass filter frequency response Figure 6.02: High pass filter frequency response
Comparator Comparator
By - Vikas Bhujade
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Gain Ideal Response Gain

Ideal Response
1 1
Stop Band Stop Band Stop Band
0.707 0.707
Pass Band Pass Band Pass Band
fL fC fH Frequency fL fC fH Frequency
Figure 6.03: Band pass filter frequency response Figure 6.04: Band reject filter frequency response
Comparator Comparator
All type of filter frequency responses are shown from figure 6.01 to
Voltage 6.04 except all pass filters. A dashed curve indicates the response of
Vin
VO ideal filter whereas solid lines indicate practical filter response. Figure
1 6.01 shows the frequency response of low pass filter. A low pass filter
has a constant gain from 0Hz to fH (high cutoff frequency). Therefore
bandwidth is also fH. After fH the gain decreases by 3dB ie. f > fH the
t gain decreases with increase in input frequency. Hence, frequencies
─1 between 0Hz and fH are known as pass band frequencies, whereas
ᶲ beyond fH includes stop band frequencies. An ideal filter has zero
attenuation in pass band and infinite attenuation in stop band.
Figure 6.05: All Pass Filter Practical circuits cannot produce the ideal response, but a close ideal
response can be obtained by using special design techniques, precise
Comparator component values and high speed op-amps.
Some of the commonly used practical filters that approximate the ideal filter response are: (i) Butterworth filter (ii)
Chebyshev filter (iii) Cauer filter
Butterworth filter also called as flat-flat filter because it has flat stop and pass band. Chebyshev filter has a ripple
pass band and flat stop band, while the cauer filter has ripple pass and stop band.
Figure 6.02 shows a high pass filter with stop band is from frequency (f >0) to frequency (f<fL) while pass band is
for frequencies (f > fL) where, fL is low cut off frequency and f is the operating frequency.
Figure 6.03 shows a band pass filter with pass band is between the two cut off frequencies fH and fL here (fH>fL).
The two stop bands are for frequencies (f>0) to (f< fL) and (f > fH). The bandwidth of the band pass filter, therefore,
is equal to (fH ─ fL). fC is the center frequency.
Figure 6.04 shows a band reject or band-stop or band-elimination filter with stop band is between the two cut off
frequencies fH and fL here (fH<fL). The two pass bands are from frequencies (f>0) to (f< fH) and (f > fL). fC is the
center frequency.
Figure 6.05 shows the input (Vin) and output (VO) signals of all pass filter where there is a phase shift (ф) between
input and output signals as a function of frequency. This filter passes all frequencies keeping input and output
voltages amplitude equal for all frequencies. The highest frequency up to which the input and output amplitudes
remain equal is dependent on the unity gain-bandwidth of the op-amp. At this frequency, the phase shift between
input and output is maximum.
The rate at which the gain of the filter changes in the stop band is determined by the order of the filter. For
example, for first order filter, the roll-off rate in stop band is 20dB/decade, on the other hand, for second order
filter, the roll-off rate in stop band is 40dB/decade.
FIRST ORDER LOW PASS BUTTERWORTH FILTER:

Figure 6.06 (a) and (b) shows the circuit diagram of first order low pass butterworth filter and frequency response
plot. Here op-amp is used in non-inverting mode and RC network for filtering. Resistance R IN and RF determine the
gain of the filter.
By - Vikas Bhujade
RF
Gain
RIN +VCC
2 7 ─20dB/decade
V2  6
R V1 741 AF
3
+ 4 VO 0.707AF
C VEE
VIN Pass Band Stop Band

fH Frequency
Figure 6.06(a): First order low pass filter Figure 6.06(b): Frequency response
According to the voltage divider rule, the voltage at the non-inverting terminal (across the capacitor C) is
Comparator
−𝑗𝑋 1 𝑉
𝑉1 = 𝑅−𝑗𝑋𝐶 𝑉𝐼𝑁 Where, j = √-1 and −𝑗𝑋𝐶 = 𝑗2𝜋𝑓𝐶 therefore 𝑉1 = 1+𝑗2𝜋𝑓𝑅𝐶
𝐼𝑁
𝐶
And the output voltage, VO = [1 + (RF/RIN)] V1 ie. VO = [1 + (RF/RIN)] [VIN / (1+j2π.f.R.C)] OR
VO/VIN = AF / (1+j2π.f.R.C) = AF / [(1+j(f/fH)] where, (VO/VIN ) is the gain of the filter as a function of frequency.
AF = [1 + (RF/RIN)] = pass band gain of the filter, f is the frequency of input signal.
fH = 1/(2π.R.C) = high cutoff frequency of the filter.
The gain magnitude and phase angle equation is obtained by converting equation (V O/VIN ) into its equivalent
polar form, as follows-
𝐕𝐎 𝐀𝐅
| |=
𝐕𝐈𝐍 √𝟏 + (𝐟⁄𝐟𝐇 )𝟐
𝐟
and ∅ = − 𝐭𝐚𝐧−𝟏 (𝐟 ) where ф is the phase angle in degrees.
𝐇
The low pass filter operation can be varied from the gain magnitude equation as shown:
𝐕
(i) At very low frequencies, ie, f < fH, |𝐕 𝐎 | ≅ AF
𝐈𝐍
VO AF
(ii) At f = fH, | |= = 0.707AF
VIN √2
VO
(iii) At f > fH, |V | < AF
IN
A low pass filter has a constant gain AF from 0Hz to the cutoff frequency fH. At fH the gain is 0.707AF, and after fH it
decreases at a constant rate with an increase in frequency ie, when the frequency is increased tenfold (one
decade), the voltage gain is divided by 10 ie the gain decreases 20 dB (= 20 log 10) each time the frequency is
increased by 10. Frequency fH is known as high cutoff frequency or ─3dB frequency or break frequency or corner
frequency.
FIRST ORDER LOW PASS FILTER DESIGN STEPS:
(i) Choose a value of high cutoff frequency fH.
(ii) Select the value of C less than or equal to 1μF. Mylar or tantalum capacitors are used for better performance.
(iii) Calculate the value of R using : R = 1 / (2π. fH. C)
(iv) Select the values of RIN and RF depend on the desired pass band gain AF using AF = [1 + (RF/RIN)]
Example: Design a low pass filter at a cutoff frequency of 1 kHz with a pass band gain of 2.
Solution: fH = 1 kHz. Assume C = 0.01μF. Then, R = 1 / (2π. fH. C) = 1 / (2π)(103)(0.01μF) = 15.9kΩ
Since the pass band gain is 2, resistors RIN and RF must have equal values. Let RIN and RF is 10 kΩ.
FREQUENCY SCALING: Frequency scaling is the procedure used to convert an original cutoff frequency fH to a new
cutoff frequency fH’. Scaling is done by multiplying R or C, but not both, by the ratio of the original cutoff
frequency to the new cutoff frequency.
For example, to change a cutoff frequency from 1kHz to 1.6kHz, multiply 15.9 kΩ resistor by
Original cutoff frequency 1 kHz
= = 0.625 . Therefore, new resistor R = (15.9 kΩ)(0.625) = 9.94 kΩ.
new cutoff frequency 1.6 kHz
Thus the new cutoff frequency is fH’ = 1 / (2π. R. C) = 1 / (2π)(9.94x103)(0.01μF) = 1.6 kHz.
By - Vikas Bhujade
SECOND-ORDER LOW PASS BUTTERWORTH FILTER:
RF
Gain
RIN +VCC
2 ─40dB/decade
V2  7 6
R2 V1 741 AF
3
+ 4 VO 0.707AF
R1 C1 C2 VEE
VIN
Pass Band Stop Band
fH Frequency
Figure 6.07(a): Second order low pass filter Figure 6.07(b): Frequency response
Figure 6.07 (a) and (b) shows the circuit diagram of second order butterworth Comparatorlow pass filter and frequency
response plot. It consists of two RC networks for filtering and op-amp used in non-inverting mode. Resistance RIN
and RF determine the gain of the filter. Roll off of 40dB/decade is obtained in frequency response of second order
low pass filter. The high cut off frequency fH is determined by R1, C1, R2, C2, as follows-
fH = 1 / 2π.√( R1. C1. R2. C2) If R1= R2=R and C1 = C2= C, then fH = 1 / (2π.R.C)
For a second-order low pass butterworth filter response, the voltage gain magnitude equation is
𝐕𝐎 𝐀𝐅
| |= where AF = [1 + (RF/RIN)] = pass band gain of the filter and f is the frequency of input signal.
𝐕𝐈𝐍 √𝟏+(𝐟⁄𝐟𝐇)𝟒
SECOND ORDER LOW PASS FILTER DESIGN STEPS:

Design steps of second order low pass filter is same as first order low pass filter, except having twice RC network.
(i) Choose a value of high cutoff frequency fH.
(ii) Select the value of C ≤ 1μF. Mylar or tantalum capacitors are used for better performance. To simply design
calculations, set R1= R2=R and C1 = C2= C
(iii) Calculate the value of R using : R = 1 / (2π. fH. C)
(iv)Because of the equal resistor and capacitor values, the pass band gain AF using AF = [1 + (RF/RIN)] of second
order low pass filter has to be equal to 1.586 ie. RF = 0.586 RIN. This pass band gain is necessary for butterworth
response. Hence select the value of R IN ≤ 100kΩ and calculate the value of RF.
Example: Design a second order low pass filter at fH = 1kHz.
Solution: fH = 1 kHz. Assume C1 = C2= C = 0.0047μF.Then, R1= R2= R= 1/(2π.fH.C) = 1/(2π)(103)(0.0047μF) = 33.86kΩ
Since the pass band gain is 1.586, hence RF = 0.586 RIN and let RIN = 27 kΩ. Therefore RF = 15.82 kΩ. Hence, the
required components are RF = 15.82 kΩ, RIN = 27 kΩ, C1 = C2= C = 0.0047μF and R1= R2= R= 33.86kΩ.
FREQUENCY SCALING: Frequency scaling method of second order low pass filter is same as of first order low pass
filter.
FIRST ORDER HIGH PASS BUTTERWORTH FILTER:

Figure 6.08 (a) and (b) shows the circuit diagram of first order high pass butterworth filter and frequency response
plot. High pass filter is formed by interchanging frequency determining resistors and capacitors in low pass filter.
Here op-amp is used in non-inverting mode and RC network for filtering. Resistance R IN and RF determine the gain
of the filter.
By - Vikas Bhujade
RF
Gain
RIN +VCC
2 7 20dB/decade
V2  6
V1 741 AF
3
+ 4 VO 0.707AF
C VEE
VIN R
Stop Band
Pass Band
fL Frequency
Figure 6.08(a): First order high pass filter Figure 6.08(b): Frequency response
Figure 6.08(b) shows a frequency response of first order butterworth high pass filter with a low cutoff frequency of
Comparator
fL. At fL the magnitude of gain is 0.707A F. All frequencies higher than fL are pass band frequencies with the highest
frequency determined by the close loop bandwidth of the op-amp. The gain increases at a rate of 20db/decade.
Output voltage VO is given by expression: VO = [1 + (RF/RIN)] [(j2π.f.R.C .VIN) / (1+j2π.f.R.C)] OR
VO/VIN = AF / (1+j2π.f.R.C) = AF { j(f/fL) / [(1 + j(f/fL)]
where, (VO/VIN ) is the gain of the filter as a function of frequency.
AF = [1 + (RF/RIN)] = pass band gain of the filter, f is the frequency of input signal (Hz).
fL = 1/(2π.R.C) = low cutoff frequency of the filter (Hz).
The gain magnitude equation is obtained by converting equation (VO/VIN ) into its equivalent polar form, as
follows-
𝐕𝐎 𝐀𝐅 (𝐟⁄𝐟𝐋 )
| |=
𝐕𝐈𝐍 √𝟏 + (𝐟⁄𝐟𝐋 )𝟐
Designing and frequency scaling procedure of first order high pass filter is same as of first order low pass filter.
SECOND ORDER HIGH PASS BUTTERWORTH FILTER:

Figure 6.09 (a) and (b) shows the circuit diagram of second order high pass butterworth filter and frequency
response plot. Here two RC networks are used for filtering and op-amp is used in non-inverting mode . Resistance
RIN and RF determine the gain of the filter.
RF
Gain
RIN +VCC
2 7 40dB/decade
V2  6
V1 741 AF
3
+ 4 VO 0.707AF
C1 C2 VEE
VIN R1 R2
Stop Band Pass Band
fL Frequency
Figure 6.09(a): Second order low pass filter Figure 6.09(b): Frequency response
Figure 6.09(b) shows a frequency response of second order butterworth high pass filter with a low cutoff
Comparator
frequency of fL. At fL the magnitude of gain is 0.707AF. All frequencies higher than fL are pass band frequencies with
the highest frequency determined by the close loop bandwidth of the op-amp. The gain increases at a rate of
40db/decade.
AF = [1 + (RF/RIN)] = pass band gain of the filter, f is the frequency of input signal (Hz).
fL = 1/(2π.R.C) = low cutoff frequency of the filter (Hz).
The gain magnitude equation is obtained by converting equation (VO/VIN ) into its equivalent polar form, as
follows-
𝐕𝐎 𝐀𝐅
| |=
𝐕𝐈𝐍 √𝟏 + (𝐟𝐋 ⁄𝐟)𝟒
Where, AF = 1.586 = pass band gain for the second order butterworth response.
Designing and frequency scaling procedure of high pass filter is same as of low pass filter because the circuits of
By -both
Vikas Bhujade
the filters are same except that the position of resistors and capacitors are interchanged.
HIGHER ORDER FILTERS:

Since the gain of filter in the stop band of first and second order filters, changes at a rate of 20 db/decade and 40
db/decade, means that, as the order of filter is increased, the actual stop band response of the filter approaches
its ideal stop band characteristic. Higher order filters, such as third, fourth and so on are formed by using first and
second order filters.
─60dB/decade
Gain
ist order iind order iind order iind order Third order
low pass low pass VO V low pass low pass AF ─80dB/decade
VIN VO
filter filter IN
filter filter 0.707AF
Fourth order
Figure6.10: Third order Filter Figure6.11: Fourth order Filter

Pass Band Stop Band
fH Frequency
Figure 6.12: Frequency response
Figure 6.10 shows the block diagram of third order low pass filter, formed by cascading Comparator first order filter with
second order filter whereas figure 6.11 shows the block diagram of fourth order low pass filter, formed by
cascading two second order filters. Although there is no limit to the order of the filter, as the order increases, size
of filter increases and its accuracy turns down. Also as the order of the filter increases, the difference between the
actual and the theoretical stop band response increases. The overall gain of the higher order filter is equal to the
product of the individual voltage gains of the filter sections. Since the value of resistors and capacitors used in
higher order filter are equal, the high cutoff frequency of higher order filter is given as: fH = 1 / (2π.R.C)
BAND PASS FILTERS:

A filter that passes only a band of frequencies lying in between lower cut off frequency (f L) and upper cutoff
frequency (fH) and block frequencies above fH and below fL is known as band pass filter. There are two types of
band pass filter: wide band pass and narrow band pass.
Wide band pass filter has a figure of merit or quality factor Q <10 whereas, Q>10 for a narrow band pass filter.
Quality factor Q is a measure of selectivity, means that higher the value of Q, the more selective is the filter or
narrower its bandwidth(BW). The relationship between Q, BW and center frequency f C is given as:
Q = (fC / BW)=[ fC/( fH ─ fL ).
For wide band pass filter, fC = √( fH . fL ) where, fH and fL are the high and low cutoff frequencies (Hz).
Important is that upper cutoff frequency fH should always be greater than lower cutoff frequency fL ie. fH > fL
Wide Band Pass Filter:
Wide band pass filter is formed by cascading high pass and low pass filter as shown in figure 6.13(a), and (b) shows
its frequency response. To obtain a ±20db/decade roll off, first order high pass filter is cascaded with first order
low pass filter ie. the order of band pass filter depends on the order of the high and low pass filter.
The voltage gain magnitude of the
RF RF’
band filter is equal to the product
RIN +VCC R IN’ + VCC of the voltage gain magnitudes of
2 7 2 7
V2  6 V2  6 the high pass and low pass.
741 741
V1 R’ V1 Therefore,
+ 4 + 4 VO
3 3 𝐕𝐎 𝐀 𝐅𝐓 (𝐟⁄𝐟𝐋 )
C VEE C’ VEE | |=
VIN R 𝐕𝐈𝐍 √[(𝟏 + (𝐟⁄𝐟𝐋 )𝟐 )][𝟏 + (𝐟⁄𝐟𝐇 )𝟐 ]
Where, AFT = total pass band gain
First order High Pass Filter f = frequency of the input signal (Hz)
First order Low Pass Filter
fL = low cutoff frequency (Hz)
fH = high cutoff frequency (Hz)
Figure 6.13(a): Wide Band Pass Filter
By - Vikas Bhujade
Gain
+20dB/decade ─20dB/decade
AF
0.707AF
Stop Band Pass Band Stop Band

fL fH Frequency
Figure 6.13(b): Frequency Response
Narrow Band Pass Filter: Comparator

Figure 6.13(a) and (b) shows the circuit diagram and frequency response of narrow band pass filter.
C2 Gain
R3
Band Width
R1 C1 +VCC
2 AF
V2  7 6
741
V1 0.707AF
VIN 3
+ 4 VO
R2 VEE Stop Band Pass Band Stop Band
R3
R3 fL fC fH Frequency
Figure 6.14(a): Narrow Band Pass Filter Figure 6.14(b): Frequency Response
Comparator
Narrow band pass filter using multiple feedback as shown hence the name multiple feedback filter. Op-amp used
is in inverting mode. This filter is designed for specific values of center frequency f C and quality factor Q or fC and
bandwidth.
Design of narrow band pass filter:
(i) Choose C1 = C2 = C.
(ii) Determine the value of R1, R2 and R3 by the following expressions:
R1 = Q / (2π.fC.C.AF); R2 = Q / [2π.fC.C.(2Q2─AF]; and R3 = Q / (π.fC.C) where Q is the quality factor, fc is the center
frequency (Hz), AF is the gain at fc , is given by : A F = (R3)/(2R1)
(iii) Important is that, the gain must satisfy the condition: A F < 2Q2
Advantages of narrow band pass filter:
(1) Only single op-amp is used.
(2) Center frequency fC can be changed to new frequency fC’ without changing the gain or bandwidth. This can be
done by changing resistor R2 to R2’ so that R2’ = R2 (fc/fc’)2
BAND REJECT FILTERS :

In band reject filters, band of frequencies from fH to fL is attenuated ie. stop band whereas frequencies are passed
outside this band ie. pass band. Band reject filters are also called as band stop or band elimination filters. This
filters are classified as (i) Wide band reject filter (ii) Narrow band reject filter.
Wide band reject filter:
Figure 6.15(a) and (b) shows the circuit diagram and frequency response of wide band reject filter. This filter has a
high pass filter, a low pass filter and a summing amplifier. Condition to realize the band reject filter response is
that the low cutoff frequency fL, of high pass filter must be larger than the high cutoff frequency fH, of low pass
filter. Also the pass band gain of high and low pass filters must be same. Center frequency fc = √( fH. fL)
By - Vikas Bhujade
RF
Gain
R1 +VCC
2 7
V2  6
741 R4 AF
C V1
+ 4 R2
3 +VCC 0.707AF
VEE A 2 7 Stop Band
R  6 Pass Band Pass Band
741
RF’ R3 B + 4 VO
3 fH fC fL
R1 ’ +VCC VEE Frequency
VIN 2 7
V2  6
741
R’ V1
3
+ 4
C’ VEE
Figure 6.15(a): Wide Band Reject Filter Figure 6.15(b): Frequency Response
From figure 6.15(b), the voltage gain changes at the rate of 20dB/decade above fH and below fL, with a maximum
Comparator
attenuation occurring at fc.
Narrow Band Reject Filter (Notch Filter):
For rejection of only a single frequency, the notch filter is used. Active notch filter commonly uses a twin-T
network and a op-amp as voltage follower. One T network has two resistors and a capacitor while the other uses
two capacitors and a resistor. The quality factor Q of T network is low and can be increased, if it is used with
voltage follower as shown in figure 6.16(a) and figure 6.16(b) shows the frequency response of filter.
R R
+ Gain
C C 741 Bandwidth
VIN ─ VO
A
R/2 2C 0.707AFF
Stop
Pass Pass
fH fN fL Frequency
Figure 6.16(a): Narrow Band Pass Filter Figure 6.16(b): Frequency Response
To design a notchComparator
filter for a desired notch out frequency f N, choose the value Comparator
of capacitor C ≤ 1μF and then
calculate the value of resistor using the expression: R = 1/ (2π.fN.C). Notch filters are used in communications and
biomedical instruments to eliminate undesired frequency.
ALL PASS FILTER:

A filter which passes all frequency components of input signal without attenuation is known as all pass filter. All
pass filters is also called as delay equalizers or phase correctors. Figure 6.17(a) and (b) shows the circuit diagram
and input and output waveforms. In this filter, the pass band covers the entire frequency, hence has a flat
amplitude response characteristics. All pass filter produces an output that is phase shifted relative to the input
signal.
By - Vikas Bhujade
RF =RIN Voltage
Vin
RIN +VCC VO
2 7 1
V2  6
741
R V1
3
+ 4 VO
VIN C VEE t
─1
ᶲ
Figure 6.17(a): All Pass Filter Figure 6.17(b): Input and Output Waveforms
ComparatorIN
The output voltage Vo is given by the expression- Vo = [(1─j2π.f.R.C)/ (1+j2π.f.R.C)].V
Where, f is the input signal frequency (Hz). From the above equation, amplitude of (Vo/V IN) is unity ie. Vo = VIN
throughout the useful frequency range and the phase shift between input and output is a function of input
frequency f. From figure 6.17(b), the output signal lags the input signal by 90° ie. there is a phase shift of 90°
between input and output. The circuit causes a change in phase angle ф from 0° to (─180°) for a frequency
variation from 0 Hz to ∞.
The phase lag introduced by the circuit is given by the expression: ф = [─2.tan─1 (2π.f.R.C)] where ф is in degrees,
f is in hertz, R in ohms and C in farads. If the position of R and C are interchanged, then the output signal leads the
input signal and the phase angle introduced by the circuit is given by: ф = [2.tan─1 {1/(2π.f.R.C)}]
By - Vikas Bhujade
IC-555 TIMER:
Figure 7.01 shows the functional block

Control diagram of IC-555 timer. It consists of a
VCC Discharge Threshold Voltage
7 6 voltage divider network, which provides
8 5
bias voltage of (2/3)Vcc to the inverting
input of the comparator-1 and (1/3)Vcc to
the non-inverting input of the comparator-
Q1 2. These two voltages fix the comparator
5kΩ +
Comparator-1 threshold voltage and also determine the
─ timing interval. Electronically, possible to
(2/3)VCC
R vary time by applying a modulation
5kΩ Q’
(1/3)VCC
F/F voltage to the control voltage input (pin-
+ S 5). If no such modulation is proposed, a
Q2
Comparator-2 0.01μF capacitor is connected between
5kΩ ─
control voltage and ground to bypass noise
Vref
and ripple from supply. The other two
Output Stage inputs to the comparator are threshold
and trigger inputs. The output of these
1 2 3 4 two comparators, SET or RESET the flip
Ground Trigger Output Reset flop, whose Q’output is fed to base of
transistor Q1. When Q’ = high, Q1 is ON
Figure 7.01: Functional block diagram of IC-555 Timer and capacitor (externally connected
between pin 7 and ground) will discharge.
The output stage is basically an inverting buffer stage used to provide a low output resistance and also to invert
the flip flop output. Output stage has a capability of sourcing and sinking 200mA current. Q2 (PNP transistor)
whose emitter is connected to an internal reference voltage which is less than Vcc. When Vref > Vcc (Pin-4 potential
is less than Vcc), Q2 is ON, which causes Q1 to turn ON and output at pin-3 is brought to ground level.
Applications include oscillator, pulse generator, ramp and square wave generator, voltage monitor and may more
applications.
IC-555 AS MONOSTABLE MULTIVIBRATOR:

Figure 7.02 (a) shows the circuit diagram of IC-555 as monostable multivibrator and (b) shows the waveform of
trigger pulse, capacitor voltage and output pulse. Since it has only one stable state (output low), hence name
monostable.
VCC
VCC Trigger
R
8 4 0
7 VCC t
2/3VCC Capacitor
VC 555 3
6 VO
C 0 Voltage (VC)
t
2 tP Output
1 5
C1 Pulse (VO)
0 t
Figure 7.02(a): Waveforms
Figure 7.02(a): Monostable Multivibrator
It is also called as one-shot multivibrator. From the circuit diagram, Pin-8 is connected to Vcc and pin-4 (reset pin)
also connected to Vcc so that reset condition is disabled. The time interval for which the output remains high (tP,
pulse width) is decided by the external RC network. The capacitor C is connected between pin 7 and 1 so that it
charges through the resistance R when the transistor Q 1 is OFF.
By - Vikas Bhujade
Operation: Initially, trigger pulse is high (Vcc), this drives the output of comparator-2 to low condition. As the
capacitor C is in discharged state, pin-6 and 7 are at ground potential. The inputs to the flip flop will be S=R=0,
hence Q’ = high, so, Q1 is ON, and C discharges to 0V ie. Vc = 0V. Since Q’ = 1, output pin-3 = 0 is actually the stable
state of multivibrator.
When the trigger input (negative trigger pulse) goes low (from Vcc to 0), comparator-2 output = high ie. S = 1. The
comparator-1 output continue to be 0 ie. R=0, hence the flip flop is in set condition ie. Q’ = 0, pin-3 = 1(High state).
Since Q’ = 0, transistor Q1 is OFF and the capacitor C starts charging exponentially towards Vcc through the resistor
R. When Vc becomes greater than ((2/3) Vcc), comparator-1 output changes form low to high ie. R = 1. Since the
trigger input has returned back to Vcc from 0, comparator-2 output is equal to zero ie. S =0. So, S = 0 and R= 1, RS
flip flop get RESET and Q’ = 1. AS Q’ = 1, transistor Q 1 = ON and capacitor C starts discharging towards zero through
the transistor Q1 and capacitor voltage Vc becomes zero. While discharging, when Vc < ((2/3) Vcc), the
comparator-1 output goes to zero ie. R=0. Since the trigger input = Vcc, the comparator-2 output will be = 0 ie.
S=0. Hence, S=0 and R=0, so no change in the Q’ output condition and hence continuous to be High. Thus, pin-3
output = LOW (0-state).
The monostable multivibrator, thus goes from stable state into quasistable state and then returns back to the
stable state after a time, tP = (1.1)R.C
The output remains to be in LOW state until the next trigger pulse is applied to change the state.
IC-555 AS ASTABLE MULTIVIBRATOR:

Figure 7.03 (a) shows the circuit diagram of IC-555 as astable multivibrator and (b) shows the waveform of
capacitor voltage and output pulse. Since no stable state, hence name astable.
VCC
RA VCC Output
8 4
Voltage
7 TON TOFF
RB 0
Pulse
555 3 T t
6 VO (VO)
VCC
2/3VCC Capacitor
C 2 1 5 1/3VCC Voltage
0
C1 t Voltage
(VC)
Figure 7.03(a): Waveforms
Figure 7.03(a): Astable Multivibrator
Astable multivibrator does not requires an external trigger pluse to change the output state, hence called as free-
running multivibrator. The time duration for which the output will remain high or low is decided by the externally
connected two resistors (RA and RB) and a capacitor (C).
Operation: Initially, when output is high (pin-3 = High), Flip flop output Q’ = 0, hence transistor Q 1 is OFF. Now the
capacitor C starts charging towards Vcc through RA and RB. As soon as the voltage across the capacitor Vc,
becomes equal to[ (2/3)Vcc], the comparator-1 output is high and will RESET the flip flop ie. Q’ = 1. Hence the
output = 0. As, Q’ =1 , transistor Q 1 = ON and the capacitor C starts discharging through resistor R B and transistor
Q1. During discharging mode of capacitor C, as soon as the voltage across the capacitor C becomes equal to
[(1/3)Vcc], comparator-2 output will SET the flip flop, Q’ = 0, and output = high. Then the cycle repeats.
Charging time duration of the capacitor C, is equal to the time the output is high is given by the expression:
tC = TON = 0.69(RA + RB )C
Discharging time duration of the capacitor C, is equal to the time the output is low is given by the expression:
td = TOFF = 0.69(RB )C
Hence the total time period of output waveform: T = tC + td = TON + TOFF = 0.69(RA + 2RB )C
𝟏.𝟒𝟓
Hence, the frequency of oscillation is, fO = 1/T = (𝐑
𝐀 +𝟐𝐑 𝐁 )𝐂
From the equation of frequency of oscillation fo, frequency is independent of the supply voltage Vcc.
Duty Cycle: Duty cycle is the ratio of the time during which the output is high (TON) to the total time period T.
By - Vikas Bhujade
𝐑 +𝐑
% duty cycle = [T ON / T] x 100 = 𝐑 𝐀+𝟐𝐑𝐁 × 𝟏𝟎𝟎
𝐀 𝐁
Applications: Astable multivibrator can be used to produce a square wave output. It can be used as a free running
ramp generator.
OP-AMP AS SCHMITT TRIGGER:

Figure 7.05(a) shows the circuit diagram and 7.05(b) input and output waveforms of op-amp as Schmitt trigger.
This circuit converts an irregular-shaped waveform to a square wave output.
+VUT
+VCC INPUT (VIN)
─ 0
741 t
+ VO −VLT
ROM=R1||R2 ─VEE
VIN <VUT
+ +VSAT
R2 OUTPUT (Vo)
VIN R1
0
─ t
─VSAT
Figure 7.05(a): Op-Amp as Schmitt Trigger VIN >VLT

Figure 7.05(b): Waveforms
Comparator
Circuit diagram shows an inverting comparator with positive feedback as a Schmitt trigger. Upper threshold
voltage (VUT) and lower threshold voltage (VLT) are obtained by using voltage divider network R1 and R2. The
voltage drop across R1 is fed back to the non-inverting input. This voltage drop across R1 is the VUT and VLT
threshold voltages that depend on the value and polarity of output voltage Vo. The output voltage Vo, switches
between positive saturation voltage (+VSAT) and negative saturation voltage (−VSAT), each time the input voltage
exceeds the threshold voltage levels, VUT and VLT, as shown in figure 7.05(b). ROM is the offset minimizing
resistance, used to minimize offset problems.
As long as VIN < VUT, the output voltage Vo = +VSAT. When VIN > VLT, the output voltage Vo = −VSAT. Using the
voltage divider rule, the values of VUT and VLT can be obtained as:
𝐑𝟏 𝐑𝟏
𝐕𝐔𝐓 = [+𝐕𝐒𝐀𝐓 ] 𝑎𝑛𝑑 𝐕𝐋𝐓 = [−𝐕𝐒𝐀𝐓 ]
𝐑𝟏 + 𝐑𝟐 𝐑𝟏 + 𝐑𝟐
To remove the false output transitions, the threshold voltages (VUT and VLT) are made slightly larger than the input
noise voltages. Also, the positive feedback, because of its regenerative action, switching of output voltage Vo,
between positive saturation voltage (+VSAT) and negative saturation voltage (−VSAT) will be fast.
This inverting comparator with positive feedback exhibits hysterisis, a dead band condition ie. the output switches
from +VSAT to −VSAT , when the VIN > VUT and output comes back to its original state ie. +VSAT when the VIN < VLT.
COMPARATOR CHARACTERISTICS:
(1)Speed of operation: As the comparator switches rapidly between +VSAT to −VSAT, implies that the bandwidth is
wider and hence the higher is the speed of operation.
(2)Accuracy: Comparator accuracy depends on its voltage gain, CMRR, input offsets, and thermal drifts.
(3)Compatibility of output: Comparator is aform of ADC converter, whose output swings between two logic levels
suitable for logic family (TTL logic family)
LIMITATIONS OF OP-AMP AS COMPARATORS:
Generally, output of a comparator is not well matched with a particular logic family (TTL logic family). This is the
limitation of comparator. Hence to matched the output, op-amps are used with external components such as
zeners or diodes. Hence, the resulting circuits, in which the outputs are limited to predetermined values, are called
limiters.
By - Vikas Bhujade
OP-AMP AS VOLTAGE LIMITERS:

Figure 7.06 (a) to (f) shows the circuit diagram and input/output waveforms of voltage limiters.
D1 D2 VP
+ − + − INPUT (VIN)
R 2
+VCC 0
7 t
V2  6
741
VIN + −VP
V1 3
+ 4 VO
VEE (VZ + VD2) OUTPUT(Vo)
ROM =R 0
t
−(VZ + VD1)
Figure 7.06(a): Op-amp as Comparator with Figure 7.06(b): Input and output Waveforms
positive and negative voltage limiting
Figure 7.06 (a) shows the circuit diagram of comparator with positive and negative voltage limiting circuit and (b)
shows the input and output waveforms. From figure, Point V1 and V2 are at virtual ground, so input voltage VIN,
appears across input resistor R, and output voltage Vo, across zener diodes D1 and D2, which are connected in the
feedback path. Resistance ROM, is used to minimize the offset problems.
This arrangement limits the output voltage. When the input voltage VIN, crosses zero and increases in positive
direction, as shown in figure 7.06(b), diode D 1 is forward biased and diode D2 goes into avalanche conduction, the
output voltage (Vo) increases in negative direction. Therefore, the maximum negative value of output voltage Vo,
is equal to –(VZ + VD1) where VZ is the zener voltage and VD1 is the voltage drop across the forward biased zener
diode D1 ( = 0.7V). On the other hand, when input crosses zero and increases in the negative direction, output
voltage Vo, starts increasing positively until diode D2 is forward biased and D1 goes into avalanche conduction.
Thus the maximum positive voltage is equal to +(VZ + VD2), where VD2 is the voltage drop across the forward biased
zener diode D2 ( = 0.7V). Thus the output voltage Vo swing is limited to +(VZ + VD2) and –(VZ + VD1).
If there is a need of output voltage to limit the swing in positive direction only, then the circuit diagram in figure
7.06(c) is used. Figure 7.06(d) shows the input and output waveforms of figure 7.06(c).
D1 D2 VP
+ − + − INPUT (VIN)
R 2
+VCC 0
7 t
V2  6
741
VIN + −VP
V1 3
+ 4 VO
VEE
(VZ + VD2) OUTPUT(Vo)
ROM =R 0 t
−( VSAT)
Figure 7.06(c): Op-amp as Comparator with Figure 7.06(d): Input and output Waveforms
positive voltage limiting
If only one zener diode is used in feedback path, as shown in figure 7.06(e), the output voltage is limited to +V Z
and −VD, as shown in figure 7.06(f). If the direction of diode D in the feedback path is changed in figure 7.06(e),
then exact opposite result can be obtained ie. output voltage Vo, is limited to −V Z and +VD, where VZ is the zener
voltage and VD is the voltage drop across the forward biased zener diode.
By - Vikas Bhujade
D VP
+ −
INPUT (VIN)
R 2
+VCC 0
V2  7 6 t
741
VIN + −VP
V1 3
+ 4 VO
VEE VZ
OUTPUT(Vo)
ROM =R 0
−( VD) t
Figure 7.06(e): Op-amp as Comparator with Figure 7.06(f): Input and output Waveforms
positive and negative voltage limiting
Voltage limiters are commonly used in communication devices such as Television and frequency modulation
receivers.
OP-AMP AS CLIPPERS AND CLAMPERS:

CLIPPERS:
The circuits which are used to clip off the unwanted portions of the input voltage above or below certain levels to
produce output are called as clipping circuits.
POSITIVE CLIPPER CIRCUIT:
Figure 7.07(a) shows the circuit diagram of positive clipper using op-amp with a rectifier diode and figure 7.07(b)
shows the input and output waveforms.
VP
2 VEE +V REF INPUT (VIN)
V2  4 6 D 0
741 t
+ VO' VO
V1 3 7 −VP
R
+ RP
VIN +VCC +V REF OUTPUT(Vo)
+VREF 0 t
−( VP)
Figure 7.07(a): Positive Clipper Circuit Figure 7.07(b): Input and output Waveforms
Here the op-amp is basically used as a voltage follower with a diode D in the feedback path. Clipping level is
determined by reference voltage +V REF. The +VREF should always be less than the input voltage range of op-amp.
Resistance RP is used as a potentiometer (variable resistor) to vary the reference voltage. Diode D is assumed as an
ideal diode.
Operation: During positive half cycle of input voltage, when VIN ≤ VREF, the VREF voltage at inverting input terminal
is higher than the input voltage VIN applied at the non-inverting terminal of op-amp. Hence, op-amp output VO’(pin
6), is sufficiently negative to turn ON diode D, so, the output Vo, follows the input VIN, because the op-amp is used
as a voltage follower. when VIN > VREF, the VREF voltage at inverting input terminal is lower than the input voltage
VIN applied at the non-inverting terminal of op-amp. Hence, op-amp output VO’(pin 6), is sufficiently positive to
turn OFF diode D, the op-amp operates open-loop; therefore it further drives its output voltage VO’(pin 6) towards
positive saturation (+VCC). Thus, when VIN > VREF, VO’ = +Vcc and Vo = +VREF.
During negative half cycle, VIN ≤ VREF, the output of op-amp VO’(pin 6), is sufficiently negative to turn ON diode D,
so, the output Vo, follows the input VIN. Thus from the output waveform, it is seen that the output portion of the
positive half cycle above reference voltage is clipped off, hence it is called as positive clipper circuit.
The op-amp alternates between closed loop and open loop as the diode D is ON and OFF respectively, so the op-
amp must be a high speed and preferably compensated for unity gain. HA2500, LM310 and µA318 are examples of
high speed op-amps.
By - Vikas Bhujade
NEGATIVE CLIPPER CIRCUIT:

If POT RP of figure 7.07(a) is connected to negative power supply –VEE, then the reference voltage VREF becomes
negative. This will cause the entire output waveform, above −VREF, to be clipped off. The output follows the input
only when Vin < −VREF. By changing the position of diode D and the polarity of reference voltage V REF, the positive
clipper can be converted into negative clipper.
SMALL SIGNAL HALF-WAVE RECTIFIERS (POSITIVE):

Figure 7.08(a) shows the circuit diagram of a positive small signal half wave rectifier with zero reference voltage
and figure 7.08(a) shows the input and output waveforms.
+VREF = 0V VP
VEE INPUT (VIN)
2 4
V2  6
D 0
310 t
+ VO
V1 3 7 VO' −VP
RL
+ VP
VIN +VCC OUTPUT(Vo)
0
t
Figure 7.08(a): Positive Small Signal Half
Wave Rectifier Figure 7.08(b): Input and output Waveforms
This circuit can rectify the signal of peak values of few millivolts. This is possible because the high open loop gain of
op-amp automatically adjusts the voltage drive to the diode D so that rectified output peak is the same as the
input. Diode D acts as an ideal diode.
Operation: When input voltage VIN increases in positive direction, output of op-amp VO’, also increases in positive
direction and diode D is forward biased and act as closed switch, and closes a feedback loop. Hence the op-amp
act as a voltage follower, and output voltage Vo, is same as input voltage, as shown in figure 7.08(b).
When input voltage VIN increases in negative direction, output of op-amp VO’, also increases in negative direction
and diode D is reverse biased and act as an open switch, and opens a feedback loop. Hence output voltage Vo, is
zero volt, and output does not follow the input as shown in figure 7.08(b).
Here the op-amp should be high speed op-amp, since it alternates between closed and open loop operations.
Examples of high speed op-amps are HA2500, LM310 and µA318.
SMALL SIGNAL HALF-WAVE RECTIFIERS (NEGATIVE):

This small signal positive half wave rectifier can be converted into negative small-signal half wave rectifier by
reversing diode D.
NEGATIVE HALF-WAVE RECTIFIER:

Figure 7.09(a) shows the circuit diagram of a negative half wave rectifier with zero reference voltage and figure
7.09(a) shows the input and output waveforms.
R1 RF = R1 VP
+ VO
VEE INPUT (VIN)
VIN + 2 4 D1
 6  0
310 VO’ t
3
+ 7 + −VP
+VCC D2
ROM  D2
D1
OUTPUT(Vo)
+VREF = 0V 0 ON ON
t
ON ON
−VP
Figure 7.09(a): Negative Half Wave Rectifier
Figure 7.09(b): Input and output Waveforms
By - Vikas Bhujade
In this circuit, op-amp is used in inverting configuration. The two diodes D1 and D2 are used in such a way that the
output Vo’ does not saturate which in turn minimizes the response time increases the operating frequency of op-
amp. The output voltage Vo is measured at the anode of D1.
Operation: During positive half cycle of input voltage VIN, output Vo’ is negative, hence diode D1 is forward biased
and closes the feedback loop through RF. Since R1 = RF, Vo = VIN. During negative half cycle of input voltage VIN,
output Vo’ is positive, hence diode D2 is forward biased and prevents the op-amp from going into positive
saturation. Since diode D1 is OFF, Vo = 0V.
In order to obtained positive half-wave rectified outputs, diodes D1 and D2 must be reverse biased.
POSITIVE AND NEGATIVE CLAMPERS:

The circuit in which the output signal is clamped to a predetermined DC level (Positive or Negative), without
changing the shape and amplitude of the input signal is called clamper. Clamper is also called as DC inserter or
restorer. Condition to keep the output waveform undistorted is that the (RC) time constant should be very large
compared to the time period of the input waveform.
Figure 7.10(a) shows the circuit diagram of peak clamper and figure 7.10(b) shows the input and output
waveforms with +VREF.
Ci
IC VP
− + VO
VP − INPUT (VIN)
− R −VEE D
VIN 2 4
0
 + t
+ 741
6
−VP
+ 7 VO’
3
+VCC
RP 2VP
VREF OUTPUT (Vo)
+VREF
0 t
Figure 7.10(b): Input and output Waveforms
Figure 7.10(a): Op-amp as peak clamper
with +VREF
Figure 7.10(c) shows the input and output waveforms with −VREF.
Figure 7.10(a) consists of a variable positive DC level.
Output Vo, is the net result of AC and DC, applied to VP
inverting terminal and non-inverting terminal of op- INPUT (VIN)
amp. 0
t
Circuit Operation: Diode D is assumed as an ideal diode.
To understand the operation, we will consider each −V P
input separately. Considering VREF input first, connected 0

to non-inverting terminal of op-amp. Since reference −VREF t
voltage VREF is positive, output at pin 6 (Vo’) is also OUTPUT (Vo)
positive, which forward bias the diode D. Thus diode act −2VP
as a closed switch, and closes the feedback loop and op-
amp operates as a voltage follower. This is possible
because capacitor Ci is an open circuit for DC voltage.
Therefore, Vo = +VREF. Figure 7.10(C): Input and output Waveforms
Now considering AC input voltage VIN, which is with −VREF
connected to inverting terminal of op-amp.
During negative half cycle of input voltage V IN, diode D conducts and capacitor starts charging to the negative peak
value of VP. During positive half cycle, diode D is reverse biased, hence V P across capacitor will remain same. Since
the positive half cycle VP, is in series with the capacitor voltage V P, hence the output voltage VO = 2VP. Thus the net
output is VREF plus 2VP, so the negative peak of 2VP is at VREF as shown in figure 7.10(b). For precision clamping,
Ci.Rd << T/2 where Rd is the resistance of diode D when forward biased (100Ω typically) and T = time period of the
By - Vikas Bhujade
input waveform. Resistor R is used to protect the op-amp from excessive discharge current from capacitor Ci,
when DC supply voltages are switched OFF. A positive peak clamped to negative reference level clamper circuit is
made by reversing the diode D and using negative reference voltage. Its input and output waveform is shown in
figure 7.10(c).
Clipping and clamping are used in wave shaping circuits. These circuits are used in digital computers and
communications such as TV and FM receivers.
ABSOLUTE VALUE OUTPUT CIRCUIT:

Figure 7.11 (a) shows the circuit diagram of absolute value output circuit, figure 7.11 (b) shows the circuit diagram
of absolute value output circuit during positive half cycle, figure 7.11 (c) shows the circuit diagram of absolute
value output circuit during negative half cycle, and figure 7.11 (d) shows the input and output waveforms.
I2
D3 D3
R R − R+ − R+ − +
I2
R +VCC +VCC
2 7 2 7
D1 V2  6 V2  6
R 741 741
V1 + R − V1
+ 4 VO + 4 VO (+)
+ D2 3
VEE + + D2− I1 +
3
VEE
VIN R R
+V −
− − P
Figure 7.11(a): Absolute value output circuit Figure 7.11(b): Absolute value output circuit
during positive half cycle
I1
+ R − D3 D3
− R+ − + − R+ − +
IB2
− R+ + VCC RTH=R/2 + VCC
2 7 2 7
− D1 + V2  6 + V2  6
741 − I2 741
V1 − V1
3
+ 4 VO (−) 3
+ 4 VO (−)
− VEE IB1 VEE
−VP R + R
+ VTH=−(VP−VD1)/2
Figure 7.11(c): Absolute value output circuit
Figure 7.11(c): Thevenin’s Equivalent
during negative half cycle
Circuit Operation: During positive half cycle of input

+VP voltage (VP), diode D2 is forward biased and D1 is reverse
INPUT (VIN) biased. Hence the Diode D2 is connected in the circuit as
0 shown in figure 7.11 (b). Thus the voltage at node V1 (+
t
input of op-amp) is:
−VP 𝐕𝐏 − 𝐕𝐃𝟐
𝐕𝟏 =
+VP 𝟐
OUTPUT (VO) Where, VD2 is the voltage drop across diode D2 = 0.7V
0 Similarly, the voltage at node V2 (− input of op-amp) is:
t 𝐕𝐎(+) − 𝐕𝐃𝟑
𝐕𝟐 =
𝟐
Where, VO(+) is the output voltage during positive half
Figure 7.11(d): Input and output Waveforms cycle and VD3 is the voltage drop across diode D3 = 0.7V
Since, difference input voltage, Vid ≈ 0V, so V1 = V2.
Therefore,
𝐕𝐏 − 𝐕𝐃𝟐 𝐕𝐎(+) − 𝐕𝐃𝟑
=
𝟐 𝟐
By - Vikas Bhujade
Hence, we get the output voltage, VO(+) = VP (ie. the output voltage is equal to the peak of positive half cycle of
the input as shown in figure 7.11(d)).
During negative half cycle of input voltage (−VP), diode D1 is forward biased and D2 is reverse biased. Hence the
Diode D1 is connected in the circuit as shown in figure 7.11 (c). This circuit is further simplified by applying
thevenin’s theorem to the left of the (−) input of op-amp. Hence, its Thevenin’s equivalent voltage and resistance
are:
𝐕𝐏 − 𝐕𝐃𝟏 𝐑
𝐕𝐓𝐇 = − ( ) 𝐚𝐧𝐝 𝐑 𝐓𝐇 ≅
𝟐 𝟐
Where, VD1 is the voltage drop across diode D1 , V TH and RTH are Thevenin’s equivalent voltage and resistance.
Now, applying Kirchoff’s current law at node V2, we get:
I1 = I2 + IB2; Since, IB2 ≈ 0A; Hence, I1 = I2
Where, I1 and I2 are the currents flowing through resistor R and RTH and IB2 is the bias current that flows into the
inverting terminal of op-amp as shown in the figure 7.11(c).
Since,
[𝐕𝐎 (−) − 𝐕𝐃𝟑 ] − 𝐕𝟐 𝐕𝟐 − (𝐕𝐓𝐇 )
𝐈𝟏 = 𝐚𝐧𝐝 𝐈𝟐 =
𝐑 𝐑⁄𝟐
Hence, on equating currents, I1 and I2, we get,
[𝐕𝐎 (−) − 𝐕𝐃𝟑 ] − 𝐕𝟐 𝐕𝟐 − (𝐕𝐓𝐇 )
=
𝐑 𝐑⁄𝟐
Since, Voltage at Node V1 = 0V, so, V2 is also zero, due to virtual ground concept. Therefore, substituting the node
voltage V2 = 0V and also VTH in the above equation, we get:
VO (−) – VD3 = VP – VD1
Hence, the output voltage, VO (−) = VP, where, VD1 = VD3 = 0.7V (ie. the output voltage is equal to the peak of
negative half cycle of the input as shown in figure 7.11(d)).
Hence, from the output equations of VO (−) and VO (+), it is concluded that the regardless of the polarity of the
input signal, the output is always positive going; hence the name given absolute value output circuit.
Note that the gain of the circuit is 1, therefore the positive peak amplitudes are the same as the input peak
amplitudes. Diode D3 compensates for the voltage drop across diodes D1 or D2.
This circuit is used in wave shaping circuits.
PEAK DETECTOR:
Peak detector is a circuit which is used to measure the peak value of any non sinusoidal waveforms. Figure 7.12(a)
shows the circuit diagram of peak detector (positive) and 7.12(b) shows the input and output waveforms.
+VP Input Voltage VIN

R 2 VEE
 4 6 D1 IB 0
t
ROM=R 741
+ − −VP
3
+ 7 + VO T
+ C RL
+ D2 − +VP Output
VIN +VCC − IC
Voltage
Voltage
0 t )
(V C
Figure 7.12(a): Peak Detector Circuit Figure 7.12(b): Input and Output Waveforms
Operation: During the application positive half cycle of input voltage VIN, diode D1 is forward biased and D2 is
reverse biased. Due to diode D1 forward biased, the op-amp operates as a voltage follower. As diode D1 is
forward biased, capacitor C starts charging towards positive peak +V P of input voltage as the polarity shown in
figure 7.12(a).
During the application of negative half cycle, diode D1 is reverse biased, and voltage across capacitor C remains
unchanged. The only discharge path for C is through load resistor RL. For proper operation of the circuit the
charging time constant (C.Rd) and discharging time constant (C.RL) must satisfy the following conditions:
By - Vikas Bhujade
(i)(C. Rd) ≤ (T/10); where Rd is the resistance of forward biased diode (100Ω typically) and T is the time period of
input waveform.
(ii) (C.RL) ≥ (10T); where RL is the load resistor.
A high speed, precision type op-amp such as µA741 is used. The resistor R is used to protect the op-amp against
the excessive discharge currents, especially when the power supply is switched off. The resistor R OM = R minimizes
the offsets problems. Diode D2 conducts during negative half cycle of V IN voltage to prevent the op-amp from
going into negative saturation, which in turn reduces the reverse recovery time of op-amp.
Negative peak detector can be detected by reversing diodes D1 and D2 of figure 7.12(a)
SAMPLE AND HOLD CIRCUIT:

Figure 7.13(a) shows the circuit diagram of sample and hold circuit and figure 7.13 (b) shows the input and output
waveforms.
VP
N-Channel VEE
2
E-MOSFET  4 6
741 INPUT (VIN)
D S VC R + 7 VO
3
RL
+ C 0
+VCC t
VIN
G VS
+VP Control Voltage (VS)
VS TS= Sample Time
TH= Hold Time
0
t
VIN : Input signal to be sampled TS TH
VS : Sample and Hold Control Voltage VO = VP
VC : Voltage across capacitor Output
G : Gate; D : Drain and S : Source Voltage (VO)
Voltage (VC)
0 t
Figure 7.13(a): Sample and Hold Circuit Figure 7.13(b): Input and output Waveforms
Sample and hold circuit is the circuit which samples the applied input signal and holds on to its last sampled value
until the input is sampled again. From the circuit, enhancement MOSFET (E-MOSFET) works as a switch ie. when
gate (G) terminal is positive E-MOSFET conducts (ON) and when zero, E-MOSFET is OFF. This ON and OFF of E-
MOSFET is controlled by sample and hold control voltage (VS). The analog input signal (VIN) to be sampled is
connected to drain (D) terminal and source (S) terminal is connected to capacitor C, where capacitor C, acts as a
storage element. Here op-amp acts as a voltage follower.
Operation: When control voltage VS, is positive, E-MOSFET is ON, and capacitor starts charging towards input
voltage VIN. This input voltage VIN, appears across capacitor C and in turn at the output of op-amp VO, as shown in
figure 7.13(b). This is the sample period time.
When control voltage VS, is zero, E-MOSFET is OFF, and act as a open switch. The only discharge path for capacitor
C is through op-amp. However the input resistance of op-amp as voltage follower is very high; hence the voltage
across capacitor VC, is retained. This is the hold period time. The output of op-amp is observed during hold
periods.
Note that, for obtaining the close approximation of the input waveform, the frequency of control voltage V S must
be higher than that of the input signal VIN. Also precise and high speed op-amp is used. Choose a low-leakage
capacitor such as Teflon or polyethylene.
Sample Periods: The time periods TS of the control voltage VS, during which the voltage across the capacitor is
equal to the input voltage VIN are called sample periods.
Hold Periods: The time periods TH of the control voltage VS, during which the voltage across the capacitor is
constant are called sample periods.
By - Vikas Bhujade
The sample and hold circuit is commonly used in digital interfacing and communications such as analog-to-digital
and pulse modulation systems.
VOLTAGE TO CURRENT CONVERTER WITH GROUNDED LOAD:

Figure 7.14 shows the circuit diagram of an op-amp voltage to current converter operating with a grounded load.
The input voltage source is connected to the non-inverting
terminal of the op-amp; hence it does not get loaded due to
R R the very high input resistance of the circuit. The circuit is
+VCC capable of converting an input voltage into its equivalent
2 7
V2  6 load current that flows through a load in which one end is
R 741
+ − V1 grounded as shown in figure. It can be shown
3
+ 4 VO =2.V1
+ I1 VEE
mathematically that the load current IL is directly
VIN − R proportional to the input voltage VIN. The circuit analysis is
+ − I2 + carried out by determining the voltage V1 that appears at
LOAD the non-inverting input (pin-3). We then establish a
− IL relationship V1 and load current IL.
Applying Kirchhoff’s current equation at node V1,
I1 + I2 = IL ………………………………………..(6.1)
Figure 7.14: Voltage to current converter with 𝐕 −𝐕 𝐕 −𝐕
Since, 𝐈𝟏 = 𝐈𝐍 𝐑 𝟏 𝐚𝐧𝐝 𝐈𝟐 = 𝐎 𝐑 𝟏
grounded load
Substituting, I1 and I2 in equation no. 6.1, we get,

𝐕𝐈𝐍−𝐕𝟏 𝐕 −𝐕 𝐕 +𝐕 −𝐑.𝐈
+ 𝐎 𝐑 𝟏 = 𝐈𝐋 ; On solving, we get, 𝐕𝟏 = 𝐈𝐍 𝟐𝐎 𝐋 … … … … … … … … … … … … … … (𝟔. 𝟐)
𝐑
Since the gain of the circuit connected in non-inverting amplifier is given as (1+R/R) = 2. Hence the output voltage
VO = 2.V1 ............................................................................(6.3)
On substituting equation 6.2 in equation 6.3, we get,
VO = VIN + VO – R.IL ; OR VIN = R.IL ; OR IL = VIN / R .....................................(6.4)
ie. IL α VIN ; this relationship shows that the load current IL is directly proportional to the input voltage VIN.
The load current IL depends on the input voltage VIN and the resistance R. In this circuit it is very important that all
resistors must have equal values for satisfactory operation.
Voltage to current converter circuits is used to test Zener diodes and LEDs. They are also used for low voltage
Voltmeters. The load size ≤ R value will give satisfactorily performance of the circuit.
VOLTAGE TO CURRENT CONVERTER WITH FLOATING LOAD:

Figure 7.15 shows the circuit diagram of an op-amp voltage to current converter operating with a floating load ie.
the load terminals are not connected to ground.
The input voltage source is connected to the non-inverting
IO RL terminal of the op-amp; hence it does not get loaded due to
− R IN
+ +VCC the very high input resistance of the circuit. The voltage drop
2 7
VA  6 across resistance RIN is equal to (IO.RIN) where IO is the output
IO 741
+ 4 current. (VA) is the input at the inverting input terminal. The
3 circuit is capable of converting an input voltage into its
VEE
+ equivalent load current that flows through the floating load
VIN
as shown in figure 7.15. This circuit is also called as current
−
series negative feedback amplifier because the feedback
voltage across resistor RIN depends upon output current IO
Figure 7.15: Voltage to current converter with
and is in series with input difference voltage Vid.
floating load
Applying Kirchhoff’s voltage law to the input circuit, we get, VIN = VA

But VA = (IO . RIN) ; but VA = VIN ; therefore VIN = (IO . RIN); or IO = [VIN / RIN] ie. IO α VIN. The relationship of the
output current IO and the input voltage VIN clearly shows that the output current IO is directly proportional to the
input voltage VIN. For satisfactory operation of the circuit, the resistor RIN must be a precision resistor. Voltage to
By - Vikas Bhujade
current converters with floating loads is used for testing Zener diodes, LEDs, for matching diodes and also in low
range (AC and DC) voltmeters.
CURRENT TO VOLTAGE CONVERTER:

Figure 7.16 shows the circuit diagram of current to voltage converter in which the input current is directly
proportional to output voltage. Basically the circuit is an op-amp inverting amplifier.
Input voltage source VIN in series with input resistor RIN is connected
IO RF to inverting terminal of op-amp. This series combination will form a
constant current source of magnitude IIN.
RIN +VCC
2 7 The voltage gain of inverting amplifier is given by:
V2  6 −𝐑 −𝐕
VIN IIN 741 (VO / VIN) = −(RF / RIN) ; ie. 𝐕𝐎 = 𝐑 𝐅 . 𝐕𝐈𝐍 𝐎𝐫 𝐕𝐎 = 𝐑 𝐈𝐍 . 𝐑 𝐅
+ + 4 VO 𝐈𝐍 𝐈𝐍
V1 3 Since, IIN = (VIN / RIN).
−  VEE
Hence, VO = −[(IIN).RF] ie. VO α (IIN).
From the above relationship it is clear that the output voltage VO is
directly proportional to the input current IIN which means that the
circuit is capable of converting an input current into a proportional
Figure 7.16: Current to voltage
output voltage. The lower limit on current measurement is set by the
converter
bias current IB of an op-amp, this means that op-amps with smaller IB
values such as μA714 which has an IB = 3 nA can be used to detect
lower currents.
Current to voltage converters are used to sense currents from photo
detectors and are also used in digital to analog converters.
PRECISION FULL WAVE RECTIFIER : [ABSOLUTE VALUE OUTPUT CIRCUIT]

Refer to figure 7.11 for circuit diagram and operation.
PRECISION HALF WAVE RECTIFIER : [SMALL SIGNAL HALF-WAVE RECTIFIERS]

Refer to figure 7.08 for circuit diagram and operation.
By - Vikas Bhujade
VOLTAGE REGULATORS: A voltage regulator is a circuit that provides a constant voltage regardless of any changes
in the load currents. Performance parameters of voltage regulators are:
Line regulation or input regulation: The change in output voltage for a change in input voltage. Expressed in
millivolts.
Load regulation: The change in output voltage for a change in load current. Expressed in millivolts.
Temperature stability or average temperature coefficient of output voltage: The change in output voltage per
unit change in temperature. Expressed in either millivolts/°C or parts per million (ppm)/°C.
Ripple rejection: It is the measure of the regulator’s ability to reject ripple voltages. Expressed in decibels.
The smaller the values of line regulation, load regulation, and temperature stability, the better the regulator.
IC voltage regulators are multipurpose and have features as programmable output, current/voltage boosting,
internal short-circuit current limiting, thermal shutdown and floating operations for high-voltage applications.
Types of IC voltage regulators are:
(1)Fixed output voltage regulators: Positive and negative output voltage
(2)Adjustable output voltage regulators: Positive or negative output voltage
(3)Switching regulators
(4)Special regulators
SERIES VOLTAGE REGULATOR USING OP-AMP:

Figure 8.01 shows the circuit diagram of series voltage regulator using op-amp.
The op-amp is used as a comparator. It
+ T + compares the part of the output voltage Vo
VIN R3 VO obtained from potential divider circuit as a
− 2
+VCC R1 − feedback with the reference voltage
V(+) + 7
6 generated by the zener diode Vz.
741
V(−) The output of the op-amp drives the series
3  4 R
VEE L pass transistor T.
If there is any change in output voltage the
+ control signal from op-amp control the
VZ R2 conduction of the transistor T. Thus the
− output voltage is maintained at a constant
level.
Figure 8.01: Series voltage regulator using op-amp
From virtual ground concept

V (−) = V(+)
V (−) = V(+)= [Vo/(R1+R2 )] R2
The voltage at non-inverting terminal V+ is nothing but the zener voltage Vz as shown in figure 8.01.
V(+) = Vz
The output voltage can be expressed as: Vo = [(R1+R2)/R2 ] V(+); Vo=[(R1+R2)/R2 ] Vz
Hence, Vo=[1+R1/R2 ] Vz
FIXED VOLTAGE REGULATORS:

Positive fixed voltage regulator: 78XX series is a positive voltage regulator ICs. It is 3-terminal IC. First terminal is
input , second terminal is ground and third terminal is output, as shown in figure 8.02.
These ICs are fixed voltage regulators and can deliver output
Vin 1 3 VOUT current of 1Amp. These ICs has internal thermal over load
78XX protection and short-circuit protection. Capacitor Ci, is required
Ci Co if the regulator is located at considerable distance from a
2
power supply filter. Capacitor Co, is used to improve the
transient response of the regulator. Ground pin no.2, should be
common for both input and output pins, for proper operation.
Figure 8.02: Positive voltage regulator IC The dropout voltage, (Vin − VOUT), must be typically 2.0V even
during the low point on the input ripple voltage.
By - Vikas Bhujade
Table 1.1 shows the 7800 series voltage regulators with seven voltage options:
Device type Output Voltage (Vo) Maximum Input Voltage (Vin)
7805 5.0 35
7806 6.0 35
7808 8.0 35
7812 12.0 35
7815 15.0 35
7818 18.0 35
7824 24.0 40
TABLE 1.1
Negative fixed voltage regulator: 79XX series is a negative voltage regulator ICs. It is 3-terminal IC as ground, input
and output.
Table 1.2 shows the 7800 series voltage regulators with seven voltage options:
Device type Output Voltage (Vo) Maximum Input Voltage (Vin)
7902 −2.0 −35
7905 −5.0 −35
7905.2 −5.2 −35
7906 −6.0 −35
7908 −8.0 −35
7912 −12.0 −35
7915 −15.0 −35
7918 −18.0 −35
7924 −24.0 −40
TABLE 1.2
ADJUSTABLE VOLTAGE REGULATORS:
A single IC which satisfies the voltage requirement from 1.2V to 57 V, is adjustable voltage regulator. LM317 series
is the most commonly used adjustable voltage regulators.
Advantages of adjustable over fixed voltage regulators:
1) Improved system performance by having line and load regulation of a factor of 10 or better.
2) Improved overload protection allows greater output current over operating temperature range.
3) Improved system reliability with each device being subjected to 100% thermal limit burn-in.
Adjustable positive voltage regulators:

Figure 8.03 shows the typical connection diagram of LM317 series adjustable 3-terminal positive voltage regulator.
The 3-terminals are: Vin, VOUT and ADJUSTMENT (ADJ).

LM317 From figure 8.03, LM317 requires only two resistors
VOUT VOUT
Vin (R1= 240Ω and R2= 3kΩ) to set the output voltage.
When configured, LM317 produces a 1.25 V, referred
ADJ
I1 R1 as reference voltage (VREF), between the output and
Vin IADJ adjustment terminal. Since this reference voltage is
LOAD constant, current I1 is also constant for a given value
of R1. Resistor R1 is called as current set or program
R2 resistor. Current (I1 + IADJ), flows through the output
set resistor R2.
Referring to the connection diagram, we will
determine the output voltage expression as:
The output voltage, VOUT = R1.I1 + R2(I1 + IADJ )-----(6.5)
Figure 8.03: Connection diagram of Positive Where, I1 = (Drop across R1)/ R1 = (VREF)/R1
R1 = Current (I1) set resistor
adjustable voltage regulator
R2= Output (Vo) set resistor
IADJ = Adjustment pin current (100µA max. Value)
By - Vikas Bhujade
Substituting the value of I1 in equation 6.5, we get:

𝐑
𝐕𝐎 = 𝐕𝐑𝐄𝐅 (𝟏 + 𝐑𝟐 ) + 𝐈𝐀𝐃𝐉 𝐑 𝟐 ------------------------------------- (6.6)
𝟏
Where, VREF = 1.25V and however IADJ is very small (100µA) and constant. Therefore, drop across resistor R2 is very
small and can be neglected.
𝐑
Hence, 𝐕𝐎 = 𝐕𝐑𝐄𝐅 (𝟏 + 𝐑𝟐 ) --------------------------------------- (6.7)
𝟏
Equation 6.7 indicated that the output voltage Vo is a function of resistor R2 for a given value of resistor R1 and
can be varied by adjusting the value of resistor R2. To achieve good regulation, resistor R1 shoud be tied directly
to the output of the regulator, as shown in figure 8.03.
Table 1.3 shows the different grade LM317 regulators.
Device Vo (V) Io (A) Vin (max) in volts Ripple rejection (dB)
LM317 1.2 to 37 1.5 40 80
LM317H 1.2 to 37 0.5 40 80
LM317HV 1.2 to 57 1.5 60 80
LM317HVH 1.2 to 37 0.50 40 80
LM317L 1.2 to 37 0.10 40 65
LM317M 1.2 to 37 0.50 40 80
Table 1.3
The different grades of regulators in the series are available with output voltage of 1.2 to 57V and output current
from 0.10 to 1.5A. These ICs are available in standard transistor packages that are easily mounted and handled.
Adjustable negative voltage regulator:

LM337 series is adjustable negative voltage regulators devices. These are available in same voltage and current
options as LM317 devices. Table 1.4 shows the different grades of regulators in the series.
Device Vo (V) Io (A) Vin (max) in volts Ripple rejection (dB)
LM337 −1.2 to −37 1.5 40 77
LM337H −1.2 to −37 0.5 40 77
LM337HV −1.2 to −47 1.5 50 77
LM337HVH −1.2 to −47 0.50 50 77
LM337LZ −1.2 to −37 0.10 40 65
LM337M −1.2 to −37 0.50 40 77
TABLE 1.4
Disadvantage: Fixed and adjustable voltage regulators such as 78XX, 79XX and LM317 and LM337 are called as
series dissipative regulators because these regulators creates a variable resistance between the input voltage and
the load, and hence function in a linear mode. Thus linear regulator maintains a constant output voltage by
dissipating the excess power as heat. Conversion efficiency of series dissipative regulator decreases as the
input/output voltage increases or vice versa. Hence, for this reason the linear series regulator is matched with
medium current applications, where power dissipation can be handled with heat sinks.
SWITCHING REGULATORS:
To improve the conversion efficiency of regulator, the series-pass transistor is used as a switch, rather than as a
variable resistor as in linear series regulator. A regulator constructed in this manner is called as switching
regulator. In switching regulators, a series pass transistor is used to switch between cut off and saturation at a
high frequency, which produces a pulse width modulated square wave output. This PWM output is then filtered
through a Low Pass LC filter to produce an average DC output voltage. The conversion efficiency of this regulator is
independent of input/output differential and can approach up to 95%.
Switching regulators comes in various configurations such as: Fly back, feed forward, push pull, and non-isolated
single ended or single polarity types.
By - Vikas Bhujade
The way, in which the components (switch and filter) are connected, the switching regulators can operates in any
of the three modes: Step down, step up, or polarity inverting.
Basic Switching regulator:
Basic switching regulator has 4-major components: (i) Voltage source VIN (ii) Switch S1 (iii) Pulse generator VPulse
and (iv) Filter F1. Figure 8.04 shows the interconnection between the components of basic switching regulator.
(i)Voltage Source, VIN : Supply Voltage source VIN may be any DC supply ie. a battery or an unregulated or a
regulated voltage. Following requirements must satisfy by the voltage source are:
1) The losses associated with voltage source and the required output power must be supplied by voltage source.
2) It must be large enough to supply satisfactory dynamic range for line and load variations.
3) It must be sufficiently high to meet the minimum requirement of the regulator system to be designed.
4) During power failure, voltage source should store energy for specified amount of time, for a back up.
(ii) Switch S1: Transistor or thyristor is
used as power switch. Switch is operated
Switch S1 Filter F1 in saturated mode. Generally output of
pulse generator used to turn the switch
Supply Voltage ON and OFF.
+
VIN (iii) Pulse Generator VPulse: It produces an
− Pulse Generator
LOAD asymmetrical square wave varying in
either frequency or pulse width called
VPulse frequency modulation or pulse width
modulation. Effective frequency range of
pulse generator is around 20kHz and is
well within the switching speeds of
Figure 8.04: Connection diagram of basic switching regulator
transistors and diodes.
The duty cycle of pulse waveform is given as :

𝐭𝐎𝐍 𝐭𝐎𝐍
duty cycle = = = (𝐭 𝐎𝐍 ∙ 𝐟); Where, tON = on-time of the pulse waveform
𝐭𝐎𝐍 +𝐭𝐎𝐅𝐅 𝐓
tOFF = off-time of the pulse waveform; T = time period.
Typical operating frequencies of switching regulators range from 10 to 50 kHz.
(iv) Filter F1: Filter is one of the major components in filter designing. The basic filter types are RC,RL and RLC,
which are used in switching regulators. The RLC filter is most commonly used filter. Filter F1 converts the pulse
into a DC voltage.
𝐭
Output Voltage VO, is a function of duty cycle and input voltage VIN, and is expressed as : 𝐕𝐎 = ( 𝐎𝐍 ) × 𝐕𝐈𝐍
𝐓
Expression of output Voltage VO, indicates that when time period T is held constant, VO is directly proportional to
the on-time, tON for a given value of VIN. This method of changing the output voltage by varying t ON is referred to as
pulse width modulation (PWM). Similarly, if tON is held constant, output voltage is inversely proportional to time
period, T or directly proportional to frequency f of pulse waveform. This method of changing the output voltage by
varying frequency f, is referred to as frequency modulation (FM).
Switching regulators are used in commercial switching supplies with multiple outputs. µA78S40 is an example of
switching regulator.
By - Vikas Bhujade
DUAL POWER SUPPLY:

Figure 8.05 shows the circuit diagram of dual DC power supply.
Bridge rectifier circuit, which will convert the
ac supply into dc supply. The output of the
IN 1 IC78XX OUT rectifier circuit ie. DC, contains the ripples in
3 the output voltage. To filter out these ripples,
2
capacitors C1 and C2 are used. The output of
+ GND +VOUT
Bridge Rectifier C1 the capacitor that is pure DC is given to voltage
− regulator IC78XX and IC79XX which will
output. Ie. DC
which contains + regulate the output voltage at +XX Volt and
C2
ripples − –XX Volt DC, despite the change in input
GND
−VOUT voltage.
1
IN OUT
2 3
IC79XX
Figure 8.05: Dual DC power supply
By - Vikas Bhujade

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Department of Electronics and Communication Engineering

OP-AMP AS FILTERS (ACTIVE FILTERS):

MAGNITUDE AND FREQUENCY RESPONSE OF FILTERS:

Pass Band Stop Band Stop Band Pass Band

Gain Ideal Response Gain

FIRST ORDER LOW PASS BUTTERWORTH FILTER:

VIN Pass Band Stop Band

SECOND-ORDER LOW PASS BUTTERWORTH FILTER:

SECOND ORDER LOW PASS FILTER DESIGN STEPS:

FIRST ORDER HIGH PASS BUTTERWORTH FILTER:

SECOND ORDER HIGH PASS BUTTERWORTH FILTER:

HIGHER ORDER FILTERS:

Figure6.10: Third order Filter Figure6.11: Fourth order Filter

BAND PASS FILTERS:

Stop Band Pass Band Stop Band

Narrow Band Pass Filter: Comparator

BAND REJECT FILTERS :

ALL PASS FILTER:

Figure 7.01 shows the functional block

IC-555 AS MONOSTABLE MULTIVIBRATOR:

IC-555 AS ASTABLE MULTIVIBRATOR:

OP-AMP AS SCHMITT TRIGGER:

Figure 7.05(a): Op-Amp as Schmitt Trigger VIN >VLT

OP-AMP AS VOLTAGE LIMITERS:

OP-AMP AS CLIPPERS AND CLAMPERS:

NEGATIVE CLIPPER CIRCUIT:

SMALL SIGNAL HALF-WAVE RECTIFIERS (POSITIVE):

SMALL SIGNAL HALF-WAVE RECTIFIERS (NEGATIVE):

NEGATIVE HALF-WAVE RECTIFIER:

POSITIVE AND NEGATIVE CLAMPERS:

input separately. Considering VREF input first, connected 0

ABSOLUTE VALUE OUTPUT CIRCUIT:

Circuit Operation: During positive half cycle of input

+VP Input Voltage VIN

SAMPLE AND HOLD CIRCUIT:

VOLTAGE TO CURRENT CONVERTER WITH GROUNDED LOAD:

Substituting, I1 and I2 in equation no. 6.1, we get,

VOLTAGE TO CURRENT CONVERTER WITH FLOATING LOAD:

Applying Kirchhoff’s voltage law to the input circuit, we get, VIN = VA

CURRENT TO VOLTAGE CONVERTER:

PRECISION FULL WAVE RECTIFIER : [ABSOLUTE VALUE OUTPUT CIRCUIT]

PRECISION HALF WAVE RECTIFIER : [SMALL SIGNAL HALF-WAVE RECTIFIERS]

SERIES VOLTAGE REGULATOR USING OP-AMP:

From virtual ground concept

FIXED VOLTAGE REGULATORS:

Adjustable positive voltage regulators:

The 3-terminals are: Vin, VOUT and ADJUSTMENT (ADJ).

Substituting the value of I1 in equation 6.5, we get:

Adjustable negative voltage regulator:

The duty cycle of pulse waveform is given as :

DUAL POWER SUPPLY:

Figure 8.05: Dual DC power supply

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