CPE 6204 – Logic Circuits and Switching Theory

1
Sequential Logic Circuits

Module 9: Sequential Logic Circuits

Course Learning Outcomes:

1. Discuss the importance of sequential logic circuits
2. Examine the behavior of the building blocks of sequential circuits
3. Determine the future output of a latch or a flip-flop, given its input signals.
4. Differentiate synchronous from asynchronous sequential circuits.

Note to the Instructor and the Students

If you haven’t already, you may consider using a logic designer/logic simulator program to
do laboratory activities. At this point, using ICs will be counterproductive because wiring and
troubleshooting can be complicated and may result to a lot of time wasted.
There are a number of free, downloadable software available on the Internet. LogicCircuit is
one example. The link to the site is included on the reference list.

Sequential Circuits
We now will analyze and design sequential logic. The outputs of sequential logic depend on
both current and prior input values. Hence, sequential logic has memory. Sequential logic
might explicitly remember certain previous inputs, or it might distill the prior inputs into a
smaller amount of information called state of the system. The state of a sequential circuit is
a set of bits called state variables that contain all the information about the past necessary to
explain the future behavior of a circuit.
We begin with a study of latches and flip-flops, which are simple sequential circuits that store
one bit of state. In general, sequential circuits are complicated to analyze. To simplify design,
we will concentrate on building synchronous sequential circuits consisting of combinational
logic and banks of flip-flops containing the state of the circuit.
We shall also be discussing finite state machines, which are an easy way to design sequential
circuits.

The Building Block of Memory

The fundamental building block of memory is a bistable element – an element with two
stable states. Figure 1(a) shows a simple bistable element consisting of a pair of inverters
connected in a loop. Figure 1(b) shows the same circuit redrawn to emphasize the symmetry.
The inverters are cross-coupled, meaning that the input of I1 is the output of I2, and vice
versa. The circuit has no inputs, but it has two outputs, 𝑄 and 𝑄̅.

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 Figure 1. Cross-coupled inverter pair

Analyzing this circuit is different from analyzing a combinational circuit because it is cyclic:
𝑄 depends on 𝑄̅, and 𝑄̅ depends on 𝑄.
Let’s consider the two cases, 𝑄 = 0 or 𝑄 = 1. Working through the consequences of each
case, we have:
• CASE I: 𝑄 = 0
As shown in Figure 2(a), I2 receives a FALSE input, 𝑄, so it produces a TRUE output on 𝑄̅.
I1 receives a TRUE input, 𝑄̅, so it produces a FALSE output on 𝑄. This is consistent with
the original assumption that 𝑄 = 0, so the case is said to be stable.
• CASE II: 𝑄 = 1
As shown in Figure 2(b), I2 receives a TRUE input and produces a FALSE output on 𝑄̅. I1
receives a FALSE input and produces a TRUE output on 𝑄. This is again stable.

Figure 2. Bistable operation of cross-coupled inverters

Because the cross-coupled inverters have two stable states, 𝑄 = 0 and 𝑄 = 1, the circuit is
said to be bistable. A subtle point is that the circuit has a third possible state with both
outputs approximately halfway between 0 and 1. This is called a metastable state.
An element with 𝑁 stable states conveys log 2 𝑁 bits of information, so a bistable element
stores one bit. The state of the cross-coupled inverters is contained in one binary state
variable, 𝑄. The value of 𝑄 tells us everything about the past that is necessary to explain the
future behavior of the circuit. Specifically, if 𝑄 = 0, it will remain 0 forever, and it 𝑄 = 1, it
will remain 1 forever. The circuit does not have another node, 𝑄̅, but 𝑄̅ does not contain any
additional information because if 𝑄 is known, 𝑄̅ is also known. On the other hand, 𝑄̅ is also
an acceptable choice for the state variable.
When power is first applied to a sequential circuit, the initial state is unknown and usually
unpredictable. It may differ each time the circuit is turned on.
 CPE 6204 – Logic Circuits and Switching Theory
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Sequential Logic Circuits

Although the cross-coupled inverters can store a bit of information, they are not practical
because the user has no inputs to control the state. However, other bistable elements, such
as latches and flip-flops, provide inputs to control the value of the state variable.

SR Latch
One of the simplest sequential circuits is the SR latch, which is composed of two cross-
coupled NOR gates, shown in Figure 3. The latch has two inputs, 𝑆 and 𝑅, and two outputs, 𝑄
and 𝑄̅. The SR latch is similar to the cross-coupled inverters, but its state can be controlled
through the 𝑆 and 𝑅 inputs, which set and reset the output 𝑄.

Figure 3. SR latch

A good way to understand an unfamiliar circuit is to look at its truth table. We must recall
that a NOR gate produces a FALSE output when either input is TRUE. Consider the four
possible combinations of 𝑆 and 𝑅.
• CASE I: 𝑅 = 1, 𝑆 = 0
N1 sees at least one TRUE input, 𝑅, so it produces a FALSE output on 𝑄. N2 sees both 𝑄
and 𝑆 FALSE, so it produces a TRUE output on 𝑄̅.
• CASE II: 𝑅 = 0, 𝑆 = 1
N1 receives inputs of 0 and 𝑄̅ . Because we don’t yet know 𝑄̅ , we can’t determine the
output 𝑄. N2 receives at least one TRUE input, 𝑆, so it produces a FALSE output on 𝑄̅.
Now we can revisit N1, knowing that both inputs are false, so that the output 𝑄 is TRUE.
• CASE III: 𝑅 = 1, 𝑆 = 1
N1 and N2 both see at least one TRUE input (𝑅 or 𝑆), so each produces a FALSE output.
Hence, 𝑄 and 𝑄̅ are both FALSE.
• CASE IV: 𝑅 = 0, 𝑆 = 0
N1 receives inputs of 0 and 𝑄̅ . Because we don’t yet know 𝑄̅ , we can’t determine the
output. N2 receives the inputs of 0 and 𝑄 . Because we don’t yet know 𝑄 , we can’t
determine the output. Now we are stuck. This reminds us of the cross-coupled inverters.
But we know that 𝑄 must either be 0 or 1. So we can solve the problem by checking what
happens in each of these subcases.
o CASE IV(a): 𝑄 = 0
Because 𝑆 and 𝑄 are FALSE, N2 produces a TRUE output on 𝑄̅, as shown in Figure
4(a). Now N1 receives one TRUE input, 𝑄̅, so its output 𝑄, is FALSE, just as we had
assumed.
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 o CASE IV (b): 𝑄 = 1
Because Q is TRUE, N2 produces a FALSE output on 𝑄̅, as shown in Figure 4(b).
Now N1 receives two FALSE inputs, 𝑅 and 𝑄̅ , so its output 𝑄, is TRUE, just as
expected.

Figure 4. Bistable states of SR latch

Putting this all together, suppose 𝑄 has some known prior value, which we will call 𝑄𝑝𝑟𝑒𝑣 ,
before we enter Case IV. 𝑄𝑝𝑟𝑒𝑣 is either 0 or 1and represents the state of the system. When
𝑅 and 𝑆 are 0, 𝑄 will remember this old value, 𝑄𝑝𝑟𝑒𝑣 , and 𝑄̅ will be its complement, 𝑄̅𝑝𝑟𝑒𝑣 . We
now know that this circuit has memory.
The truth table in Figure 5 summarizes these four cases. The inputs 𝑆 and 𝑅 stand for 𝑆𝑒𝑡
and 𝑅𝑒𝑠𝑒𝑡. To set a bit means to make it TRUE. To reset a bit means to make it FALSE. The
outputs, 𝑄 and 𝑄̅, are normally complementary. When 𝑅 is asserted (𝑆 = 0, 𝑅 = 1), 𝑄 is reset
to 0 and 𝑄̅ does the opposite. When 𝑆 is asserted (𝑆 = 1, 𝑅 = 0), 𝑄 remembers its old value
𝑄𝑝𝑟𝑒𝑣 . Asserting both 𝑆 and 𝑅 simultaneously ( 𝑆 = 1, 𝑅 = 1 ) doesn’t make much sense
because it means the latch should be set and reset at the same time, which is impossible. The
circuit responds by making both inputs 0.

Figure 5. SR latch truth table

Figure 6. SR latch symbol

The SR latch is represented by the symbol in Figure 6. Using the symbol is an application of
abstraction and modularity. There are various ways to build an SR latch, such as using
different logic gates or transistors. Nevertheless, any circuit element with the relationship
specified by the truth table in Figure 5 and the symbol in Figure 6 is called an SR latch.
Like the cross-coupled inverters, the SR latch is a bistable element with one bit of state stored
in 𝑄. However, the state can be controlled through the 𝑆 and 𝑅 inputs. When 𝑅 is asserted,
the state is reset to 0. When 𝑆 is asserted, the state is set to 1. When neither is asserted, the
state retains its old value. notice that the entire history of inputs can be accounted for by the
single state variable 𝑄. No matter what pattern of setting and resetting occurred in the past,
 CPE 6204 – Logic Circuits and Switching Theory
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Sequential Logic Circuits

all that is needed to predict the future behavior of the SR latch is whether it was most recently
set or reset.

D Latch
The SR latch is awkward because it behaves strangely when both 𝑆 and 𝑅 are simultaneously
asserted. Moreover, the 𝑆 and 𝑅 inputs conflate the issues of what and when. Asserting one
of the inputs determines what the state should be, as well as when it should change.
Designing circuits becomes easier when these questions of what and when are separated.
The D latch in Figure 7(a) solves these problems.
The D latch has two inputs. The data input, D, controls what the next state should be. The
clock input, CLK, controls when the state should change.

Figure 7. D latch: (a) diagram/schematic, (b) truth table, (c) symbol

Again, we analyze the latch by writing the truth table, given in Figure 7(b). We first consider
the internal nodes 𝐷̅ , 𝑆, and 𝑅. If 𝐶𝐿𝐾 = 0, both 𝑆 and 𝑅 are FALSE regardless of the value of
𝐷. If 𝐶𝐿𝐾 = 1, one AND gate will produce TRUE and the other FALSE, depending on the value
of 𝐷. Given 𝑆 and 𝑅, 𝑄 and 𝑄̅ are determined using the table in Figure 5. We notice that in all
cases, 𝑄̅ is the complement of 𝑄, which seems logical. The D latch avoids the strange case of
simultaneously asserted 𝑅 and 𝑆 inputs.
Putting it all together, the clock controls when data flows through the latch. When 𝐶𝐿𝐾 = 1,
the latch is transparent; the data at 𝐷 flows through to 𝑄 as if the latch were just a buffer.
When 𝐶𝐿𝐾 = 0, the latch is opaque. It blocks the new data from flowing through to 𝑄, and 𝑄
retains the old value. Hence, the D latch is sometimes called a transparent latch or level-
sensitive latch. The D latch symbol is given in Figure 7(c).
The D latch updates its state continuously while 𝐶𝐿𝐾 = 1. We shall see later on that it is
useful to update the state only at a specific instant in time.

D Flip-Flop
A D flip-flop can be built from two back-to-back D latches controlled by complementary
clocks, as shown in Figure 8(a). The first latch, L1, is called the master. The second latch, L2,
is called the slave. The node between them is named N1. A symbol for the D flip-flop. When
the 𝑄̅ output is not needed, we condense the symbol. See Figure 8(c).

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 Figure 8. D flip-flop: (a) schematic, (b) symbol, (c) condensed symbol

When 𝐶𝐿𝐾 = 0, the master latch is transparent and the slave is opaque. When 𝐶𝐿𝐾 = 1, the
master goes opaque and the slave becomes transparent. The value at N1 propagates to 𝑄,
but N1 is cut off from 𝐷. So, whatever value was at 𝐷 immediately before the clock rises from
0 to 1 gets copied to 𝑄 immediately after the clock rises. At all other times, 𝑄 retains its old
value, because there is always an opaque latch blocking the path between 𝐷 and 𝑄.
In other words, a D flip-flop copies 𝑫 to 𝑸 on the rising edge of the clock and remembers
its state at all other times. The rising edge of the clock is often just called clock edge. The
𝐷 input specifies what the new state will be. The clock edge indicates when the state should
be updated.
A D flip-flop is also known as a master-slave flip-flop, an edge-triggered flip-flop, or a
positive edge-triggered flip-flop. The triangle in the symbols denotes an edge-triggered
clock input. The 𝑄̅ output is often omitted when not needed.

The precise distinction between flip-flops and latches is somewhat muddled and has evolved over
time. In common industry usage, a flip-flop is edge-triggered. In other words, it is a bistable element
with a clock input. The state of the flip-flop changes only in response to a clock edge, such as when
the clock rises from 0 to 1. Bistable elements without an edge-triggered clock are commonly called
latches.
The term flip-flop or latch by itself usually refers to a D flip-flop or D latch, respectively, because these
are the types most commonly used in practice.

Register
An 𝑁-bit register is a bank of 𝑁 flip-flops that share a common CLK input, so that all bits of
the register are updated at the same time. Registers are the key building block of most
sequential circuits. Figure 9 shows a schematic and symbol for a four-bit register with inputs
𝐷3:0 and outputs 𝑄3:0 . 𝐷3:0 and 𝑄3:0 are both 4-bit busses.
 CPE 6204 – Logic Circuits and Switching Theory
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Sequential Logic Circuits

Figure 9. A 4-bit register: (a) schematic, (b) symbol

Enabled Flip-Flop
An enabled flip-flop adds another input called EN or ENABLE to determine whether data is
loaded on the clock edge. When 𝐸𝑁 is TRUE, the enabled flip-flop behaves like an ordinary D
flip-flop. When 𝐸𝑁 is FALSE, the enabled flip-flop ignores the clock and retains its state.
Enabled flip-flops are useful when we wish to load a new value into a flip-flop only some of
the time, rather than on every clock edge.

Figure 10. Enabled flip-flop: (a,b) schematics, (c) symbol

Figure 10 shows two ways to construct an enabled flip-flop from a D flip-flop and an extra
gate. In figure 10(a), an input multiplexer chooses whether to pass the value at 𝐷, if 𝐸𝑁 is
TRUE, or to recycle the old state from 𝑄, if 𝐸𝑁 is FALSE. In Figure 10(b), the clock is gated.
If 𝐸𝑁 is TRUE, the 𝐶𝐿𝐾 input to the flip-flop toggles normally. If 𝐸𝑁 is FALSE, the 𝐶𝐿𝐾 input
is also FALSE and the flip-flop retains its old value. notice that 𝐸𝑁 must not change while
𝐶𝐿𝐾 = 1 , lest the flip-flop see a clock glitch (switch at an incorrect time). Generally,

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 performing logic on the clock is a bad idea. Clock gating delays the clock and cause timing
errors, so we must do it only if we are sure what we are doing. The symbol for an enabled
flip-flop is given in Figure 10(c).

Resettable Flip-Flop
A resettable flip-flop adds another input called RESET. When RESET is FALSE, the resettable
flip-flop behaves like an ordinary D flip-flop. When 𝑅𝐸𝑆𝐸𝑇 is TRUE, the resettable flip-flop
ignores 𝐷 and resets the output to 0. Resettable flip-flops are used when we want to force a
known state (i.e., 0) into all the flip-flops in a system when we first turn it on.
Such flip-flops may be synchronously or asynchronously resettable. Synchronously
resettable flip-flops reset themselves only on the rising edge of CLK. Asynchronously
resettable flip-flops reset themselves as soon as 𝑅𝐸𝑆𝐸𝑇 becomes TRUE, independent of 𝐶𝐿𝐾.

Figure 11. Synchronously resettable flip-flop: (a) schematic, (b, c) symbols

Figure 11(a) shows how to construct a synchronously resettable flip-flop from an ordinary
̅̅̅̅̅̅̅̅̅ is FALSE, the AND gate forces a 0 into the flip-flop.
D flip-flop and an AND gate. When 𝑅𝐸𝑆𝐸𝑇
̅̅̅̅̅̅̅̅̅
In this example, 𝑅𝐸𝑆𝐸𝑇 is an active low signal, meaning that the reset signal performs its
function when it is 0, not when it is 1. By adding an inverter, the circuit could have accepted
an active high reset signal instead. Figures 11(b) and 11(c) show symbols for the resettable
flip-flop with active high reset.
Asynchronously resettable flip-flops require modifying the internal structure of the flip-flop,
which may be left to the student to design; however, they are frequently available to the
designer as a standard component.
Settable flip-flops are also occasionally used. They load a 1 into the flip-flop when the SET is
asserted, and there are synchronous and asynchronous versions as well. Resettable and
settable flip-flops may also have an enable input and may be grouped into 𝑁-bit registers.

A Note on Other Latches and Flip-Flops

Not all latches and flip-flops have been discussed in this module. Those that have been
omitted offer refinements of the basic SR latch or the basic flip-flop (gated SR latch, JK flip-
flop, T flip-flop). You may look them up for a better understanding of latches and flip-flops.

Synchronous Logic Design

In general, sequential circuits include all circuits that are not combinational—that is, those
whose output cannot be determined simply by looking at the current inputs. In this module,
we examine some of those curious circuits. Then we introduce the notion of synchronous
sequential circuits and the dynamic discipline. By disciplining ourselves to synchronous
sequential circuits, we can develop easy, systematic ways to analyze and design sequential
systems.
 CPE 6204 – Logic Circuits and Switching Theory
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Sequential Logic Circuits

Some Problematic Circuits

Example 1: Astable Circuits

Alyssa encounters three misbegotten inverters who have tied
themselves in a loop, as shown in Figure 12. The output of the
third inverter is fed back to the first inverter. Each inverter
Figure 12. Three-inverter loop
has a propagation delay of 1 ns. Determine what the circuit
does.
SOLUTION:
Suppose node 𝑋 is initially 0. Then 𝑌 = 1 ,
𝑍 = 0, so 𝑋 = 1, which is inconsistent with
out original assumption. The circuit has no
stable states and is said to be unstable or
astable. Figure 13 shows the behavior of the
circuit. If 𝑋 rises at time 0, 𝑌 will fall at 1 ns, 𝑍
will rise at 2 ns, and 𝑋 will fall again at 3 ns.
Figure 13. Ring oscillator waveforms
In turn, 𝑌 will rise at 4 ns, 𝑍 will fall at 5 ns,
and 𝑋 will rise again at 6 ns, and then the pattern will repeat. Each node oscillates between
0 and 1 with a period (repetition time) of 6 ns. This circuit is called a ring oscillator.
The period of the ring oscillator depends on the propagation delay of each inverter. This
delay depends on how the inverter was manufactured, the power supply voltage, and even
the temperature. Therefore, the ring oscillator period is difficult to accurately predict. In
short, the ring oscillator is a sequential circuit with zero inputs and one output that changes
periodically.

Example 2: Race Conditions

Ben designed a new D latch that he claims is better than Figure 7 because it uses fewer gates.
He has written the truth table to find the output 𝑄given the two inputs 𝐷 and 𝐶𝐿𝐾, and the
old state of the latch, 𝑄𝑝𝑟𝑒𝑣 . Based on this truth table, he has derived Boolean equations. He
obtains 𝑄𝑝𝑟𝑒𝑣 by feeding back the output 𝑄. His design is shown in Figure 14. Does this latch
work correctly, independent of the delays of each gate?

Figure 14. Ben's D latch design

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 SOLUTION:
Figure 15 shows that the circuit has a race condition that causes it to fail when certain gates
are slower than others. Suppose 𝐶𝐿𝐾 = 𝐷 = 1 . The latch is transparent and passes 𝐷
through to make 𝑄 = 1. Now, 𝐶𝐿𝐾 falls. The latch should remember its old value, keeping
𝑄 = 1. However, suppose the delay through the inverter from 𝐶𝐿𝐾 to ̅̅̅̅̅̅ 𝐶𝐿𝐾 is rather long
compared to the delays of the AND and OR gates. Then nodes N1 and 𝑄 may both fall before
̅̅̅̅̅̅ rises. In such a case, N2 will never rise, and 𝑄 becomes stuck at 0.
𝐶𝐿𝐾

Figure 15. Latch waveform illustrating race condition

This is an example of asynchronous circuit design in which outputs are directly fed back to
inputs. Asynchronous circuits known to have race conditions where the behavior of the
circuit depends on which of two paths through logic gates is fastest. One circuit may work,
while seemingly identical one build from gates with slightly different delays may not work.
Or the circuit may work only at certain temperatures or voltages at which the delays are just
right. These malfunctions are extremely difficult to track down.

Synchronous Sequential Circuits

The previous two examples contain loops called cyclic paths, in which outputs are fed
directly back to inputs. They are sequential rather than combinational circuits.
Combinational logic has no cyclic paths and no races. If inputs are applied to combinational
logic, the outputs will always settle to the correct value within a propagation delay. However,
sequential circuits with cyclic paths can have undesirable races or unstable behavior.
Analyzing such circuits for problems is time-consuming.
To avoid these problems, designers break the cyclic paths by inserting registers somewhere
in the path. This transforms the circuit into a collection of combinational and logic registers.
The registers contain the state of the system, which changes only at the clock edge, so we say
that the state is synchronized to the clock. If the clock is sufficiently slow, so that the inputs
to all registers settle before the next clock edge, all races are eliminated. Adopting this
discipline of always using registers in the feedback path leads us to the formal definition of
a synchronous sequential circuit.
We must recall that a circuit is defined by its input and output terminals and its functional
and timing specifications. A sequential circuit has a finite set of discrete states
{𝑆0 , 𝑆1 , … , 𝑆𝑘−1 }. A synchronous sequential circuit has a clock input, whose rising edges
indicate a sequence of times at which state transitions occur. We often use the terms current
state and next state to distinguish the state of the system at the present from the state to
which it will enter on the next clock edge. The functional specification details the next state

𝑡𝑝𝑐𝑞 stands for the time of propagation from clock to 𝑄 , where 𝑄 indicates the output of a
synchronous sequential circuit. 𝑡𝑐𝑐𝑞 stands for the time of contamination from clock to 𝑄. These are
analogous to 𝑡𝑝𝑑 and 𝑡𝑐𝑑 in combinational logic.
 CPE 6204 – Logic Circuits and Switching Theory
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Sequential Logic Circuits

and the value of each output for each possible combination of current state and input values.
The timing specification consists of an upper bound, 𝑡𝑝𝑐𝑞 , and a lower bound 𝑡𝑐𝑐𝑞 , on the time
from the rising edge of the clock until the output changes, as well as setup and hold times,
𝑡𝑠𝑒𝑡𝑢𝑝 and 𝑡ℎ𝑜𝑙𝑑 , that indicate when the inputs must be stable relative to the rising edge of the
clock.
The rules of synchronous sequential circuit composition teach us that a circuit is a
synchronous sequential circuit if it consists of interconnected circuit elements such that
• Every circuit element is either a register or a combinational circuit
• At least one circuit element is a register
• All registers receive the same clock signal
• Every cyclic path contains at least one register.
Sequential circuits that are not synchronous are called asynchronous.
A flip-flop is the simplest synchronous sequential circuit. It has one input 𝐷, one clock 𝐶𝐿𝐾,
one output 𝑄, and two states {0,1}. The functional specification for a flip-flop is that the next
state is 𝐷 and the output 𝑄 is the current state, as shown in Figure 16.

Figure 16. Flip-flop current state and next state

We often call the current state variable 𝑆 and the next state variable 𝑆′. In this case, the prime
after 𝑆 indicates next state, not inversion.
Two other common types of synchronous sequential circuits are called finite state machines
and pipelines.

Example 3: Synchronous Sequential Circuits

Which of the circuits in Figure 17 are synchronous sequential circuits?

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 Figure 17. Example circuits

SOLUTION:
Circuit (a) is combinational, not sequential, because it has no registers. (b) is a simple
sequential circuit with no feedback. (c) is neither a combinational circuit nor a synchronous
sequential circuit because it has a latch that is neither a register nor a combinational circuit.
(d) and € are synchronous sequential circuits; they are two forms of finite state machines
(next module discussion). (f) is neither combinational nor synchronous sequential because
it has a cyclic path from the output of the combinational logic back to the input of the same
logic but no register in the path. (g) is synchronous sequential in the form of a pipeline (not
covered in this class). (h) is not, strictly speaking, a synchronous sequential circuit because
the second register receives a different clock signal than the first, delayed by the two inverter
delays.

Synchronous and Asynchronous Circuits

Asynchronous design in theory is more general than synchronous design, because the timing
of the system is not limited by clocked registers. Just as analog circuits are more general than
digital circuits because analog circuits can use any voltage, asynchronous circuits are more
general than synchronous circuits because they can use any kind of feedback. However,
synchronous circuits have proved to be easier to design and use than asynchronous circuits.
Despite decades of research on asynchronous circuits, virtually all digital systems are
essentially synchronous.
Asynchronous circuits are occasionally necessary when communicating between systems
with different clocks or when receiving inputs at arbitrary times, just as analog circuits are
necessary when communicating with the real world of continuous voltages. Furthermore,
research in asynchronous circuits continues to generate interesting insights, some of which
can improve synchronous circuits, too.
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Sequential Logic Circuits

References and Supplementary Materials

Software
1. LogicCircuit, www.logiccircuit.org/download.html

Books and Journals

1. Mano, M. M., Ciletti, M.D. (2018). Digital Design: With an Introduction to the Verilog HDL,
VHDL, and SystemVerilog (6th ed.). New Jersey: Pearson.
2. Harris, D.M, Harris, S.L. (2016). Digital Design and Computer Architecture: ARM Edition.
Massachusetts: Elsevier Inc.
3. Roth, C.H. Jr., Kinney, L.L. (2014). Fundamentals of Logic Design (7th ed.). Connecticut:
Cengage Learning

Online Supplementary Reading Materials

1. Latches and Flip-Flops.
http://www.cs.ucr.edu/~ehwang/courses/cs120b/flipflops.pdf, Date Accessed: 31
October 2019
2. Latches and Flip-Flops. http://electricalacademia.com/digital-circuits/latches-flip-
flops/, Date Accessed: 31 October 2019
3. Digital Flip-Flops – SR, D, JK and T Flip-Flops,
https://www.electricaltechnology.org/2018/05/digital-flip-flops.html, Date
Accessed: 31 October 2019
4. Synchronous and Asynchronous Circuits, www.ee.surrey.ac.uk/Projects/CAL/seq-
switching/synchronous_and_asynchronous_cir.htm, Date Accessed: 31 October 2019

Online Instructional Videos

1. Latches and Flip-Flops, https://www.youtube.com/watch?v=1oXdgNReQ6o, Date
Accessed: 31 October 2019

Course Module