IMEL7002

Digital Integrated Circuits

2022
Instructors:
Prof. Chi Hang, Chan (Ivor)
University of Macau
Institute of Microelectronic

Lecture 3: Designing Combinational

Logic Circuits
 CMOS Process

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2 Lecture 3 2
 Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

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3 Lecture 3 3
 Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

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4 Lecture 3 4
 Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

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5 Lecture 3 5
 NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

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6 Lecture 3 6
 PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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7 Lecture 3 7
 Threshold Drops
VDD VDD
PUN
S D
VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S D

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8 Lecture 3 8
 Complementary CMOS Logic Style

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9 Lecture 3 9
 Example Gate: NAND

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10 Lecture 3 10
 Example Gate: NOR

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11 Lecture 3 11
 Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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12 Lecture 3 12
 Constructing a Complex Gate
VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

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13 Lecture 3 13
 Cell Design
• Standard Cells
– General purpose logic
– Can be synthesized
– Same height, varying width
• Datapath Cells
– For regular, structured designs (arithmetic)
– Includes some wiring in the cell
– Fixed height and width

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14 Lecture 3 14
 Standard Cell Layout Methodology –
1980s

Routing
channel
VDD

signals

GND

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15 Lecture 3 15
 Standard Cell Layout Methodology –
1990s
Mirrored Cell

No Routing VDD
channels
VDD

M2

M3
GND

Mirrored Cell GND

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16 Lecture 3 16
 Standard Cells
N Well
VDD Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects

Cell height is “12 pitch”

Out
In
2

Rails ~10
GND
Cell boundary

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17 Lecture 3 17
 Standard Cells
With minimal VDD With silicided VDD
diffusion diffusion
routing

VDD

M2
Out In Out
In
In Out

M1

GND GND

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18 Lecture 3 18
 Standard Cells
VDD 2-input NAND gate
VDD

B
A B

Out
A

GND

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19 Lecture 3 19
 Stick Diagrams
Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

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20 Lecture 3 20
 Stick Diagrams
Logic Graph X
A PUN
j C
B C

X i VDD
X = C • (A + B)
C
i B j A

A B
PDN
A GND
B
C

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21 Lecture 3 21
 Two Versions of C • (A + B)

A C B A B C

VDD VDD

X X

GND GND

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22 Lecture 3 22
 Consistent Euler Path
X

X i VDD

B j A

GND A B C

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23 Lecture 3 23
 OAI22 Logic Graph
X PUN
A C

B D D C

X VDD
X = (A+B)•(C+D)

C D
B A

A B PDN
A GND
B
C
D

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24 Lecture 3 24
 Example: x = ab+cd
x x

b c b c

x VDD x VD D

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

VD D

GND
a b c d
(c) stick diagram for ordering {a b c d}

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25 Lecture 3 25
 Multi-Fingered Transistors
One finger Two fingers (folded)

Less diffusion capacitance

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26 Lecture 3 26
 Properties of Complementary CMOS Gates
Snapshot

High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)

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27 Lecture 3 27
 CMOS Properties
• Full rail-to-rail swing; high noise margins
• Logic levels not dependent upon the relative
device sizes; ratioless
• Always a path to Vdd or Gnd in steady state; low
output impedance
• Extremely high input resistance; nearly zero
steady-state input current
• No direct path steady state between power and
ground; no static power dissipation
• Propagation delay function of load capacitance
and resistance of transistors

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28 Lecture 3 28
 Switch Delay Model
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

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29 Lecture 3 29
 Input Pattern Effects on Delay
• Delay is dependent on the
Rp Rp pattern of inputs
A B • Low to high transition
– both inputs go low
Rn CL • delay is 0.69 Rp/2 CL
B – one input goes low
• delay is 0.69 Rp CL
Rn
Cint • High to low transition
A
– both inputs go high
• delay is 0.69 2Rn CL

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30 Lecture 3 30
 Delay Dependence on Input Patterns
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
3
Input Data Delay
2.5 A=B=10
Pattern (psec)
2 A=B=01 67
A=1 0, B=1
1.5 A=1, B=01 64
Voltage [V]

1
A=1, B=10 A= 01, B=1 61

0.5 A=B=10 45

0 A=1, B=10 80
0 100 200 300 400 A= 10, B=1 81
-0.5
time [ps]

31
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 Transistor Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

32
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32 32 Lecture 3 32
 Transistor Sizing a Complex CMOS
Gate
B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

33
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33 33 Lecture 3 33
 Fan-In Considerations

A B C D

A CL Distributed RC model
(Elmore delay)
B C3
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C C2
Propagation delay deteriorates rapidly as a
D C1 function of fan-in – quadratically in the worst
case.

34
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34 34 Lecture 3 34
 tp as a Function of Fan-In
1250
quadratic
1000
Gates with a fan-in
750 greater than 4
should be avoided.
tp (psec)

tpHL tp
500

250 tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

35
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 tp as a Function of Fan-Out

All gates have the

same drive
tpNOR2 tpNAND2
current.

tpINV
tp (psec)

Slope is a function
of “driving
strength”

2 4 6 8 10 12 14 16

36
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 tp as a Function of Fan-In and Fan-Out

• Fan-in: quadratic due to increasing resistance

and capacitance
• Fan-out: each additional fan-out gate adds
two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

37 37
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37 37 Lecture 3 37
 Fast Complex Gates:
Design Technique 1
• Transistor sizing
– as long as fan-out capacitance dominates
• Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
38 38
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38 38
Lecture 3 38
 Fast Complex Gates:
Design Technique 2
• Transistor ordering

critical path critical path

charged 01
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

39 39
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39 39 Lecture 3 39
 Fast Complex Gates:
Design Technique 3
• Alternative logic structures
F = ABCDEFGH

40 40
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40 40 Lecture 3 40
 Fast Complex Gates:
Design Technique 4
• Isolating fan-in from fan-out using buffer
insertion

CL CL

41 41
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41 41 Lecture 3 41
 Fast Complex Gates:
Design Technique 5
• Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

– linear reduction in delay

– also reduces power consumption
• But the following gate is much slower!
• Or requires use of “sense amplifiers” on the receiving
end to restore the signal level (memory design)

42 42
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42 42 Lecture 3 42
 Sizing Logic Paths for Speed
• Frequently, input capacitance of a logic path is
constrained
• Logic also has to drive some capacitance
• Example: ALU load in an Intel’s microprocessor is
0.5pF
• How do we size the ALU datapath to achieve
maximum speed?
• We have already solved this for the inverter chain –
can we generalize it for any type of logic?

43 43
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43 43 Lecture 3 43
 Buffer Example
In Out

CL
1 2 N

N
Delay    pi  g i  f i  (in units of tinv)
i 1

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?

44 44
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44 44 Lecture 3 44
 Logical Effort
 CL 
Delay  k  Runit Cunit 1  
 Cin 
t p  g  f 
p – intrinsic delay (3kRunitCunit) - gate parameter  f(W)
g – logical effort (kRunitCunit) – gate parameter  f(W)
f – effective fanout

Normalize everything to an inverter:

ginv =1, pinv = 1

Divide everything by tinv

(everything is measured in unit delays tinv)
Assume  = 1.

45 45
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45 45 Lecture 3 45
 Delay in a Logic Gate
Gate delay:

d=h+p

effort delay intrinsic delay

Effort delay:

h=gf

logical effort effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizing

Effective fanout (electrical effort) is a function of load/gate size
46 46
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46 46 Lecture 3 46
 Logical Effort
• Inverter has the smallest logical effort and intrinsic
delay of all static CMOS gates
• Logical effort of a gate presents the ratio of its input
capacitance to the inverter capacitance when sized
to deliver the same current
• Logical effort increases with the gate complexity

47 47
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47 47 Lecture 3 47
 Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD VDD VDD

A 2 A 2 B 2 B 4

F
F
A 4
A 2
A 1 F

A 1 B 1
B 2

Inverter 2-input NAND 2-input NOR

g=1 g = 4/3 g = 5/3

48 48
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48 48 Lecture 3 48
 Logical Effort of Gates

t pNAND
g= t pINV
Normalized delay (d)

p=
d=
g=
p=
d=

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

49 49
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49 49 Lecture 3 49
 Logical Effort of Gates

t pNAND
g = 4/3 t pINV
Normalized delay (d)

p=2
d = (4/3)h+2
g=1
p=1
d = h+1

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

50 50
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50 50 Lecture 3 50
 Logical Effort of Gates

2
=
p
3;
4/
5 1

=
p=

g
Normalized Delay

1;

D:
4

AN
g =
tN er :
rt
pu
3 ve
In
in

Effort
2-

Delay
2

1
Intrinsic 
Delay

1 2 3 4 5
Fanout f
51 51
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51 51 Lecture 3 51
 Add Branching Effort

Branching effort:

Con  path  Coff  path

b
Con  path

52 52
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52 52 Lecture 3 52
 Multistage Networks
N
Delay    pi  g i  f i 
i 1

Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin
Path logical effort: 𝑖 =G = g1g2…gN (x
Branching effort: 𝑖=B = b1b2…bN
Path effort: H = G*B*F

Path delay D = Sdi = Spi + Shi

53 53
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53 53 Lecture 3 53
 Optimum Effort per Stage
When each stage bears the same effort:

h H
N

hN H
Stage efforts: g1f1 = g2f2 = … = gNfN

Effective fanout of each stage:

fi  h gi
Minimum path delay

D   g i f i  pi   NH  P
ˆ 1/ N

54 54
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54 54 Lecture 3 54
 Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing

D  NH 1/ N
 Npinv
D
N
 
  H 1/ N ln H 1/ N  H 1/ N  pinv  0

1 / Nˆ
Substitute ‘best stage effort’ hH

55 55
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55 55 Lecture 3 55
 Logical Effort

From Sutherland, Sproull

56 56
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56 56 Lecture 3 56
 Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F =
G=
H=
h=
a=
b=

57 57
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57 57 Lecture 3 57
 Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59

58 58
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58 58 Lecture 3 58
 Example: Optimize Path

1 b c
a 5

g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1

Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59

59 59
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59 59 Lecture 3 59
 Assignment1 – 8-input AND
Big loading (50) and small loading scenario (1), which setup is better?

g=10/3 g=1 g=2 g=5/3 g=4/3 g=5/3 g=4/3 g=1

G=10/3 G=10/3 G=80/27

60 60
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60 60 Lecture 3 60
 Method of Logical Effort
• Compute the path effort: F = GBH
• Find the best number of stages N ~ log4F
• Compute the stage effort f = F1/N
• Sketch the path with this number of stages
• Work either from either end, find sizes:
Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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 Summary

Sutherland,
Sproull
Harris

62 62
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62 62 Lecture 3 62
Ratioed Logic
 Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

64 64
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64 64 Lecture 3 64
 Ratioed Logic
VDD

• N transistors + Load
Resistive
• VOH = V DD
Load RL

• VOL = RPN
F RPN + RL

In1 • Assymetrical response

In2 PDN
In3 • Static power consumption

• tpL = 0.69 RLCL

VSS

65 65
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65 65 Lecture 3 65
 Active Loads
VDD VDD

Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS

66 66
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66 66 Lecture 3 66
 Pseudo-NMOS
VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

V OL 2 kp
  2
k  V – V V – -------------  = ------  V – V 
n DD Tn OL 2  2 DD Tp


kp
V = V –V  1– 1 – ------ (assuming that V = V = V )
OL DD T k T Tn Tp
n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

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 Pseudo-NMOS VTC

3.0

2.5

2.0 W/Lp = 4

1.5
Vout [V]

W/Lp = 2
1.0

W/Lp = 0.5 W/Lp = 1

0.5

W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]

68 68
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68 68 Lecture 3 68
 Improved Loads

VDD

M1 M1 >> M2
Enable M2

CL
A B C D

Adaptive Load
69 69
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69 69 Lecture 3 69
 Improved Loads (2)
VDD VDD

M1 M2

Out Out

A
A PDN1 PDN2
B
B

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

70 70
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70 70 Lecture 3 70
 DCVSL Example

Out

Out

B B B B

A A

XOR-NXOR gate
71 71
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71 71 Lecture 3 71
 DCVSL Transient Response

2.5

AB
V ol ta ge [V]

1.5
AB
A, B
0.5 A,B

-0.5 0 0.2 0.4 0.6 0.8 1.0

Time [ns]

72 72
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72 72 Lecture 3 72
Pass-Transistor
Logic
 Pass-Transistor Logic

Switch Out A
Out
Inputs

Network B
B

• N transistors
• No static consumption

74 74
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74 74 Lecture 3 74
 Example: AND Gate
B

A
B
F = AB

75 75
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75 75 Lecture 3 75
 NMOS-Only Logic

3.0
In
In
1.5 m/0.25 m Out
2.0

Volta ge [V]
VD D x x
Out
0.5  m/0.25 m
0.5 m/0.25 m 1.0

0.0
0 0.5 1 1.5 2
Time [ns]

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76 76 Lecture 3 76
 NMOS-only Switch

C = 2.5V C = 2.5 V
M2
A = 2.5 V A = 2.5 V B
Mn
B
CL M1

V B does not pull up to 2.5V, but 2.5V - V TN

Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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 NMOS Only Logic:
Level Restoring Transistor

VDD
VDD
Level Restorer
Mr
B
M2
X
A Mn Out
M1

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X
• Ratio problem

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78 78 Lecture 3 78
 Restorer Sizing

3.0
•Upper limit on restorer size
•Pass-transistor pull-down
2.0 can have several transistors in
W/L r =1.75/0.25
V olta ge [V]

stack
W/L r =1.50/0.25

1.0

W/L r =1.0/0.25 W/L r =1.25/0.25

0.0
0 100 200 300 400 500
Time [ps]

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Solution 2: Single Transistor Pass Gate with VT=0

VDD

VDD
0V 2.5V

VDD 0V Out

2.5V

WATCH OUT FOR LEAKAGE CURRENTS

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 Complementary Pass Transistor Logic
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network

B B B B B B

A A A

B F=AB B F=A+B A F=AÝ

A A A
(b)

B F=AB B F=A+B A F=AÝ

AND/NAND OR/NOR EXOR/NEXOR

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81 81 Lecture 3 81
 Solution 3: Transmission Gate
C
C

A B A B

C
C

C = 2.5 V
A = 2.5 V
B
CL

C=0V

82 82
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 Resistance of Transmission Gate

30

2.5 V
Rn Rn
20 Rp
Resistance, ohms

2.5 V Vou t

Rp
0V
10
Rn || Rp

0
0.0 1.0 2.0
Vou t , V

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 Pass-Transistor Based Multiplexer

S S
VDD

V DD
S

A
M2

S F

M1
B

GND
In1 S S In2

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84 84 Lecture 3 84
 Transmission Gate XOR

B
M2

A
A
F
M1 M3/M4
B

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85 85 Lecture 3 85
 Delay in Transmission Gate Networks
2.5 2.5 2.5 2.5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In

C C C C C
0 0 0 0

(a)

Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In

C C C C C

(b)
m

Req Req Req Req Req Req

In
C CC C C CC C

(c)

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 Delay Optimization

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 Transmission Gate Full Adder

P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

Similar delays for sum and carry

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88 88 Lecture 3 88
Dynamic Logic
 Dynamic CMOS
• In static circuits at every point in time (except when
switching) the output is connected to either GND or
VDD via a low resistance path.
– fan-in of n requires 2n (n N-type + n P-type) devices

• Dynamic circuits rely on the temporary storage of

signal values on the capacitance of high impedance
nodes.
– requires on n + 2 (n+1 N-type + 1 P-type) transistors

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90 90 Lecture 3 90
 Dynamic Gate

Clk Mp Clk Mp
Out Out
In1 CL
A
In2 PDN
C
In3
B
Clk Me
Clk Me
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)

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91 91 Lecture 3 91
 Dynamic Gate
off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)

92 92
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92 92 Lecture 3 92
 Conditions on Output
• Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
• Inputs to the gate can make at most one transition
during evaluation.

• Output can be in the high impedance state during

and after evaluation (PDN off), state is stored on CL

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93 93 Lecture 3 93
 Properties of Dynamic Gates
• Logic function is implemented by the PDN only
– number of transistors is N + 2 (versus 2N for static complementary CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)
• Non-ratioed - sizing of the devices does not affect the
logic levels
• Faster switching speeds
– reduced load capacitance due to lower input capacitance (Cin)
– reduced load capacitance due to smaller output loading (Cout)
– no Isc, so all the current provided by PDN goes into discharging CL

94 94
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 Properties of Dynamic Gates
• Overall power dissipation usually higher than static
CMOS
– no static current path ever exists between VDD and GND
(including Psc)
– no glitching
– higher transition probabilities
– extra load on Clk
• PDN starts to work as soon as the input signals exceed
VTn, so VM, VIH and VIL equal to VTn
– low noise margin (NML)
• Needs a precharge/evaluate clock
95 95
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95 95 Lecture 3 95
 Issues in Dynamic Design 1: Charge
Leakage
CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

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96 96 Lecture 3 96
 Solution to Charge Leakage
Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

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 Issues in Dynamic Design 2: Charge
Sharing
Charge stored originally on CL is
redistributed (shared) over CL and CA
Clk Mp leading to reduced robustness
Out
A CL

B=0 CA

Clk Me CB

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 Charge Sharing Example

Clk
Out
A A CL=50fF

Ca=15fF B B B !B Cb=15fF

Cc=15fF C C Cd=10fF

Clk

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99 99 Lecture 3 99
 Charge Sharing
VDD
case 1) if V out < VTn

Clk Mp
C V = C V t + C V V V
Out L DD L out   a DD – Tn  X  
or
CL
A Ma Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
X C
L
Ca
B 0 Mb case 2) if V out > VTn

 Ca 
Cb Vout = –V DD  ---------------------- 
Clk Me  Ca + CL 

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 Solution to Charge Redistribution

Clk Mp Mkp Clk

Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased
area and power)

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101 101 Lecture 3 101
 Issues in Dynamic Design 3:
Backgate Coupling

Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

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 Backgate Coupling Effect
3

Out1
-1
0 2 4 6

Clk

In Out2

Time, ns

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 Issues in Dynamic Design 4: Clock
Feedthrough
Coupling between Out and Clk input of
the precharge device due to the gate to
Clk Mp drain capacitance. So voltage of Out can
Out rise above VDD. The fast rising (and
A CL falling edges) of the clock couple to Out.

Clk Me

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 Clock Feedthrough
2.5
Clock feedthrough
Clk 1.5

Out 0.5

In1
-0.5
0 0.5 1

In2

In3 In &
Clk
In4 Out
Clk
Time, ns
Clock feedthrough

105 105
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 Other Effects
• Capacitive coupling
• Substrate coupling
• Minority charge injection
• Supply noise (ground bounce)

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 Cascading Dynamic Gates
V

Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

V
Out2

Only 0  1 transitions allowed at inputs!

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 Domino Logic

Clk Mp Clk Mp Mkp

11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

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 Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

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 Properties of Domino Logic

• Only non-inverting logic can be implemented

• Very high speed
– static inverter can be skewed, only L-H transition
– Input capacitance reduced – smaller logical effort

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 Designing with Domino Logic
VDD VDD
VDD

Clk Mp Clk Mp
Mr
Out1

Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!

Clk Me Clk Me

Inputs = 0
during precharge

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 Footless Domino
VDD VDD VDD

Clk Mp Clk Mp Clk Mp

Out1 Out2 Outn
0 1 0 1 0 1
In1 In2 In3 Inn
1 0 1 0 1 0 1 0

The first gate in the chain needs a foot switch

Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage

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 Differential (Dual Rail) Domino
off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B

Clk Me

Solves the problem of non-inverting logic

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 np-CMOS

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

Only 0  1 transitions allowed at inputs of PDN Only 1  0

transitions allowed at inputs of PUN

114 114
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 NORA Logic

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

to other to other
PDN’s PUN’s
WARNING: Very sensitive to noise!

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