Chapter i 4. TABLE OF CONTENTS Outline of Functions and Features. Vt 1.2, Features Outline of Functions. 1.3 Summary of the Pnnciples of FM-type Sound Generation Construction and Features .§ 21 Block Diagram ... . 5 DLT Resistor. - - cee 5 22 Phase Generator. seen ocean 6 2.3 FM Operator... 7 2.1.4 Envelope Generator R 2LS Noise Generator... it 21.6 Low Frequency OSC.. 10 QF Timer 7 2 2.1.8 Accumulator. ests seit 22. Pin Wiring . 22.1 Pin Funetions... Device Specifications . "4 3.1. Maximum Ratings... 3.2 Electrical Characteristics... Interfacing1. OUTLINE OF FUNCTIONS AND FEATURES 1.1 Outline of Functions The YM2151 is an FM-type sound generator equipped with an 8 bit bus line and capable of producing superb audio quality via a microprocessor program. When this IC is used in tandem with the specially-developed YM3012 D/A converter, you can obtain 8-note, left-right/2-channel audio signals. In addition, this unit is equipped with noise, vibrato, an amplitude modulation circuit, a sound effects circuit, and timer. ‘The package is a 24-pin dual in-line package. 1.2 Features ‘© Generate up to 8 notes. © Generate noise. © Timbre can be altered temporally. ‘© High harmonic can be de-harmonized from the base frequency. © De-harmonize between octawes. © Interval settings of up to 1.6 cents. © Add vibrato and amplitude modulation. © Generate a variety of sound effects by extreme de- harmonization of the high harmonic from the base frequency and massive vibrato and amplitude modulation. 1.3 Summary of the Principles of FM-type Sound Generation FM-type sound can be expressed via 2 basic configuration like that depicted in Figure 1.1. If this were to be expressed formally, it would look like this: Fig. 11 (C+DEit) = A(t)*sinf(Ne+ De)*wt + B(t)*sin(Nm + Dm)=wi] A(t): Volume envelope B(t) : Timbre envelope Nx. : 1/2 of the basic pitch or multipie value Dx : 1/2 of the baste pitch (1.6 cents) harmonic walue For example, when B(t) = 0, you get a sine wave of (Nc + De) times with respect to the basic pitch. In this case, if we assume values for Nc and Dc like those given above, we will obtain 1/2 the basic pitch or a sine wave of multiple value. As long as the value for De is not 0, the ‘output will indicate a pitch sine wave slightly offset from 1/2 the basic pitch or multiple value ‘When B(t) is greater than 0, the output will not be a sine wave but 2 wave form including a high harmonic component, because B(1) * sin (Nm + Dm) * wris added onto the (Ne ~ Dc) + wt phase information. It therefore follows that a variety of wave forms including a bigh harmonic component cin be obtained by selecting different values for B(t) and (Nm+ Dm). Also, the timbre can be altered and output by temporal adjustment of B(t). Actual output patteros when altering the value of Bit) and (Nm + Dm) and adding it onto the previous pattern are indicated in Fig. 1.2~1.9. Fig. 1.2 Fig. 1.3 (Ne+ De)/(Nm+ Dmm)=1, BQ)= 0 (Ne+De)/(Nm + Dmp = 1, BE) = 0.5 Fig. 14 Fig. 1.5 (Ne+De)(Nm+Dm)=1, Bit)= 1.0 (Nc+ De)(Nm+ Dm)=1, B= 1.5 NIN MIMFig 1.6 Fig 1.7 (Ne+ Doy/(Nm+Dm)=1, Bi)=2.0 (Ne+ De)/(Nm + Dm) =0.5, Bit) =0.5 Fig. 1.8 Fig. 1.9 (Ne + De)/(Nm + Dm)=0.5, Bit) =1.0 (Ne+ De)/(Nm + Dm)=0.8, Bi)=1.5 Wy SW ‘The YM2I5I is equipped to handle 7 different kinds of combinatory connection methods, with two circuits composed of this basic structure assigned to a single note, which can be arranged serially or in parallel, or made to act as only a sine- wave sound souree, In addition, with the tunit set up as in Figure 1.10, with inclusion of a circuit that takes one’s own output signal and retums it to oneself, virtually any type of wave form can be obtained via proper adjustment. Fig. 1.10 (ee Dew SIN an TABLE aeAn example of the wave form in this case is depicted in Figure 1.11 Fig. 1.11 Example output of a-point waveform.2. CONSTRUCTION AND FEATURES 2.1 Block Diagram ‘The block diagram is as depicted in Figure 2.1. As explained in the previous section, the YM21S1 uses two FM modulation circuits for a single note. These are time division circuits, with sine table read fout times. Since it is possible 211 REG: Register ‘This is 256-byte area register for the storage of data which in turn drive and set the individual function circuits to be explained later. The address map is shown in Figure 23, When the, register is at initial clear (IC terminal =~"0"), all is “0” level. © B: WRITE BUSY FLAG (READ MODE) ‘The bit in the diagram below is shown being written in. From the time the write command \* received until the write is completed, a period of w 68 bits is required. During this time the fag reads “I~. When continuing data and writing in, itis necessary to confirm that the flag reads “0” before writing in the next datum. ERT © CT: CONTROL OUTPUT Bits Ds and D> correspond to output terminals CT! and CT2 and comprise the External control output port. At initial clear (IC terminal = ~“0"), the CT: and Cr; terminals read “0” level. * KON: KEY ON ‘As shown in the figure below, when entering a key on (off) which corresponds to a 3-bit channel number and a 4-bit slot. the sound source begins (ends). Writing in “1” for the tevel at SN tums the key on, while writing in “O” turns the key off. For the channel number please refer to the channel gumber in Figure 2.2. The SN bits Ds, Ds, Ds, and De correspond to Mi. Ci, Mz and C2 (bes b.DDyO}Y SN CHNo21.2 PG: Phase Generator ‘The phase information needed to fix the carrier frequency and modulator frequency is generated here by KC, KF, MUL, DTI, DT2, PMS data from the REG. Also, the production of vibrato effects by data from the LFO and sound effects due to frequency modulation, etc is carried out at the PG. © KC: KEY CODE (OCT, NOTE) The key code uses a datum per note, and a datum is composed of 7 bits as depicted in the figure below. The first 3 bits express the octave (8 octaves), and the last 4 bits express the note. The relation between octaves and notes on the one hand and intervals cn the other is depicted in Figure 2.4, A sound frequency of 440.0 Hz can be obtained by setting the device clock frequency st 3.579545 MHz and entering frequency data KC{OCT =4, NOTE= 10), KF=0, MUL= 1, DTI =0, DT2=0, PMS=0, [Kb-b: bpp oo] OCT NOTE © KF: KEY FRACTION The key fraction uses a datum per note, and a datum is composed of 6 bits as depicted in the figure below. With these 6 bits of data you can fix the phase information by dividing the note interval (100 cents) into 1.6-cent segments (see Figure 2.4). pobpbbXy —_—— KEY PRACTH © MUL: PHASE MULTIPLY Four data set one note, comprised of 4 bits as indicated in the figure below. With this function you can multiply the KC- and KF-input phase information, as shown in Figure 25. KEP Dp P| DT MUL © DTI: DETUNE (1) Four data set one note, comprised of 3 bits as indicated in the figure above. With this function you can detune the phase information from the frequency vis-a-vis the KC- and KF-input phase information, as shown in Figure 2.6. Also. the phase information from this DTI undergoes scaling via the key code.¢ DT2: DETUNE (2) Four data set one note, comprised of 2 bits as indicated in the figure below. With this function you can carry out gross detuning of the phase information from the frequency vieacvis the KC- and KF-imput phase information, as shown in Figure 2.7. This is effective when generating sound effects. ppd J a * PMS: PHASE MODULATION SENSITIVITY ‘One datum used to set a note, comprised of 3 bits as indicated in the figure below. You can obtain vibrato and trembling sounds from the LFO (low frequency oscillator) signals that express band width in 8 bits by adding them to the KC and KF. As indicated in Figure 2.8, this sensitivity can be controlled at 8 different levels. The value indicated here obtains when the LFO output is at its maximum value, KebbDDI PMS 21.3 OP: FM Operator Picks up the phase information from the PG and reads out the sine table, The read-out signal is multiplied by the envelope information from the EG. At end of OP circuit, connection switch js activated, of you can control the volume of feedback the phase information as necessary. Here, the FM-modulated signal is transmitted to ACC. CON: CONNECTION ‘One datum used to set a note, comprised of 3 bits as indicated in the figure below. With this CON, you can construct a distinct &-note OP circuit configuration that will allow you to produce all 8 notes with various timbre. Figure 2.9 shows this circuit construction. bpp poy Se FL CON = (Fo © FL: SELF FEEDBACK LEVEL ‘One datum used to set a note, comprised of 3 bits as indicated in the figure above. The FL level can be controlled for all notes as shown in Figure 2.10.21.4 EG: Envelope Generator The EG output is multiplied by the signal appearing after the OP reads out the sine table, imparting timbre and volume alterations. When the key on is entered at the EG, the EG changes in the manner indicated in the following figure. KEY on KEY OFF When the attenuation volume is x- On, pressed as a logarithm, the attack changes exponentially and the decay changes in a ° ; straight line. atequapoe pit volume The movement from TA to TDI, as MAX well as from TD1 to TD2, is carried out TA. , when the attenuation volume is 0 dB. as well as at the first decay level (DIL) © AR: ATTACK RATE Four data used to set a note, comprised of 5 bits as indicated in the figure below. When key on is entered at the EG, the attenuation volume diminishes, and after the attack time (TA) the attenuation volume approaches 0 dB. The attack time can be set by means of the AR as in Figure 2.11. Also, the AR is scaled by the key cade, so refer to Figure 2. X{[p-[b:[bs]p: [oy ——— AR © DIR: FIRST DECAY RATE Four data used to set a note, comprised of 5 bits as indicated in the figure below. When the attenuation volume is 0 dB, the EG automatically moves to first decay, obtaining first decay level. This first decay time (TD!) can be set by means of the DIR asin Figure 2.11 Also, DIR is scaled by the key code, so refer 1 Figure 2.12. RXbPp ppp] ——— DIR © D2R: SECOND DECAY RATE Four data used to set a note, with a datum comprised of 5 bits as indicated in the figure below. When the first decay level has been passed, the EG automatically moves to second decay and remains in this state until key off. This second decay time (TD2) can be set by means of the D2R as in Figure 2.11, Also, D2R is scaled by the key code, so refer to Figure 22 L Xp-eyp: [pp] DIR« RR: RELEASE RATE Four data used to set a note, with a datum comprised of 4 bits as indicated in the figure below. With key off the EG begins release and attenuation advances toward the maxtmam cusauation volume (96 dB). The release time (TR) can be set by means of the TR as in Figure 2-11. Also, RR is scaled by the key code, s refer to Figure 2.12. Note that because the RR contains one less bit than cither DIR or D2R, resolution will be poor. [ [pound —— RR © KS: KEY SCALING Four data used to set a note, with a datum comprised of 2 bits as indicated in the figure below. The KS scales the AR, DIR. D2R, and RR rates according to the key code, and this sealing can be controlled via four different levels as indicated in Figure 2.12. pot TTT —— KS ‘The attack, first decay, second decay, and release limes are set by each rate after it bas been sealed. DIL: FIRST DECAY LEVEL ‘Four data used to set @ note, with a datum comprised of 4 bits as indicated in the figure below. When EG passes this level it automatically moves from first decay to second decay: With 2 3B resolution, each bit weighted as indicated in Figure 2.13 pp-pi TTT) —— IL, «TL: TOTAL LEVEL Four data used to set a note, with a datum comprised of 7 bits as indicated in the figure below. The EG calculates the taral level (expressed ag attenuation volume} operated by the EG with respect to cach time and outputs this figure to the OP. controlling the timbre (modulation) as well as the volume Minimum resolution is 0.75 dB, with the bits weighted as indicated in Figure 2.14 bp b-pAp DT: —— cf«© AMS: AMPLITUDE MODULATION SENSITIVITY One datum used to sct a note, comprised of 2 pits as indicated in the figure below. The EG can carry out amplitude: modulation using (8-bit) LFA data from the LFO. Maximum tmplitude modulation can be set 2s indicated in Figure 2.15, Rees} a NS EN DIR PMS AMS You can decide whether oF not to modulate a particular slot by using the AMS-EN switch when carring out amplitude modulation. AMS data is set for every channel. 21.8 NOISE: Noise Generator When the NOISE control is on ENABLE, the 32nd slot is changed to the noise siot. The noise OS is controled by the NOISE GENERATOR clock externally and can be changed. Also- the envelope uses the 32nd slot for the envelope function, but at this point transformations are not logarithmic: the attack undergoes exponential change and the decay undergoes straight-line change. NOISE ENABLE NE is available if the (D:) bit is set at “1”, making the 32nd bit slot the noise stot. pixie SO — NE NFRQ © NFRQ: NOISE FREQUENCY “The relation between NFRQ and noise frequency is ou (KHz) = EE) ew = err f soe KHA=-3.QNFRQ) eu=3579.45KHz (YM215I added clock frequency) and can be changed throughout a range of from approximately 3.5 kHz to 1.9 kHz. ‘AL this point the noise period value is wrt T nome (SEC) = 7H) and can range from approximately 37.5 soc to 1-17 see. 2.1.6 LFO: Low Frequency OSC Tne LFO, which can control oscillation waves over a wide speslnity (from approximately 53 MHz to 0.008 Hz), selects one wave form from among ‘several available, providing sound Source frequency modulation and amplitude modulation, ‘At thig point, the output level can be controlled with the signals used for the frequency modulation and amplitude modulation.© LFRQ: LOW FREQUENCY Wh the following 8 bits the oscillation frequency can be set as indicated in Figure 216. Pbpb bbPpy ——— LFRQ « W: WAVE FORM With the following 2 bits 4 different types of frequency ulation can be output. COREE a SSH je | PMD/AMD: PHASE MODULATION DEPTH/AMPLITUDE MODULATION DEPTH. Tech datum is composed of 7 bits, with the data assigned to the firs bit distinguishing between PMD and AMD. The PMD and AMD control the frequency modulation’ amplitude modulation signal output level to a resolution of 1/128. As you may have ‘guessed from the previous section on wave forms, the PMD-.[b|pap od oe Letro reser 21.7 Timer “The Timer actually consists of two different timers: a pre-set 10-bit Timer A and 2 pre-set e-bit Timer B. Both timers can be started and stopped. When there is an overflow, these timers function to insert a flag into the data bus. Also, for Timer A there is a key-on function that ic activated when there is an overflow, At this point itis necessary stop the interrupt, and there is a control for this as well © CLKAL/CLKA2 “As indicated in the following diagram, these art composed of 2 words of 10 bits, With these, Timer A generates an overflow at the indicated period. ipo [o-pfpjpip} > ————— EXEEEXP SN CLRAZ CLKAL [eK MSE 8 NA 649(1024-NA) ‘ou (KH) 1D @w=3579.S45KHz (YM2ISI added clock frequency) Ta (ms) =* CLKB Composed of 8 bits as indicated in the following diagram. With these, Timer B generates an overflow at the indicated period. Pabpbpeby — cLkB 1024#(256-CLKB) ou (KH) co OM=3879.549KH2z (YM2I51 added clock frequency) Ta (ms)= @ LOAD “The start/stop action of timers A and Bis controlled with the 2bits depicted in the following figure. Entering “I” starts the timers, while entering “O” stops them. CeCe ed —— LOAD | Oe pimer 8 start ——* Timer B start @ F RESET These 7 bits reset the flag register contents indicating thatthe timers mentioned previously have generated an overflow (“1 resets). Cee F RESET Le timer A Rag resister reset Timer B flag register reset e IRQEN ane 2 bits enable you to inbibit the flag register indicating that the Timers mentioned previously have generated an overflow. BPC = IRQINH Qu Timer A IRQ EN Timer B IRQ EN° cM Entering “I” in this slot enables you to enter a key-on in all sound source slots when ‘Timer A generates an overflow. een Le timer A Key-on can be givea to all slots of the sound generator, IST: (READ MODE) The 2 bits to be discussed below indicate the status of the flag register. When the IRQ pin terminal reads “0”, one of the 2 flag registers will indicate that the overflow from either ‘Timer A or Timer B and that the level status reads “1” —— IST Le Fimer A FLAG Timer B FLAG 21.8 ACC: Accumulator ‘This functional unit takes the L/R control signal ftom the register, imputs the musical signa! data into either the L sequence or the R sequence, or into both the L and R sequences simul- taneously, and accumulates it. The accumulated L,/R sequence signals are then alternately output to the serial in mantissa 10- bit (including the sine bit) and index 3-bit offset binary format from the LSB, (Refer to Figure 2.17.) LR: LEFT CHANNEL ENABLE’ RIGHT CHANNEL ENABLE This is the control signal for used to divide the 2-bit signal from the OP between the Left and Right sequences of input it t the simultaneous dual accumulator, as indicated in the following figure. pq T 0 RIGHT CH. ENABLE LEFT CH. ENABLE1 Block Diagram Fig. GNOWIN Ja aSION ANN sr 7 oY ud awa OF a (NOD) wn ud At nt wid ot “a a 40 nu] aa Mt oa oun TRENOD VAD ONY wi e WL ax and oud Jawys (NAD ONINLL jaar Ot we WAIL on aH18 15,Fig. 22 Slot Designations [nena mi i a = | Tatar Mae? Care Came 7 nom [Ti sss eT PONE uo THEE DM ST Bw cHNe[rasese7eliasesetelraseseralizaesete [When the NOISE costrol Is wt ut ENABLE] this slot changes « become the eoise slot. Fig. 23 a) Fig. 2.3 b) Address Map (1), WRITE MODE ‘Address Map (2); WRITE MODE Hex MSB Ls Refer to Fig 230) oe eli RL_[_F8_|CONECT| Ke KF aE PMS AMS) ye pti MUL elf oF As DIR AMS-EN bit RR FE Fig. 23 c) Address Map (3); READ MODE PRESET > FE AG RESE:Fig. 24 KEY CODE, KEY FRACTION cnn c aise Bee lye ocr [olrizlatels[olr Diam eps] ap lwalle new [cpp el FiPtaiclalaialc =o. lol] s2ba] a — xr can lo Las — Fig 2.9 PHASE MULTIPLY wos. on [ola ]s]e]s]a] 1s [alo apelalela MULTIPLY. tatstels[al rT [off alieiafishis oxt_vore | peer oo | a.e00 9.500 21 | oLeoe 8.008 oz oreo 2.000 o 5 | ove. 2.000 to | eee 8.000 1 4 | o:ee 2.000 2 | ove 2.200 t 3 [olen 8.000 2 0 | o.eoe 9900 2 1 | o.c00 0.060 22 |olom 2.900 2 5 [oreo 8.000 3 6 Joceoe 9:608, 3 1 [oteco 0.600 32 |o.e00 : 8.000 3 3 [evo eer 0,000 49 fosoce sr 2.000 © t |elee ey 2.000 42 [oleco ise o000 © fetes ase 9.000 so |os000 pa o.c00 3 1 [eine esr 2000 3 2 [diem oot 609 3 3 |olov oss 0.600 so elo. oss e009 $1 [etooo ort O80 & 2 [oes ors 2.000 & 5 |o.c00 Ouest 2.800 3 9 |eLeon oar 2000 7 4 |e.eco ose 2000 7 2 loloce os 2009 > 3 |oleen er 20 ort 9.493 amar o.ess 0.907 Lory Toe? ans Ler aes alasFig. 2.7 DETUNE(2) ona |e] it? en eee O_o beast oe Fig. 1.8 PHASE MODULATION SENSITIVITY PMs = (De pte pets Pet [ep maxiean | @ (as [aw [em [m0 [oie] seen | 0 | Fig 2.9 CONNECTION =(FS) cone Oe HEP cones OTD ee . f° [our out conn GL BO ot con=4 [+ out out con? coN=s Fig 2.10 SELF FEED BACK LEVEL mmole paps iets) eT STC eeeFig 2.11 ATTACK, DECAY TIME In Figure 2.12, the 6 bits of the RATE after they have undergone key scaling are divided in two parts and are thus expressed as the first 4 bits and the last 2 bit and “(90% ~ 10%)” tables express the amount of time it takes for the from 10% and from 90% to 10%. The “(10% ~90%)" level to reach 90% The “(96 dB~0 dB)" and “(0 dB~96 dB)” tables express the amount of time it takes for the level to reach 100% from 0% and from 100% to 0%. ‘These tables assume $a = 3.6 MHz. iOTE: ETI. Hint oe nee DECAY Fir me me 8 ATTIC THe oe es ec TIME oe PARRANRT EN IRIASSERRSBCRSRSRE LE PR ARRESARCRAEERGEAG HER Ditddddcddedguge eear! fiery o + betwryFig. 212 KEY SCALING (*) RATEs that have undergone key scaling have doubled the input rate (R} and added the values listed in the table below (Rss). (#*) AR, DIR, and D2R use the values entered in the register for input rate (R). However, for RR a calculation of double the values entered in the register plus | has been used for the ‘input rate (R). RATE =2*R + Rxs ‘When calculation results yield « value greater than 63, assume all RATEs = 63. R: Input rates Res: The values listed in the following table, found by using the KEY CODE and KS. © However, the KEY CODE used here refers to the KC’ of the last 2 detached bits of a note, as indicated in the following diagram. x Ss o ° 1 ‘ 3 3 ‘ weep B t eb sue nee sooelHz xc ——, bes Bb, OTS —— ot New Figure 2.13 Bits and weighting of the First DECAY LEVEL DIL =— [p-[p.p,1D.) rrr saan] jaa faa] e | 3 © The decay level value of 48 AB will be added if D: through De are ALL “1"=45 dB. Figure 214 Bits and weighting of TOTAL LEVEL R sou —_—_ Puy b.[o[o.[5,[,10,[o. 5 2a) 5] cao B es fal] ale [ise 3 6B OF pw Figure 21S AMPLITUDE MODULATION. wos TRS SENSITIVITY nfs 7 asm ‘AMS |_AM MOD (MAX) ° ° 1 | moossa3 2 | 4s 4B 3 | ssn aoFig 2.16 LOW FREQ. OSC SHLEULERSBRNR TET EAT SEERSGEGRURERE RUSE LESS HEE PERSE RRARERRSE SUSY SIS359933 Fig. 2.17 SO, 1, SHI, SH2: TIMING plelele le ebels[T = LEFT [bel TST RIGHT ECE SH22 Pin Wiring The YM2151 uses a 24-lead dual in-line package. The terminal signals are indicated in the following diagram. Top View om o voor + $v) so su sHz or De ps pe bs pr 2.2.1 Pin Functions © De~Dr: Address/Data Bus (input/output high impedance) ‘A multiplex bus that can be used for both address and data; inputs an 8 between an external device und the internal register. it parallel signal © AO: Address/Data Select (Input) When A0=“0", the Do~ Ds signal is processes as an address signal; when AO= Ds~D: signal is processed as data. ", the @ WR: Write (Input) ‘When there is a write signal, the signals in the bus can be entered. © RD: Read (Input) When there is a read signal, the internal signals can be read out via the bus. © GS: Chip Select (Input) oe When there is a chip select signal, the AO, WR, and RD signais become operative and the De~ D> bus data can be entered in the internal register or internal data can be read out ‘on the Do~ D> bus. TC. Initial clear (Inpur) Internal registers and circuits are initialized when this terminal reads “0”. © FRO: Interrupt request (Output: Open drain) If either of the 2 types of timer counters begins a carry out, this signal will read out a “O" level and request an interrupt from the CPU. Then, with the CPU’s readout of the data, the unit will determine from which timer the interrupt request fias been made and will process the interrupt.CTI, C12: Control 1, Control 2 (Ourput) This is the terminal that is used to control an external device and should read “O" level when at initial condition. SO: Serial Output (Gutput) Takes the tone signal divided between the 2 left and right channels, outputs it as serial data, and sends it to the YM3012 D/A converter specially developed for usc with the YM21 51. SHI, SH2:; Sample and hold Used to pick up the serial data supplied to the YM3012 D/A converter, and for sampling hold after analog conversion. 9M: System clock (Input) Inputs the clock @M that drives the YM2I51, which is intemally broken down to and used at 1/2 the frequency. The $M is the reference for the tone signal $1: Clock for D/A (Output) This clock drives the D/A and operates at the same frequency as the clock inside the YM2ISL, Also, when the ¢1 level shifts from “1” to “0”. the IRQ. CTI. CT2, TO. SHI, SH2, and SO signals all change Voo: Power Supply (Input Normally supplies at + SV. Vss: Grand (Input) Conects the system grand.3. DEVICE SPECIFICATION 3.1 Maximum Ratings Voltage Range -03V ~ + 7V Operating temperature orc ~ + 70°C ‘Storage temperature =50°C ~ +125°C 3.2 Electrical Characteristics [MIN] [TYP] 1) operating supply voltage (Vss to Voo) 475 2) clock [eM] Voltage level “o -03 Voltage level “a 20 Rise time (Fig3-1) Tr Fall time (Fig3-1) TF ON time (Fig.3-1) Tox 100 Frequency Fem 30 3.58 Input capacitance = COM Fig 31 PPHASE DATA [MAX] 5.25 os Vo 40 10 Vv 2s MHz pF3 4) 6) 8) [MIN] [TYP] [MAX] ALL INPUT Voltage level “0" 03 08 Voltage level “1" 20 Voo ALL OUTPUT Voltage level “0" 03 4 Voltage level “1” 24 Voo [A0, WR, RD, ¢M] Input Leak Current (Fig.3-5) b (at 25°C Vi=0-Voo) -10 10 fc, CS} Enput Current ¢Fig.3-6) lig (at Voo=5V) 10 60 (TRQ*, CT1, CT2, DO-D7, SHI, SH2, SO, 1] Load Current (Fig.3-7) In {at Vio=0.4V) I * OPEN DRAIN WRITE/READ TIMING (Fig.3-2a. Fig.3-2b) Address Set-up Time (Tas) 10 Address Hold Time (Tan) 10 CS WRITE WIDTH (Tew) 100 WR WRITE WIDTH (Tws) 100 WRITE DATA Set-up Time (Tos) 50 WRITE DATA Hold Time (Tow) 10 READ DATA Access Time (Tace) 180 READ DATA Hold Time (Town) to ns Rs as ns as[MIN] {TYP} 9) [el] Rise time (Fig.3-3) Trt Fall time (Fig.3-3) Tht Load capacitance CL (Fig.3-7) 10) (TRQ, CTI, CT2, SO, SHI, SH2] Rise time (Fig.3-3) Tr Fall time (Fig.3-3) Tr Load capacitance CL (Fig.3-7) 11) POWER Supply curreat Ino 12) POWER Dispation Pp (st Voo= 5.25V) IMAX] 180, 120 100 250 250 100, 120 630 a5 pF mWFig. 3-28 WRITE TIMING Daw De=Dy NOTE: Tos and Tous use as a reference cither CS or WR, whichever has attained High Level Fig. -2b READ TIMING DATA {Beebo NOTE: Tace uses as a reference cither CS or RD, whichever is the last to attain Low Level _ Tonr uses as a reference either CS or RD, whichever has attained High Level.Fig. 3-4 oureuT iRQ. CTL. CT $0. SH. 52) Fig. +6 Fig. wrut Fig. 3-7 | queen oer iFig. 4.1 SYSTEM BLOCK DIAGRAM opm ¢YM215)) AUDIO AMPLIFIER Fig. 4.2 DAC INTERFACE SAMPLE & poxn-9v * v0 [Jaane Geog, yas Tees]; [mas PATAL, one nf sia] sti” Roa ai = ots 1a] = ro a our C4. Cs 1008F cele Rneivsboer TAC oERR a2 AGNO -1 =v ACH OUTPUT LcnoureT4. INTERFACING Figure 4.1 is a block diagram of the basic configuration of the unit, including the micro- Processor or microcomputer, DA converter, and speakers, in addition to the YM21SI. As it is possible that you may alter the data if you operate this device without synchronizing it with the microprocessor or microcomputer, you can drive the unit by using a separate clock generator to achieve the required sound levels. With the YM2151 and the DAC configurated as shown in Figure 4.2, you can have both left and right, 2-channel output.