1

3) 8er el two active elements dool el homa

el transistors fe passives
zy el poly capacitor w dh two poly layers
w fe benhom dielectric constant 3ali
34an t3mel capacitance
9) Passivation Layer t3zelna 7) deh btkoon thick enough 34an n3mel beh el RF coils b4akl spiral
4) momken t3mel poly resistance mn 3n el environment el btkoon thick 34an tkoon moqawmetha watia w 3alia 34an tkoon b3eda 3n el substrate w
poly layer leha high sheet resistance 34an 7awalena btkoon 8aleban ya2ma oxide bel tali mt3mel4 ay coupling m3 el conducting layer el t7t deh w t3mel eddy currents w
n3rf n3mel moqawmat 3alia fe msa7a 2olyla ya2ma nitride
Passivation mask losses w t2lel el Quality Factor
5) MIM capacitor w dh bykoon el insulator bta3o high K 8) Bnst5dmha 3adatan ya2ma for power supply
w dh very ideal bel nesba lel distribution 34an n2lel el electomigration effect fa
very high frequency (RF) bn3mlha thick enough 34an my7slha4
6) fel low frequency aw el digital momken nktefi overheating
bel poly resistance

2) Deep Junction
el side wall oxide by3ml
Vertical Oxide protection against el ion
implantation 34an n7afez
3la el
shallow junction

1) Shallow Junction
34an tkoon shallow fel depth w bel tali tkoon
shallow fel lateral direction w mt3ml4
overlap kebeer m3 3l Gate

* P-epi is the P-well doping. Difference from the P-substrate doping is needed
for better design of the N-MOS VT.
* Starting from the P-substrate we make P-epi (without mask) then one mask
for N-well.
* Poly2 is replaced by HiResPoly if high resistances are needed.
* M4 is replaced by Thick Metal if RF spirals are needed.

2
 m7tageen fehom deposition by CVD

for Local Interconnects

Trench for sub 90

microns
y3ni abl mn7ot
metallization w lazm ykon
layen w sahl ta4kelo w sahl
n3melo planarization
3n tare2 el CMP f bn3melo
mn el TEOS

p-epi 22l fel doping 3n

el p-substrate 34an
nsahel 3amliet enena
n3ml el n-well

byt3mel thermally
34an ykoon very high
quality w bykoon dry
oxidation
enma el FOX momekn
n3melo bel wet oxidation
34an howa mogarad mada
3azla

Parasitic Inversion (N-parasitic Channel) ka2nena bnwsl el N+ bel n-well bta3et

CVD PVD el transitor el ganbeha fa bnst3ml el channel stopper

P+ substrate is good for reducing latchup. P-epi makes it practical to form the
wells (difficulty to overcompensate P+ doping to form N-well !). This is for
typical digital technology.
el poly layer btt3mel by CVD

3
Only For Mechanical
Support

4
hn7tagha 34an n3mel local oxidation

5
by7sel compression
3ala el sat7 bta3 el silicon
la2n el SiO2 bymn3 tmadod
el Si el ab3ad feh btt3arf b7es enhom y2lelo el stress eli mwgood 3ala el sat7 bta3 el silicon
el Si3N4 lw 7ateto directly
3ala el Si hy3ml expansion
lel sat7

e7na 3ayzeen n3mel

oxidation locally fa lazm minimum stress to avoid cracks
n7ot Si3N4 la2no howa
el hytm est5damo as
mask against el oxidation
34an el Si3N4 la yt2ksd

6
7
Plasma Etching

8
 Doping 34an a3mel N-Well

ion implantation 3ala el sat7 mn 5lal el Oxide 34an nmna3 el channeling dayman lma bnegi n3mel ion implantation lazm
n3melo Through thin oxide layer

initial Oxide Thickness

Phosphorus el atomic
mass bta3to 31

(34an ngeeb Depth mo3ayan)

(cm-2)

9
 4elna el PhotoResist 5alas m4 3ayzeno w ba2a 3andena nitride, w 7eta mafha4 nitride, el 7eta el mafha4 nitride deh n2dar n3mlha oxidation,
fe initial oxide thickness w aroo7 mkamel w hn3mlha by wet oxidation, el nitride el asfar mwgood w 3amel Masking against el oxidation.
lama negi n3mel el Well el 3ala el 4emal hn7ot oxide kebeer nesbeyan 34an ymna3 ay ion implantation eno yi go through it w ywsal lel
N-Well el 3amlnah fel mar7ala el Sabeqa

Haykoon mask lama negi n3mel el P-Well

yb2a keda est5dmna el

N-Well Mask 34an n3mel
el two wells

10
11
 el Boron a5f mn el phosphorus fa by penetrate aktar 4wia

Energy 22l mn
el est5mnaha fel
N-Well Implant 34an el boron
a5f fa 34an nwsal li nafs el depth

lessa hn3mel annealing

34an n3ml activation
lel impurities w 34an
n suppress el defects
el natga mn el impacts

keda 2derna n3mel el two wells b mask wa7ed

12
 Drive-in howa el Annealing

Ana 3ayz well 3ameeq 34an 22dar abni gowah el 2tneen transistors bto3i
W el well yo3tbr noo3 mn el 3azl bel nesba lel substrate la2n deh kolha btkoon reverse biased junctions
3ala el 22l el N-Well over el P-substrate hatkonn reverse biased junction
el P over P m4 junction enma N over P deh junction w btkoon reverse biased

13
4elna kol el Oxide mn 3ala el sat7
w ban 3andena en fe Step mwgoda la2n el N-Well nazla ta7t 4wia

14
7atena tani pad oxide 500 Angstroms 34an nawi a3mel local oxidatio
w tabe3i ntwk3 enena hn7ot nitride

15
 7atena Nitride by CVD bel thickness el monaseb 34an
7war el stress dh

Kan momken n3mel el pad oxide dh by thermal oxidation la2n el silicon bayen w lessa mwgood,
e7na m4 m7tageen el high quality la2n lessa el gate mt3ml4 fa 8aleban bn3mel el pad oxide bel CVD w warah 3alatool
el Si3N4 bel thicknesses el monasba

16
hena mask no.2 el hn3ml beh el Field Oxide, hayegi fel nos 34an ye3zel transistor el 4emal 3n el ymeen w fe LOCOS bardo 3ala el ymeen 5ales w
el 4emal 5ales hy7sal 34an n3zel el goz2 el ganbo w n7ot feh el Bulk Tie (Bulk Connection)

17
18
Howa nafs el N-Well mask m4 m7tageen wa7d tani

19
Dh P+ doping (doping 3ali) gowa el P-Well lw fe ay conducting layer b voltage 3ali haykoon sa3b enena ni invert el stopper w y7sal parasitic channel (n-type) w twslni m3
el N-well w deh 7aga 8er mar8oob feha akeed

Lw kan el well nafso light highly doped kan momken nst8na 3n el 5atwa deh

20
 4elna el photoresist w 3amlna Local Oxidation (7asal fel 7etat el mafee4 3aleha nitride deh), el 4akl hytqrar 4emal w
ymeen 3ala el different P and N wells, el sat7 mafhoo4 8er N and P wells

T7t el oxide ba2a fe Channel Stopper (highly doped), keda lw fe ay conducting material 3aleha voltage 3ali(+ve hena ka example
momken y3mel inversion w ygeeb electrons twsal el N-well bel parasitic channel el et3mlt

El Bird Bec dh bykoon nategt el lateral oxidation bykoon 3amel zy mosls keda

m3ml4 channel stopper na7yet el N-Well la2no eftrad en el N-well doping 3ali kfaia 34an lw fe ay voltage negative kebeer hyb2a mn
el sa3b enena n3mel inversion t7teeh 34an el doping 3ali

21
 Hn3mel transistor hena

Hn3mel transistor hena

Bulk Contact
34an nwsal el
Wells
N-Channel b potential sabet
(NMOS) transistor P-Channel e7na 3awzeno
(PMOS) Transistor

22
el dry hyb2a t7t el Wet, la2n bn7ot el oxygen w b3deen by7sal diffusion mn 5lal el SiO2 el Wet dh l8ayet ma bnwsal l sat7 el silicon w lma nwslha
bn3ml el new layer mn el SiO2 el heya el Dry w ndefa nesbeyan w y7afez 3ala el interface el ben el sacrificial oxide dh w been el silicon

7atena tani SiO2 dh oxide 7ato 34an a3mel mn 5alalo Ion Implantation 34an
n combat mwadoo3 3l channeling

nedeef

The final 100 A dry oxidation improves the oxide/silicon interface

properties…

23
Fine Tuning lel Threshold Voltage
el FOX hy act ka protection against el Doping
w m4 hy7sal Channeling 34an fe 3andi Sacrificial Oxide mwgood

P-type dopants

24
hn7mi el 3amlnah fel 5atwa el fatet 3n tare2 el Photoresist el 3ala el 4emal dh w n adjust tani el threshold voltage
bta3 el PMOS transistor

Dh Bardo Mask moqarar howa nafso bta3 el N-well

p-Channel MOSFET

25
 bn7awel ni adjust el Vthreshold bta3 el PMOS w el NMOS enhom ykono 2d b3d
el PMOS keda el Vth adjustment bta3o et3ml 3ala two steps la2nena 3amlna doping b boron mara tania zyada

n-Channel MOSFET p-Channel MOSFET

- E7na 3azyeen el Vthn w el Vthp ykono bqdr el emkan equal, el gate oxide el bn7oto fe 5atwa (25) bykon feh +ve Charge
w deh mn a7d 3yoob el oxidation eno bykoon feh excessive +ve oxide charges swa2 nategt 3adm el oxidation el kamel gowa el SiO2 3and el sat7
aw nateget wgood sodium wla whatever.
- El +ve oxide charges deh ht3mel eh ? ht3mel induction li negative charges 3and el channel swa2 fel NMOS wla el PMOS
- Fa keda fel NMOS el 3ala el 4emal dh ht2lel el threshold voltage w el PMOS el 3ala el ymeen bel nsbalo el Vth hyzeed la2n el -ve induced
charges ht compensate 4wia el holes el 3ayzen n7otha t7t el TOX el htkwnli el Channel
- lama 3amlna doping bel Boron keda dh hyzwd el Vth bta3 el NMOS la2no keda 2lel el minority el fel P-well w ba2a takween el channel as3ab wi
bel nesba lel PMOS el Vth keda hy2el la2n el minority el m7tageen negbha
3ala el sat7 34an n3mel inversion zadet ( el majority 2alet bta3et el N-Well)

Note that with blanket implant we use only one masking step to adjust VT for
the two transistors.
The adjust implant of B+ in the N-Well should not of course invert the well
doping. The background doping of the NMOS is slightly increased and that of
the PMOS is slightly decreased.
Notice that the gate oxide usually incorporate some +ve charge that will
induce –ve charge in bulks shifting VT of both PMOS and NMOS negatively.
The implanted acceptors (+ve charge) should compensate the oxide charge and
allow to equate both thresholds.

26
The sacrificial oxide (also called Kooi oxide) helps in preventing channeling
of the VT adjust implanted ions.

27
 Dh keda el gate oxide w bykoon 15 nm w bykoon High Quality w bn3melo Dry

- E7na 3azyeen el Vthn w el Vthp ykono bqdr el emkan equal, el gate oxide el bn7oto fe 5atwa (25)
bykon feh +ve Charge
w deh mn a7d 3yoob el oxidation eno bykoon feh excessive +ve oxide charges swa2 nategt 3adm el
oxidation el kamel gowa el SiO2 3and el sat7 aw nateget wgood sodium wla whatever.
- El +ve oxide charges deh ht3mel eh ? ht3mel induction li negative charges 3and el channel swa2 fel
NMOS wla el PMOS
- Fa keda fel NMOS el 3ala el 4emal dh ht2lel el threshold voltage w el PMOS el 3ala el ymeen bel
nsbalo el Vth hyzeed la2n el -ve induced charges ht compensate 4wia el holes el 3ayzen n7otha t7t el
TOX el htkwnli el Channel
- lama 3amlna doping bel Boron keda dh hyzwd el Vth bta3 el NMOS la2no keda 2lel el minority el fel
P-well w ba2a takween el channel as3ab wi bel nesba lel PMOS el Vth keda hy2el la2n el minority el
m7tageen negbha
3ala el sat7 34an n3mel inversion zadet ( el majority 2alet bta3et el N-Well)

28
 Poly Deposition 3ala el sat7 bel Kamel
el poly hyt3mlop doping marteen mara dlw2ti w mara w e7na bn3mel doping lel Drain w el Source

The drawing is not to scale, the poly to gate oxide thicknesses are 600 nm / 15
nm

29
 hnraseb tab2a mn el SiO2 feha Phosphorus w nsa5an l7d 1000 darga fe gaw 5amel mn el nitrogen
fa el phosphorus hy diffuse w bysmoha solid state diffusion 34an diffusion mn solid l solid w dh yo3tbr initial
doping lel Poly

zy el photoresist
w bykon
mo3alaq feha el
impurities deh

In-situ doping or gaseous-doping are also possible. No need for the expensive
ion-implantation doping (no directivity),

30
31
32
Accurate

33
34
 Ohmic
Contact

34an n fix
el potential bta3
n-Channel MOSFET el N-Well

35
 el 7etat el exposed 3amlnalha doping b phosphorus, bn3mel el junction shallow la2n lw nezel l ta7t deeply kan hyd5ol bel 3ard kteer w kan hy3ml Overlap
capacitance kebera been el gate w been el drain/source w y2lel el high frequency performance bta3 el transistor 34an keda howa 3amel el junction very shallow
34an ni minimize el overlap

Shallow

Shallow Junction to Reduce Overlap Capacitance

mkn4 ynf3 n3tmd 3ala el Shallow junction deh nkamel el steps 3aleha w n7ot contact lel drain w contact lel source, la2n sa3etha hykon 3andena moqawma 3alia
in series m3 el channel 34an keda bn7ot deep drain w deep source b3d keda 34an ngeeb moqawma watia lel drain w el source el bnsmeha el access resistance
el heya el resistance el hnwsal beha lel channel

36
37
Momken nst5dm PR 3aks el fat w bkeda n2dr nst5m nafs el Mask bta3 el N-Select

38
 boron 34an yb2a P 34an hn3mel el P channel transistor bs shallow, w fe P el 3ala el 4emal dh 34an n3mel ohmic contact m3 el P-well

Ohmic Contact

39
40
 hena hn3ml el sidewalls w deh mohema 34an ne7mi el Shallow Junction deh, la2n lessa hn3mel el deep junctions bs m4 3ayzeen n2sar 3ala el sh
el 3amlnaha fa hn3ml 7aga ti protect el shallow junction, el 7aga deh m4 mask enma oxide, oxide protection lel shallow junction, fa hnst5dm Oxid
oxide conformal y3ni ma4ya m3 el topology bta3 el sat7 bdoon m4akel y3ni maslan 3alia fo2 el gate w
watia foo2 el junction w hakaza w bn3mlha bel CVD 3n taree2 gas esmo TEOS w mn el Sahl eni a3melo CMP

Han4eel ay 7aga
horizontal

Nitrides have higher k than oxides. This means the nitride structure is more
compact than oxide.
Consequently it has a slower etch rate (easier to control).

41
 El Spacer foo2 el Shallow Junction, fa keda lw 3amlna ion implantation tani dlw2ti, m4 hy2dr y3di mn el sidewall (spacer)
hn7tfz bel implant el t7t el space shallow zy ma7na 3ayzeen la2n howa dh el mas2ool 3n el overlap enma el goz2 el mafee
spacer deh htb2a Deep Junction w htb2a highly doped 3aks el shallow juntion eli btb2a Lightly Doped Drain (LDD)

(sidewall)

42
hnst5dm nafs el Mask tani el 3mlna beeh el shallow junction, hn3ml beeh el deep junction, la2n el far2 ben el 2 masks ba2a mawgood 3n taree3 el
sidewall (Spacer) el 3mlnah m4 3n taree2 enena n3mel Mask m5soos

bnbda2 bel N doping 34an bykoon b Arsenic aw Phosphorus w bykoon at2al 4wia mn el Boron w lma b3melo howa el 2wl
b3dha a3mel el P m4 byt2sr kteer enma el P byt3ml b Boron w el Boron 5afeef fa lw 3aksna hy7sl drive-in

43
 Doping 3ali, Dose a3la y3ni 3omq akbar, w el doping el 3ali m3naha dose kebera m3naha low resistivity, fa lw 7atena fo2eha contact el
current hym4i fe 7eta low resistivity tawel w ba3dha 7eta so8yra aw high resistivity el heya bta3et el Shallow jucntion bs heya 4ar labod
menoh 34an el overlap

Note how the side wall oxide protects the LDD region.
The deep D/S edge is aligned with the sidewall oxide.

Doping 3ali w Dose kebera fa y2dr ygeeb low resistivity

44
45
46
 Boron 34an hn3mel el PMOS, b dose a3la bardo 34an n3mel el Deep Junction, keda el transistor ta2reban 5eles, ba2a 3andi el
junction el 3ameqa w el junction el Shallow w el gate bta3na w t7to el OXide w 2ela 2a5ero

Note that the KeV for the shallow and deep implants are equal. The difference
is only in the dose.
The junction depth difference comes from the difference in straggle rather than
projected range. Larger straggle leads to larger Xj.

47
48
- El oxide el kona 7atena kan 7assal mn 5elalo ion implantation el goz2 el wa7eed el m7sl4 through it ion implantation howa el ta7t el gate, han4eel kol el 7assal mn 5elalhom
ion implantation 34an howa damaged w ba3dha hn3mel Salicidation, el Salicidation by7tag en el Silicon ykoon mwgood (exposed) fa howa 4al bardo el damaged oxide 34an
yb2a el Silicon exposed, w el polysilicon 3eryan bardo w mawgood, fa y2dar dlw2ti y3mel el titanium bta3o w y3mel Rapid Thermal Annealing w yb2a fe silicide foo2 el D/S w
foo2 el Gate w el spacer hymna3 ay short circuit been el gate w el Drain aw el gate w el Source
- El oxide m4 hy7sal fo2o salicidation hy7sal faqat foo2 el Silicon el exposed w el Polysilicon

The sacrificial oxide is etched. It was used only to avoid channeling.

49
El Salicidation by7tag en el Silicon ykoon mwgood

50
 Alloying w byntog 3ano good contact w by2ll el moqawma

Salicidated transistor is now terminated.

Only contact plugs are ramaining.

51
Deh Awl Dielectric Layer 2bl el el metal number 1

52
Contact foo2 kol drain w source w fo2 el 2 bulk ties
el gate contact byt3ml 5areg el Active Area

53
This slide shows how the CC printing is done on different heights. This
exhibits non-focused imaging where the cut perimeter will be flu.

54
hn3mel Etching 34an nwsal lel atraf bta3et el Contacts

55
 El Shallow Junction m7sl4 fo2ha Salicidation la2nha ma7mia bel Spacer

The difference in the gray level of SW oxide and FOX is bcause of different
dielectrics.
The FOX is oxide and SW is nitride.

56
hn7ot el Tungsten Plug b chemical vapour growth
el W bey overflow w b3dha bn3ml CMP

57
58
59
This is non-Cu technology.

60
Under M1 we see the FOX over which the 1st isolation is deposited (mauve).
Some times
both oxides are termed FOX. This is the level we reached in the previous
slides.
Over M1 we have to deposit the 1st IMD (1st planarizing dielectric) , M2,
IMD2…etc

61
1) Field Oxide 4) Poly Gate 5) Shallow Junction 6) Sidewall(Spacer) 7) Deep junction

Deep Junction btkoon

low resistance
w el Shallow Junction
btkoon High resistance
el Contact btkon 3and el
Deep Junction

BE color differences means that the metallization layers and vias are not made
of Cu.

62
 Stackable y3ni momken t7ot el contact foo2 el Via

El nitride leeh Dielectric Constant akbar mn el oxide yb2a el Dielectic

constant el 3ali dh gai mn el compactness el 3alia bta3et el atoms aw el
molecules y3ni el Si3N4 more comapact 3n el SiO2 34an keda el Dielectric
constant bta3o a3la

- Sa3at bykoon fe transistors high voltage fa 34an keda fe qemteen lel supply
- el Latch Up howa short circuit ben el supply w el ground

63