ISSN 2322-0929

Vol.04, Issue.07,
July-2016,
Pages:0533-0535

www.ijvdcs.org
Design of an I2C Master Interfacing with APB Bus
PARIKI MANASA1, B. PADMINI2, S. NAGI REDDY3
1
PG Scholar, Dept of ECE, TKREC, Meerpet, Hyderabad, TS, India, E-mail: [email protected].
2
Assistant Professor, Dept of ECE, TKREC, Meerpet, Hyderabad, TS, India.
3
HOD, Dept of ECE, TKREC, Meerpet, Hyderabad, TS, India.

Abstract: All design units consist of smaller functional blocks called subsystem or module. For effective functioning of the system
these modules need to be in sync with each other and share resources. Problem starts when one module follows different protocol as
others and each module has its different bit rate or baud rate of data transfer which can be either asynchronous or synchronous. The
paper takes an example of I2C protocol and AMBA APB protocol to describe the architecture which defines how data are transferred
from one protocol to another. It exploits the flexible protocols of I2C to make it compatible with APB protocol. The proposed
architecture is a bridge between I2C Master and APB Salve. The data travels from a serial bus (I2C) to parallel bus (APB) to serial
(I2C) in sync with the respective domain clock. This forms a bidirectional interface between I2C supported module and APB
supported module.

Keywords: SCL, SDA, PSELx, PENABLE, Xilinx ISE.

I. INTRODUCTION SETUP state, where the select signal, PSELx, is asserted. The
I2C is a 2-wire, SDA and SCL, bus developed with the basic bus remains here for one clock cycle and moves to the
idea of connecting different ICs and application specific ENABLE state on the next rising edge of the clock. ENABLE.
modules with processors on a common communication network. The enable signal, PENABLE, is asserted. The address, write
I2C is a multi-master bus and the peripheral devices are and select signals have to remain stable during the transition
addressed by unique programmable address. By sampling the from the SETUP to ENABLE state. If no further transfers are
SDA above Nyquist rate I2C can communicate with any device. required the bus returns to the IDLE state.
On the other hand APB is a low bandwidth bus with reduced
interface complexity. APB has dedicated programmable control
registers to access peripherals devices. Like I2C, APB
compatible devices are easily incorporated in any design flow.

A. I2C Protocol
I2C bus runs on simple master-slave relationship. All trans-
actions begin with detection of START condition and are
terminated by encountering STOP condition. As soon as start
condition arises bus is considered to be busy and it will re-main
in the same state till all requests for the bus have been granted.
For the read/write operation, first the slave’s address is sent
followed by the corresponding data, as shown in fig.1. ACK
signal is sent after successful transfer of each data byte. For
Fig.2. State diagram for write operation on APB.
interrupted transmission NACK signal is raised.
Alternatively, if another transfer is to be made then the bus
will move to SETUP. Address, write and select signals can
glitch during transition. Rest of the paper is divided in five
sections. Section II illustrates the motivation behind the work.
Section III is the core of the paper and gives details about
designed and hence implemented architecture which is
Fig.1. 12c Data Transfer protocol. essentially a bridge be-tweenI2C protocols to APB Protocols.
The section describes functionality of the system. SectionIV
B. APB Write Protocol addresses the limitations that are encountered while operating
Fig. 2 explains the write cycle as- IDLE: The default state. the system and may need attention. Following the limitations is
SETUP: When transfer is required the bus moves into the the section V of future work which is framed considering who

Copyright @ 2016 IJVDCS. All rights reserved.

 PARIKI MANASA, B. PADMINI, S. NAGI REDDY
these limitations could be resolved and also further development  APB Salve will send a signal to APB Master telling that the
in the design. Section VI gives the simulation results from data are available to be read.
Xilinx ISE 14.2 Simulator. The last section, section VII is the  APB Salve then transmit the data to APB Master where it is
concluding part. stored in the internal memory to be fetched by I2C Slave at
II. RELATED WORK time point of time.
I2C bus was developed to reduce congestion, area and power
consumption by microcontroller when multiple devices were IV. LIMITATIONS
needed to be attached to it. Owing to increasing demand of the  By the design I2C operating frequency is much greater than
high-speed high-performance system microcontroller ran on designed APB master clock frequency. I2C can overwrite
parallel buses. This triggered the need to interface serial buses the same address multiple times. In this scenario, designed
with parallel buses. Created a common architecture for I2C and APB master block sends the updated data only and data
SPI interface with APB AMBA bus thereby reducing the chip transfer rate limits by the operating frequency of the
area. PCA9564 bus controller is a generic interface between I2C designed APB master.
and SMBus with standard 8-bit parallel buses. Shows AHB  Designed APB master does not send the address specified
communicating with SPI Master.And connected host compliant by the I2C. It sends only data from the internal memory to
with AMBA protocol to I2C bus via APB protocol. the fixed addresses. This internal memory updates through
the I2C any time.
III. DESIGNED ARCHITECTURE  When I2C writes the 4 successive data in the internal
Architectural block diagram of the implemented memory of designed APB master then only designed APB
communication bridge between I2C and APB is shown in Fig. 3 master writing operation initiates. Data flows from the I2C
This design is an Intellectual Property (IP) core of AHB to APB and from APB to I2C.
(Advanced extensible high performance bus) to APB(Advanced  I2C bus will hang even if the single device on the bus stops
Peripheral Bus) Bridge, which translates the AHB transactions operating. The operation can be restored by cycling the
into APB transactions. The bridge provides interfaces between power to the bus.
the high-performance AHB bus and low-power APB domain
and Transactions than fed to I2C .I2c controller is used to V. FUTURE WORK
control the master and slave of I2C bus. As proposed care has been taken to match data transfer speed
of both the buses for better compliance. We intend to design a
model with added buffers at the interface to get even higher
speed of data transfer Latency and chances of losing data can be
decreased by-
 Increasing the buffer length at the interface of designed
APB master. Keeping the operating frequencies of designed
APB master compatible with I2C. The other ways to
perform Reading Operations-
 Time Based: APB reads in a particular time interval which
is defined by user. APB reads the data at the address of
Fig 3. Architectural block diagram. interfaced module and updates all register in its internal
memory.
A. Write Operation
 Making I2C initiate read operation in APB. VI.
 Whenever I2C Master needs to communicate with APB
Slave it would be done via I2C Slave. VI. RESULT
 I2C Slave will assert Data Valid and Address Valid Fig4 shows input data to the I2C bus is being replicated at the
signals. output slave device, meeting all the protocols and constraints. In
 Seeing these signal high, designed APB Master polls the this data changes in-between high edges of clock. Data transfer
memory for its availability and starts APB write state takes place between start and stop. Start condition is depicted by
machine. a high to low transition on the SDA line while SCL is high
 I2C sends four chunks of 8-bit data serially to be written whereas Stop condition is marked by low to high transition on
on APB Memory at four consecutive addresses. the SDA line while SCL is high. When Start condition is
 After transfer of each byte APB Master keeps a check on matched with the following data transfer protocol - Start bit,
count whether all four memory locations are updated Device address, R/W bit(0), Acknowledge, Register Address,
successfully. Acknowledge, Data, Acknowledge, Data (Auto Increment),
 As soon as the data at APB Master is updated it transfers Acknowledge, Data (Auto Increment), Acknowledge,…….,
the same 32-bit data to APB Slave. Stop bit - I2C sends four chunks of 8 bit data serially to be
written on APB memory block at four consecutive address.
B. Read Operation APB master keeps a check on count whether all four memory
 Here again when I2C need to read data from the APB locations are updated successfully. As soon as the data at APB
Slave, communication will take place via APB Master to Master is updated it transfers the same 32-bit data to APB Slave
I2C Salve to I2C master. as shown in the fig.5.
International Journal of VLSI System Design and Communication Systems
Volume.04, IssueNo.07, July-2016, Pages: 0533-0535
 Design of an I2C Master Interfacing with APB Bus
[6] UM10204, I2C-bus specification and user manual, Rev. 4 —
13 February 2012, NXP Semiconductors.
[7] AMBA® APB Protocol Specification, Version: 2.0, 13 April
2010, issue C, http://www.arm.com.
[8] D.B.Rane, Ahmed Mustafa M. I. Shaikh, Devanand
Mahajan, Mehdi Ali, ‖Priority Based I2C Bus Controller‖
(IJCTEE) Volume 3, Special Issue, March-April 2013.
[9] Bacciarelli, L. Lucia, G. ; Saponara, S. ; Fanucci, L. ; Forliti,
M.,―Design,testing and prototyping of a software programmable
I2C/SPI IP on AMBA bus‖ , IEEE Research in Microelectronics
and Electronics 2006, Ph. D.
[10] ―NXP I2C-bus and SMBus controller PCA9564‖,
www.nxp.com.
[11] Chetan Sharma, Abhishek Godara, ―AHB interface with
SPI master by using verilog‖, International Journal of Advances
Fig.4. Data transfer AHB to I2C Top module.
in Engineering Research, 2011, Vol. No. 2, Issue No. VI,
December. [12] Product brochure, ―National Semiconductor
I2C Interface‖, www.ipextreme.com.
[13] ―DB-I2C-M-APB-DS-V1.1‖, APB Bus I2C Master
Controller, Digital Blocks, Inc., September

Fig.5. Data transfer from AHB to I2C Top module.

VII. CONCLUSION
The implemented communication bridge between I2C and
APB was designed and implemented in Xilinx ISE 14.2, Vertex
6, using Verilog HDL. I2C Bus was successfully designed
according to the standards given by NXP Semiconductors. A
working communication model was set up between I2C
protocol and APB protocol. Data flow from I2C master to I2C
slave to APB master to APB Slave is shown while describing
the architecture. Simulation results are verified and data transfer
from I2C master to APB slave can be clearly seen in provided
simulation results. As proposed care has been taken to match
data transfer speed of both the buses for better compliance. We
intend to design a model with added buffers at the interface to
get even higher speed of data transfer.

VIII. REFERENCES
[1]Enhanced Universal Serial Communication Interface(eUSCI)
– I2C Mode, SLAU425B–August 2012–Revised February 2013,
Texas Instruments Incorporated.
[2] M. Alassir, J. Denoulet, O. Romain & P. Garda ―A SystemC
AMS Model of an I2C Bus Controller‖, IEEE.
[3] J. J Patel, B.H. Soni, ―Design and Implementation of I2C
Bus Controller Using Verilog‖ ISSN: 0975 – 6779| NOV 12 TO
OCT 13 | VOLUME – 02, ISSUE - 02
[4] Philips Semiconductors: PCF 8584, I2C bus controller
datasheet,http://www.semiconductors.philips.com/acrobat/datas
heets/PCF8584_4.
[5] Samir Palnitkar, Verilog HDL, second Edition.
International Journal of VLSI System Design and Communication Systems
Volume.04, IssueNo.07, July-2016, Pages: 0533-0535