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Testing of Radiation Hardened Transistors: Made in Jazz 0.18μm process

This document provides information to test engineers on testing radiation hardened transistors and sample test circuits laid out in a 0.18μm process. It describes the various test structures including transistor arrays, ring oscillators, a flip-flop, and transmission gates. Details are given on the pin connections and descriptions of the different test circuits, including power connections, the ring oscillators which use different sized nmos transistors, transistor test structures, a bipolar test structure, and the pin connections for a D flip-flop and transmission gates.

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36 views7 pages

Testing of Radiation Hardened Transistors: Made in Jazz 0.18μm process

This document provides information to test engineers on testing radiation hardened transistors and sample test circuits laid out in a 0.18μm process. It describes the various test structures including transistor arrays, ring oscillators, a flip-flop, and transmission gates. Details are given on the pin connections and descriptions of the different test circuits, including power connections, the ring oscillators which use different sized nmos transistors, transistor test structures, a bipolar test structure, and the pin connections for a D flip-flop and transmission gates.

Uploaded by

whosthishere
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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2011

Testing of Radiation Hardened Transistors


Made in Jazz 0.18m process
The tape-out features radiation hardened transistors and also some sample test circuit structures laid out for ready performance assessment and in comparison to conventional transistors. Goal of this documentation is to help test engineer understand what pins need to be probed or powered for successful testing of each of these test circuits. Circuits: transistor arrays, ring oscillators, a flip-flop and some transmission gates.

Vedhas Sadanand Pandit Email: [email protected] 6/21/2011

Table of Contents
Tapeout overview .............................................................3 Pin-number to pin-name correspondence .......................4 Circuit descriptions and pin connections ..........................4 Power connections ....................................................4 Ring oscillators ...........................................................4 Transistor Test Structures ..........................................6 Bipolar Test Structure ................................................7 D flip flop ...................................................................7 Transmission gates ....................................................7

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Tapeout overview (with pin-numbers annotated):

25 26 27 28 29 30

31 32 33 34 35 36

19 20 21 22 23 24

37 38 39 40 41 42

13 14 15 16 17 18

43 44 45 46 47 48

7 1

8 2

9 3

10 11 12 4 5 6

49 50 51 52 53 54

55 56 57 58 59 60 61 62 63 64 65 66

67 68 69 70 71 72

73 74 75 76 77 78

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Pin-number to pin-name correspondence:


1 dsub 2 7 Out1SN 8 13 GLN 14 19 GSN 20 25 GSR 26 31 GLR 32 37 GP 38 43 Emitter1 44 49 qb 50 55 A2p5 56 61 A1 62 67 A3E 68 73 A3 74 dgnd Out1LN DLN1 DSN1 DSR1 DLR1 DP1 Base1 q B2p5 B1 B3E B3 3 9 15 21 27 33 39 45 51 57 63 69 75 dvdd Out2SR DLN2 DSN2 DSR2 DLR2 DP2 pre N A2 Ap5 A2p5E A1p5E 4 10 16 22 28 34 40 46 52 58 64 70 76 dvnw Out2LR DLN3 DSN3 DSR3 DLR3 DP3 d P B2 Bp5 B2p5E B1p5E 5 11 17 23 29 35 41 47 53 59 65 71 77 Out1LR Out2SN DLN4 DSN4 DSR4 DLR4 Base2 clr A4 A1p5 B4E A2E A1E 6 12 18 24 30 36 42 48 54 60 66 72 78 Out1SR Out2LN DLN5 DSN5 DSR5 DLR5 Emitter2 clk B4 B1p5 A4E B2E B1E

Circuit descriptions and pin connections: Power connections (4 pins):


dsub: Sets the substrate voltage. Body tie for all nmos, common collector of all bipolars. dgnd: Ground connection. Sources of nmoss in ring oscillators are shorted to this pin. dvdd: Vdd connection. Sources of pmoss in ring oscillators are shorted to this pin. dvnw: Sets the nwell voltage. Body tie for all pmos in the circuit.

Ring oscillators (2 x 4 = 8 output pins):


There are four ring oscillators in the circuit. Each of the ring oscillators has 577 inverter stages, followed by an output buffer in order to avoid possible loading of the oscillator circuit. Every output stage buffer is made of two inverters, and the inverters are identical to the ones used in preceding ring oscillator circuit. Output for the oscillator part alone is given to the pin with a name that is prefixed with Out1 while output from the buffer stage is given to the pin with a name prefixed with Out2. Suffixes in the name denote type of ring oscillator: L/S for indicating whether a large (L) or small (S) nmos is used, N/R to indicate whether Radiation hardened (N) or Regular (R) nmos is used.

Out2xx Out1xx

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Therefore, we have:

Out2LN Out1LN

and nmos is radiation hardened nmos, having two fingers each 10m wide.

Out2SN Out1SN

and nmos is radiation hardened nmos, having two fingers each 0.5m wide.

Out2LR Out1LR

and nmos in use is regular ca18 library nmos, having two fingers each 10m wide.

Out2SR Out1SR

and nmos in use is regular ca18 library nmos, having two fingers each 0.5m wide. For all these circuits, pmos have six 5m-wide fingers.

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Transistor Test Structures (6 x 4 + 4 x 1 = 28 pins):


There are 5 arrays of transistor test structures. Four of these correspond to each of the four nmos used in ring oscillator circuits and remaining one corresponds to pmos in use common to all the ring oscillators. For every test structure array, gates have been shorted together and are provided as a connection to a pin (pin name Gxx) with separate drain connections (Dxxn). Nmos arrays consist of 5 transistors each, while pmos array consists of 3 transistors. Sources and bodies of all these transistors are connected to appropriate power pins (pmos sources to dvdd, pmos body to dvnw, nmos sources to dgnd, and substrate to dsub). Therefore, we have:
GLN DLN1 DLN2 DLN3 DLN4 DLN5

Radiation hardened nmos, having two fingers, each 10m wide

GSN DSN1 DSN2 DSN3 DSN4 DSN5

Radiation hardened nmos having two fingers, each 0.5m wide

GLR DLR1 DLR2 DLR3 DLR4 DLR5

Regular ca18 library nmos having two fingers, each 10m wide

GSR DSR1 DSR2 DSR3 DSR4 DSR5

Regular ca18 library nmos having two fingers, each 0.5m wide

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Regular ca18 library pmos, six fingers each 5m wide


DP1 DP2 DP3 GP

Bipolar Test Structure (4 x 1 = 4 pins):


Following schematic has been laid out with pin-names as noted. The common collector terminal is connected to dsub pin.
Emitter1 Base1 Emitter2 Base2

dsub

D flip flop (6 x 1 = 6 pins):


Input pin d clk pre clr q qb Description D Input Clock input Pre-charge input Clear input Q output Qb output

Transmission gates (2 + 2 x 13 = 28 pins):


Transmission gates have pin-name correspondence as shown in the adjoining figure. N & P pins have been shorted for all the tgates. The size parameter indicates width of nmos finger. Because each of the Radiation hardened nmos uses 2 fingers, width of nmos =2 x size x 100 m. Presence/absence of letter E indicates whether or not enclosed (radiation hardened) pmos is used for the corresponding tgate. All the transistors have gate length = 180nm.
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