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SCAN INSERTION ASSIGNMENT 1

1. Explain full scan and partition scan?

▪ Full scan Methodology:

All sequential cells replaced by corresponding scan counter parts. Sequential cells not
scanned are black box cells. Combinatorial ATPG Algorithm can be used. Non-scanned cells are
tested by sequential ATPG Algorithm.

▪ Partition scan Methodology:

The full design is divided into parts and then the scan process is done. For complex
design we use partition scan for minimizing timing consumption.

2. Why do designs require scan insertion?

The goal of scan design is to make a difficult-to-test sequential circuit behave (during the
Testing process) like an easier-to-test combinational circuit.

Achieving this goal involves replacing sequential elements with scannable sequential and
followed by that we observe controllability and observability.

Controllability: Controls over the each node (Shift mode)

Observability: Response of the each node (Capture mode)

3. Explain the different types of scan with diagrams?

Scan circuitry facilitates test generation and can reduce external tester usage. There are two main
types of scan circuitry:

▪ Internal scan : Internal scan is the internal modification of your design’s circuitry to
increase its testability. Only two states Shift & Capture depending on SCAN ENABLE
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▪ Boundary scan : Boundary scan adds scan circuitry around the periphery of the design
to make internal circuitry on a chip accessible via a standard board interface. The added circuitry
enhances board testability of the chip, the chip I/O pads, and the interconnections of the chip to
other board circuitry

4. Explain the inputs needed for carrying out scan insertion for a design?

Netlist: Design data (Gate level Verilog)

Do-files: The commands needed for the tool information about circuit and how to insert test
structures. one can issue these commands interactively in the tool for placing them in do file.
Same of t

Library files: The design library contains description of all cells the design uses. Library also
includes information that the tool uses to map non scan cells to scan cells and to select
components for added test logics circuitry. the tool uses the library to translate the design data
into a flat, gate level simulation model on which it runs its internal process.

Test procedure files: this files the stimulus for shifting scan data through the defined scan
chains. This input is only necessary on designs containing pre-existing scan circuitry or requiring
test setup patterns.
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5. What is scan chain balancing and what is the need of it?

In general, a scan chain is formed out of scan cells belonging to a single clock domain.
For clock domains that contain a large number of scan cells, several scan chains are constructed,
and a scan-chain balancing operation is performed on the clock domain to reduce the maximum
scan-chain length

Scan chains are balanced for avoiding extra post shift bits Scan chain is a technique used
for design for testing. Scan chains are the elements in scan-based designs that are used to shift-in
and shift-out test data. A scan chain is formed by a number of flops connected back to back in a
chain with the output of one flop connected to another. The input of first flop is connected to the
input pin of the chip (called scan-in) from where scan data is fed. The output of the last flop is
connected to the output pin of the chip (called scan-out) which is used to take the shifted data
out. Test time will be minimized if chains are balanced.

If the all scan chains in the blocks contains equal num of flops then it is known as scan
chain balancing. If scan chain contains different num of flops the chain containing less flops has
to wait for all scan chains to shift data.

6. What is lockup latches? Why we need lockup latch? Write waveform?

Whenever clock domains crossing Tool will add automatically lockup latches between the flops.
Lockup latches will be present in the Shift path, not in capture path (Functional logic). Main
purpose of the lock up latch is to avoid hold violation. Need to interact with STA team regarding
the Timing violations. Based on timing violations we need to insert lockup latches on timing
paths. Scan chains are balanced and avoid extra post shift bits.

A scan lock-up latch is a retiming sequential cell on a scan path that can address skew problems
between adjacent scan cells when clock mixing or clock-edge mixing is enabled.

DFT Compiler inserts them to prevent skew problems that might occur.
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7. Why need terminal lockup latches?

Usually lockup to a functional register timing path will be with different clock. The
timing path to the lockup will be with same clock. This is since in our methodology we use to
add terminal lockup latch in the scan chains .when the partition was scan stitched, these were two
independent clocks so at this time lock up latch was inserted. At the chip level, these two
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different clocks were generated to the same scan clock. Thus we were getting lockup to
functional register paths also with the same clock.

8. How do you differentiate Shift and capture?

Scan-in involves shifting in and loading all the flip-flops with an input vector. Once the
sequence is loaded, one clock pulse (also called the capture pulse) is allowed to excite the
combinatorial logic block and the output is captured at the second flop.

9. What is the impact of having latches in the design?

The latch will add the difficulty of our controllability on the design. By having latches in
the design we can avoid hold violations that occurs in the shift and capture path. Whenever latch
is enabled it will pass whatever is there on its D inputs to Q output. If suppose any glitch is
coming on D and latch is enabled it will pass it to q. Glitch always create problem u would be
knowing this. Latches are fast, consumes less power, less area than Flops but Glitches can also
come along with these advantages, that’s why we go for flops. Also Latches are not DFT
friendly. It is very difficult to perform Static timing analysis with latches in your design.

10. Can latches be part of scan chains, explain?

Yes latches can be a part of scan chains .Latches are very often part of a scan chain, but
most commonly as "lock-up latches" that occur between clock domains, to guard against hold
time violations in scan shift mode.Mainly latches are added to avoid the skew problems. Setup
and hold problems can be solved. By inserting a negative level triggered latch (called as lock-up
latch) between the two flip-flops which had a significant difference in the clock latency between
the flops.

11. What are DRC Rules during scan insertion?

DRC is an acronym for design rules check and these rules are checked for any violations
during scan insertion process.

Majorly DRC rules is based on

Clock should be controllable from the top (clock pins)

Reset/Set/Preset should be inactive during shifting

The DRC rules checked during scan insertion are,

Pre DRC-Rules:

Need to check all clocks are defined properly

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Clocks always controllable, means clock should not derived from the flops output and
combo path

If any clock fixes from the DFT team, need to interact with STA for Timing checks.

As per guidelines, we shouldn’t modify the clock paths.

Resets

Test mode entry

Set of constraints

It should control through TDR (Test data register)

Post DRC Rules:

Clock rule violations: c1, c2, c6, c7

Data rule violations: d5, d6

Scan rule violation: s1, s2, s3

Contention rule violation: e4, e10

DRC rule impact:

Coverage: d1, e10, c7, a1, a7

No timing simulation: c3, c6

Timing simulation: Other common DRC rules: d5, d6

DRC severity: Error, Warning

12. What is Scan? What are the difference between full scan and partial Scan?

Scan chain is a technique used in design for testing. The objective is to make testing easier by
providing a simple way to set and observe every flip-flop in an IC. The basic structure of scan
include the following set of signals in order to control and observe the scan mechanism.

1. Scan in and scan out define the input and output of a scan chain. In a full scan mode
usually each input drives only one chain and scan out observe one as well.

2. A scan enable pin is a special signal that is added to a design. When this signal is
asserted, every flip-flop in the design is connected into a long shift register.
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3. Clock signal which is used for controlling all the FFs in the chain during shift phase and
the capture phase. An arbitrary pattern can be entered into the chain of flip-flops, and the
state of every flip-flop can be read out.

Full scan: all sequential cells are replaced by corresponding counter parts. Combinational ATPG
can be used. We can achieve full coverage through this scan type.

Partial scan: not all parts are replaced by corresponding counter parts. As because of this we
cannot achieve full coverage.

13. What are the benefits of scan?

Benefits of scan:

Highly automated process

High effective predictive method

Ease of use

Assured quality

14. What are the different scan styles? Explain each scan styles?

SCAN STYLES

▪ Multiplexed Flip-Flop Scan Style

▪ LSSD Style

▪ Clocked-Scan Scan Style

Multiplexed Flip-Flop Scan Style

The multiplexed flip-flop scan style uses a multiplexed data input to provide scan shift
capability. In functional mode, the scan-enable signal, acting as the multiplexer select line,
selects the system data input. During scan shift, the scan-enable signal selects the scan data input.
The scan data input comes from either the scan-input port or the scan-output pin of the previous
cell in the scan chain.

the following test pins are required on a multiplexed flip-flop equivalent cell:

Scan-input

Scan-enable

Scan-output
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Test pins are identified in the test cell group of the cell description in the logic library.

Multiplexed flip-flop is the scan style most commonly supported in logic libraries. Most libraries
provide multiplexed flip-flop equivalents for D flip-flops.

LSSD Scan Style

The master clock (CLKA) pulse precedes the slave clock (CLKB) pulse, and the clocks are non-
overlapping.
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Clocked-Scan Scan Style

The clocked-scan scan style uses a separate dedicated edge-triggered test clock to provide scan
shift capability. In functional mode, the system clock is active and system data is clocked into the
cell. During Scan shift, Test clock is active and scan data is clocked into the cell.

15. What are the scan methodology?

Scan methodologies are:

Full scan

Partial scan

Partition scan

16. What is scan chain and scan group?

Scan chain is a technique used in dft. The Technique where all flops are stitched together
like a shift register (one output is connected to input of next flop). The objective is to make
testing easier by providing a simple way to set and observe every flip flop in an IC. Scan in and
Scan out define the input and output of a scan chain.
In a full scan mode usually each input drives only one chain and scan out observe one as
well. A scan enable pin is a special signal that is added to a designScan group: when you
download new definitions, they are automatically added to the scan group. When a security scan
group has several sub groups to help you organize the definitions that are scanned for.
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17. Explain the scan flow?

 Synthesis netlist

 Read library files

 Apply scan constraints

 Scan tool commands

 DRC rules check

 Insert dft

 Post drc rules

 Dump all reports

 Review log files

 Scan inserted output netlist

 Atpg setup input files

 Scandef
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18. What is observability and controllability?

Controllability and observability are two important properties of state models which are to be
studied prior to designing a controller. 

Controllability: Controls over the each node (Shift mode)

Observability: Response of the each node (Capture mode)

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Controllability: deals with the possibility of forcing the system to a particular state by application
of a known control input. If a state is uncontrollable then no input will be able to control that
state.

Observability: On the other hand whether or not the initial states can be observed from the output
is determined using observability property. Thus if a state is not observable then the controller
will not be able to determine its behavior from the system output and hence not be able to use
that state to stabilize the system.

19. What is the use of Shift Enable & Test Mode signal?

The shift enable is used for shifting the data.

If Scan enable=1, Shift path i.e. dft path SI to Q path

Scan enable=0, Capture path i.e. functional path D to Q path.

The test signal is used if test mode pad =0 it is in functional mode (no shift or capture) and if test
mode pad=1 it is in dft mode

20. What are the inputs and outputs for Scan?

Inputs:

 Design – Netlist
 circuit set up (do file)
 library

Outputs:

 Scan inserted netlist ( SI to Q connection in the netlist , SE is connected to the top

level scan enable)
 ATPG Setup like do files and test proc for mentor, .still for
 ATPG test proc
 Scan DEF - which required physical team physical location for flops
 Reports
 Logs

21. How do you take care neg-edge flops during scan insertion?

Negative edge flop does not impact anything during scan insertion

But positive followed by negative edge flop impacts, since at the intersection of positive and
negative flop the data will not be captured. Since at single pulse data launch and capture is not
possible. We will require lock up latch to avoid old violations.
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22. If design having multiple clock domains, how do you take care during scan insertion?

We use clock mixing by lockup latch or combine domain wise based on pros and cons of
the design when we `have the multiple domains during scan insertion

23. What are the advantages and disadvantages clock mixing and no clock mixing during
scan stitching?

Clock mixing:

Advantages:

Scan chain is balanced, if scan has many chains cycles, shift in and shift out are used to equally
divided for better results.

 Tool will use lockup latches between clock domains.

 Lock up always in shift path not in capture path.

Disadvantages:

 Static timing analysis issue .STA will check timing on shift path

 Extra lockup latches added in the design.

No clock mixing:

Advantages:

 Static timing Analysis will be easy

 There is not lockup latches

Disadvantages:

 Scan chain is not balancing

 Additional post shift bits required
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24. What is top down and bottom up approach scan insertion?

Top-Down Approach

• Single DFT insertion operation at the top level of design. This flow is simple, but it requires
that DFT insertion be repeated for the entire design if any part of the design changes,

• A very large design that is not suitable for a single top-down DFT insertion

• Time-consuming for large designs

• Routing Congestion

Bottom Up Approach

▪ In bottom-up hierarchical scan synthesis, perform DFT insertion at a lower level of hierarchy,
then incorporate those completed scan structures into DFT insertion at a higher level of
hierarchy. HSS) flow.
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▪ Test models to represent core designs during top-level DFT operations, which improves tool
performance and capacity for multimillion-gate designs.

▪ Re-architect DFT structures in a block independently of its surrounding design logic

• Time-consuming is less for large designs

• Create a DFT-inserted block that can be reused in future designs

• Routing Congestion

25. Explain clock gating circuit with diagram? Why we need clock gating circuit?

Clock gating is a common technique for reducing clock power by shutting off the clock
to modules by a clock enable signal. Clock gating functionally requires only an AND or OR gate.
Consider you were using an AND gate with clock. The high EN edge may come anytime and
may not coincide with a clock edge. In that case the output of the AND gate will be a 1 for less
time than the clock’s duty cycle. You in turn end up with a glitch in your clock signal.

To avoid this, a special kind of clock gating cells are used, that synchronizes the EN with
a clock edge. These are call integrated clock gating cells or ICG.

There are two commonly used ICG cell types.

 Using AND gate with high EN

 The following design uses a negative edge triggered latch to synchronize the EN signal to the
CLK. The GCLK is available only when the latch o/p is high. GCLK is held low when EN is
low.

 Using OR gate with high EN

The following design uses a positive edge triggered latch. GCLK is held high when EN is low.
Note that the latch o/p is inverted at the OR input. Hence, the clock is passed through when this
i/p gets a low.
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26. What is link library and target library?

The target library specifies the name of the technology library that corresponds to the library
whose cells the designers want DC shell to infer and finally map to.

The link library defines the name of the library that refers to the library of cells used solely for
reference, i.e., cells in the link library are not inferred by DC shell.

For example, you may specify a standard cell technology library as the target library,
while specifying the pad technology library name and all other macros (RAMs, ROMs etc.) in
the link library list. This means that the user would synthesize the design that targets the cells
present in the standard cell library, while linking to the pads and macros that are instantiated in
the design. If the pad library is included in the target library list, then DC may use the pads to
synthesize the core logic. The target library name should also be included in the link library list.

27. If the entire design is a shift register, do you need scan insertion, explain ?

No ,if the entire design is shift register, we do not need scan insertion. In the chain if the
first flop is shift register only it will be converted to scan flop and the remaining flops are left as
it is.(Shift Register contain only flops no combinational logic is present in between flops, so
there is no need to convert all flops in a shift register)

28. Where are negative edge flops placed in the scan chains? Can negative edge flops be in
between the scan chains, if yes explain what precautions to be taken care?

Negative edge flops are placed in the first position in scan chains .If negative edge flops
are in between the scan chains, it leads to setup and hold violations. Since at the intersection of
positive and negative flop the data will not be captured. Since at single pulse data launch and
capture is not possible. We will require lock up latch. Therefore we have to add lockup latch to
avoid those violations

29. What is CTL and why need to use during scan insertion?
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HSS means hierarchical scan synthesis or bottom-up synthesis flow. This makes use of
the scan information of DFT inserted blocks as CTL model (core test language). For chip level
scan integration, instead of netlist we can use the CTL models.

SCANDEF files are used for scan chain reordering by back-end tools. It consists of stub
chains for reordering. In HSS flow by using CTL models, SCANDEF has sub block scan
segments as black boxes. Here we would only be able to perform repartitioning considering
segment as a whole. For reordering the cells in the segment, we can use '-expand elements'
option of 'write scan def' command.

30. If IP is already scan inserted, how do you take care during scan insertion?

If already scan inserted in vnc server if we going to use with existing we can run or else we can
remove the scan by rm scan insertion and then continue the process.

31. How do you decide number of scan chains for particular block?

Based on the external scan channels and compression ratio we decide the number of scan
chains for the particular block.

32. If multiple power domains in the design, how do you take during scan insertion?

If there are multiple power domains in the design, we take each power domain separately
and for each power domains we do scan insertion separately.