EDT INSERTION LAB OBSERVATIONS

Test Case 1: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
case1_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
case1_sa.dofile, case1_sa.testproc and create case1_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case1/EDT_RTL_GENERATION/
netlist/case1_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case1/EDT_RTL_GENERATION/dofile/c
ase1_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

analyze_compression

write_edt_files/hdd2/home/poojitha/compression/case1/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v
• ATPG Dofile
 DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

Two clock domains EDT clk, FastClk

3) How many resets?

One only is the Reset

4) Number of internal scan chains and external Scan Channel?

We have 4 scan chains to the design and 2 external scan channel

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

Totally 40 flops are scan flops, the non-scan flop are in the decompressor
and compressor why because there are unscanable blocks
8) Chain length?
Each scan chain having 10 scan flops

9) Number of DRC violations?

K13, E5
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 2: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
case2_scan.v
• ATPG Setup Dofiles ( Dofile and testproc file from scan inserted step)
case2_sa.dofile case2_sa.testproc and create case2_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case2/EDT_RTL_GENERATION/
netlist/case2_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case2/EDT_RTL_GENERATION/dofile/c
ase2_sa.dofile

set_edt_options -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_file/hdd2/home/poojitha/compression/case2/EDT_RTL_GENERATION
/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design has two clock domain FastClk, edt clk

3) How many resets?

The design has only one Reset

4) Number of internal scan chains and external Scan Channel?

We have 4 scan chains and 2 external scan channels

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

Totally 40 flops are scan flops, the non-scan flop are in the decompressor
and compressor why because there are unscanable blocks

8) Chain length?
Each chain having 10 scan flops

9) Number of DRC violations?

E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 4: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
case4_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
case4_sa.dofile, case4_sa.testproc and create case4_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case4/EDT_RTL_GENERATION/
netlist/case4_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case4/EDT_RTL_GENERATION/dofile/c
ase4_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case4/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design have two clock domain Clk, edt clk

3) How many resets?

The design have one reset Reset_

4) Number of internal scan chains and external Scan Channel?

The design have 2 scan chains, 2 external scan channels

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design have 18 scan flops, the non-scan flop are in the decompressor
and compressor why because there are unscanable blocks

8) Chain length?
One chain length is 10 scan flops
Another chain length is 8 scan flops
9) Number of DRC violations?
E5, K13

10) How many mask registers, hold registers?

Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 5: -
Problem Definition: -
Input:-
• Scan inserted Netlist
Case5_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case5_sa.dofile, case5_sa.testproc and create case5_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case5/EDT_RTL_GENERATION/
netlist/case5_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case5/EDT_RTL_GENERATION/dofile/c
ase5_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case5/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design has 3 clock domains ProcClk, FastClk, edt clk

3) How many resets?

The design has one reset [Reset]

4) Number of internal scan chains and external Scan Channel?

In this design 2 scan chains and 2 external scan channels

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

There are 54 flops in the design are scanflops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
One chain length is 28 scan flops
Another chain length is 26 scan flops
9) Number of DRC violations?
E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 6: -
Problem Definition: -
Input:-
• Scan inserted Netlist
Case6_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case6_sa.dofile, case6_sa.testproc and create case6_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case6/EDT_RTL_GENERATION/
netlist/case6_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case6/EDT_RTL_GENERATION/dofile/c
ase6_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case6/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design has two clock domain BIST_CLK, edt clk

3) How many resets?

The design has only one reset is MBIST_RST_L

4) Number of internal scan chains and external Scan Channel?

The design has 3 scan chains, 2 external scan channel

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

In this have102 flops are scan flops , the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
Each has scan chain consist of 34 flops

9) Number of DRC violations?

E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case7: -
Problem Definition: -
Input:-
• Scan inserted Netlist
Case7_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case7_sa.dofile, case7_sa.testproc and create case7_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case7/EDT_RTL_GENERATION/
netlist/case7_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case7/EDT_RTL_GENERATION/dofile/c
as7_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case7/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design has two clock domain Clk, edt clk

3) How many resets?

The design has reset which is turned ON in the netlist itself

4) Number of internal scan chains and external Scan Channel?

The design has 2 scan chains, 2 external scan channels

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

Totally 14 flops are scan flops, the non-scan flop are in the decompressor
and compressor why because there are unscanable blocks

8) Chain length?
Each scan chain having 7 scan flops
9) Number of DRC violations?
E5, K13

10) How many mask registers, hold registers?

Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case8: -
Problem Definition: -
Input:-
• Scan inserted Netlist
Case8_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case8_sa.dofile, case8_sa.testproc and create case8_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case8/EDT_RTL_GENERATION/
netlist/case8_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case8/EDT_RTL_GENERATION/dofile/c
as8_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case8/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design has two clock domain sysclk,edt clk

3) How many resets?

The design has only one reset is reset1

4) Number of internal scan chains and external Scan Channel?

The design having 2scan chains and 2external scan channel

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

82 flops and all are scan flops, the non-scan flop are in the decompressor and
compressor why because there are unscanable blocks

8) Chain length?
Each scan chain having 41 scan flops

9) Number of DRC violations?

E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 9: -
Problem Definition: -
Input:-
• Scan inserted Netlist
Case9_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case9_sa.dofile, case9_sa.testproc and create case9_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case9/EDT_RTL_GENERATION/
netlist/case9_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case9/EDT_RTL_GENERATION/dofile/c
as9_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case9/EDT_RTL_GENERATIO
N/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design has two clock domain clk, edt clk

3) How many resets?

The design has reset which is already turned ON in scan

4) Number of internal scan chains and external Scan Channel?

The design has 2 scan chains and 2 external scan chains

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 77 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
One chain length is 39 scan flops
Another chain length is 38 scan flops
9) Number of DRC violations?
E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case10: -
Problem Definition: -
Inputs: -
Input:-
• Scan inserted Netlist
Case10_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case10_sa.dofile, case10_sa.testproc and create case10_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case10/EDT_RTL_GENERATION
/netlist/case10_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case10/EDT_RTL_GENERATION/dofile
/cas10_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case10/EDT_RTL_GENERATI
ON/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
 DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design consist of 4 clock domains rx_clk, tx_clk, clk_sys, edt clk

3) How many resets?

The design consist of two reset (but only one reset is connected to the flops
of block-2 so we are going to use only one reset is tx_rst in scan)

4) Number of internal scan chains and external Scan Channel?

The design has 4 scan chains and 2 external scan channel

5) Is it top-down or bottom up approach?

Bottom-up approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 77 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
each chain length having 53 scan flops
9) Number of DRC violations?
E5, K13

10) How many mask registers, hold registers?

Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X- decoder are used
Test Case 11: -
Problem Definition: -
Inputs:-
• Scan inserted Netlist
Case11_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case11_sa.dofile, case11_sa.testproc and create case11_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case11/EDT_RTL_GENERATION
/netlist/case11_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case11/EDT_RTL_GENERATION/dofile
/cas11_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case11/EDT_RTL_GENERATI
ON/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

The design have two clock domains tx_clk, edt clk

3) How many resets?

There is No reset

4) Number of internal scan chains and external Scan Channel?

The design having 4 scan chains and 2 external scan channel

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 187 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
The first three chains are 38 scan flops and fourth chain having 37 scan flops
9) Number of DRC violations?
D5, E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 12A: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
Case12_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case12a_sa.dofile, case12a_sa.testproc and create case12a_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case12/case12a/EDT_RTL_GENE
RATION/netlist/case12_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case12/case12a/EDT_RTL_GENERATIO
N/dofile/cas12a_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case12/case12a/EDT_RTL_GEN
ERATION/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def

Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

There were 4 clock domains in the design FastClk, ProcClk, St81, edt clk

3) How many resets?

The design have only one reset is Reset

4) Number of internal scan chains and external Scan Channel?

The design having 4 scan chain and 2 external scan channel

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 128 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
It have 4 chains of length [7, 41, 17, 63]

9) Number of DRC violations?

C8 & C9, D5 & D7, E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 12B: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
Case12_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case12b_sa.dofile, case12b_sa.testproc and create case12b_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case12/case12b/EDT_RTL_GENE
RATION/netlist/case12_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case12/case12b/EDT_RTL_GENERATIO
N/dofile/cas12b_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case12/case12b/EDT_RTL_GEN
ERATION/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def
Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

There were 4 clock domains in the design FastClk, ProcClk, St81, edt clk

3) How many resets?

The design have only one reset [Reset]

4) Number of internal scan chains and external Scan Channel?

2 scan chains and 2 scan external channels to the design

5) Is it top-down or bottom up approach?

Top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 128 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
It have 2 chains of length [7,121]

9) Number of DRC violations?

C8 & C9, D5 & D7, E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 12C: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
Case12_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case12c_sa.dofile, case12c_sa.testproc and create case12c_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case12/case12c/EDT_RTL_GENE
RATION/netlist/case12_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case12/case12c/EDT_RTL_GENERATIO
N/dofile/cas12c_sa.dofile

set_edt_option -input_channels 1 -output_channel 1 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case12/case12c/EDT_RTL_GEN
ERATION/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def
Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

There were 4 clock domains in the design FastClk, ProcClk, St81, edt clk

3) How many resets?

The design have only one reset [Reset]

4) Number of internal scan chains and external Scan Channel?

2 scan chains and 1 scan external channels to the design

5) Is it top-down or bottom up approach?

top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 128 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
It have 1 chains of length 128

9) Number of DRC violations?

C8 & C9, D5 & D7, E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used
Test Case 12D: -
Problem Definition: -
Inputs: -
• Scan inserted Netlist
Case12_scan.v
• ATPG Setup Dofiles (Dofile and testproc file from scan inserted step)
Case12d_sa.dofile, case12d_sa.testproc and create case12d_edt.dofile
• Library Model
tsmc13.mdt
• Dofile commands
set_context dft -edt

read_verilog/hdd2/home/poojitha/compression/case12/case12d/EDT_RTL_GENE
RATION/netlist/case12_scan.v

read_cell_library /hdd2/home/poojitha/scan_insertion/library/atpg/tsmc13.mdt

set_current_design

dofile/hdd2/home/poojitha/compression/case12/case12d/EDT_RTL_GENERATIO
N/dofile/cas12d_sa.dofile

set_edt_option -input_channels 2 -output_channel 2 -location internal

set_system_mode analysis

write_edt_files/hdd2/home/poojitha/compression/case12/case12d/EDT_RTL_GEN
ERATION/output/DmaWr -verilog -replace

Outputs: -
• EDT inserted Netlist
DmaWr_edt_top_gate.v
DmaWr_edt_top_rtl.v
DmaWr_edt.v

• ATPG Dofile
DmaWr_bypass.dofile
DmaWr_edt.dofile
• ATPG Testproc
DmaWr_edt.testproc
DmaWr_bypass.testproc
• Scan Def
Observations: -
1) Write block diagram with all DFT inputs?

2) How many clock domains?

There were 4 clock domains in the design FastClk, ProcClk, St81, edt clk

3) How many resets?

The design have only one reset [Reset]

4) Number of internal scan chains and external Scan Channel?

2 scan chains and 2 scan external channels to the design

5) Is it top-down or bottom up approach?

Top-down approach

6) How many terminal lockup latches are added?

There are no terminal lockup latches in edt block

7) Number of scan flops and non-scan flops in the design?

The design has 128 flops and all are scan flops, the non-scan flop are in the
decompressor and compressor why because there are unscanable blocks

8) Chain length?
It have 4 chains of length [7,41,40,40]

9) Number of DRC violations?

C8 & C9, D5 & D7, E5, K13
10) How many mask registers, hold registers?
Mask registers are 2
Hold registers are 2

11) Basic decoder or X-Decoder?

X-decoder are used