Ch.

5 Processing Unit Design

page 83

lec4
 2.4. Programming Examples

• This is done in order to emphasize the

understanding of how to use different
addressing modes in performing different
operations independent of the machine used.
• Example 1: In this example, we would like to
show a program segment that can be used to
perform the task of adding 100 numbers stored
at consecutive memory locations starting at
location 1000.

2
• The results should be stored in memory
location 2000.
• In this example, use has been made of
immediate (MOVE #100, R1) and indexed
(ADD 1000(R2), R0) addressing.
3
• As can be seen, a given task can be performed
using more than one programming
methodology. The method used by the
programmer depends on his/her experience

4
• Example 3 This example illustrates the use of
a subroutine, SORT, to sort N values in
ascending order (Fig. 2.13).
• The numbers are originally stored in a list
starting at location 1000.
• The sorted values are also stored in the
same list and again starting at location 1000.
• The subroutine sorts the data using the
well-known “Bubble Sort” technique.
• The content of register R3 is checked at the
end of every loop to find out whether the
list is sorted or not.

5
6
• Example 4 This example illustrates the use of
a subroutine, SEARCH, to search for a value
VAL in a list of N values (Fig. 2.14).
• We assume that the list is not originally
sorted and therefore a brute force search is
used.
• In this search, the value VAL is compared with
every element in the list from top to bottom.
• The content of register R3 is used to indicate
whether VAL was found.7
8
• Example 5 This example illustrates the use of a
subroutine, SEARCH, to search for a value VAL
in a list of N values (as in Example 4) (Fig.
2.15). Here, we make use of the stack to send
the parameters VAL and N.

9
10
 In this lecture
– 5.1. CPU Basics 83
– 5.2. Register Set 85
 5.1. CPU Basics… 83

A typical CPU has

three major
The primary
components:
function of the CPU
(1)Register set, is to execute a set
(2)Arithmetic logic of instructions
unit (ALU), and stored in the
(3)Control unit computer’s
(CU). memory.
The register set differs from one
computer architecture to another. It is
usually a combination of :
1. General-purpose registers are
used for any purpose, hence the
name general purpose.
2. Special-purpose registers have
specific functions within the CPU.
1. For example, the program
counter (PC) is a special-
purpose register that is used
to hold the address of the
instruction to be executed
next.
2. Another example of special-
purpose registers is the
instruction register (IR), which
is used to hold the instruction
that is currently executed.
The ALU provides the
circuitry needed to
perform the arithmetic,
logical and shift
operations demanded of
the instruction set.
The control unit is the entity
responsible for fetching the
instruction to be executed from
the main memory and
decoding and then executing it.
Simple execution cycle
A typical and simple execution cycle can be summarized
as follows:
1. The next instruction to be executed, whose address is
obtained from the PC, is fetched from the memory and
stored in the IR.
2. The instruction is decoded.
3. Operands are fetched from the memory and stored in
CPU registers, if needed.
4. The instruction is executed.
5. Results are transferred from CPU registers to the
memory, if needed.
PC: next ins. Addr.
Fetch mem[ ins.]

Store ins. into IR

Decode ins.

Fetch operands
Move them to Ri

Execute ins.

Store result in Mem.

• The execution cycle is repeated as long as there are
more instructions to execute.
• A check for pending interrupts is usually included in
the cycle.
– Examples of interrupts include I/O device request,
arithmetic overflow, or a page fault.
• When an interrupt request is encountered, a transfer
to an interrupt handling routine takes place.
– Interrupt handling routines are programs that are invoked
to collect the state of the currently executing program,
correct the cause of the interrupt, and restore the state of
the program.
• The actions of the CPU during an execution cycle are
defined by micro-orders issued by the control unit.
• These micro-orders are individual control signals sent
over dedicated control lines.
– For example, let us assume that we want to execute an
instruction that moves the contents of register X to
register Y.
– Let us also assume that both registers are connected to
the data bus, D.
– The control unit will issue a control signal to tell register X
to place its contents on the data bus D. After some delay,
another control signal will be sent to tell register Y to read
from data bus D.
• The activation of the control signals is determined
using either hardwired control or microprogramming.
5.2. Register Set ..pg85
• Registers are essentially extremely fast memory locations
within the CPU that are used to create and store the
results of CPU operations and other calculations.
• Different computers have different register sets.
– They differ in the number of registers,
– register types, and the length of each register.
• They also differ in the usage of each register.
– General-purpose registers can be used for multiple purposes and assigned to
a variety of functions by the programmer.
– Special-purpose registers are restricted to only specific functions.
• Another type of registers is used to hold processor status
bits, or flags.
– These bits are set by the CPU as the result of the execution of
an operation. The status bits can be tested at a later time as
part of another operation.
• In some cases, some registers are used only to hold data
and cannot be used in the calculations of operand
addresses.
• The length of a data register must be long enough to hold
values of most data types.
– Some machines allow two contiguous registers to hold
double-length values.
• Address registers
– may be dedicated to a particular addressing mode or may be
used as address general purpose.
– Address registers must be long enough to hold the largest
address.
• The number of registers in a particular architecture
affects the instruction set design.
• A very of registers may result in an increase in memory
references.
 5.2.1. Memory Access Registers
• Two registers are essential in memory write and read
operations: the memory data register (MDR) and
memory address register (MAR). The MDR and MAR
are used exclusively by the CPU and are not directly
accessible to programmers.
• In order to perform a write operation into a specified
memory location, the MDR and MAR are used as
follows:
– 1. The word to be stored into the memory location is first
loaded by the CPU into MDR.
– 2. The address of the location into which the word is to be
stored is loaded by the CPU into a MAR.
– 3. A write signal is issued by the CPU.
• Similarly, to perform a memory read
operation, the MDR and MAR are used as
follows:
– 1. The address of the location from which the
word is to be read is loaded into the MAR.
– 2. A read signal is issued by the CPU.
– 3. The required word will be loaded by the
memory into the MDR ready for use by the CPU.
5.2.2. Instruction Fetching Registers
• Two main registers are involved in fetching an
instruction for execution: the program counter (PC)
and the instruction register (IR).
• The PC is the register that contains the address of
the next instruction to be fetched.
• The fetched instruction is loaded in the IR for
execution.
• After a successful instruction fetch, the PC is
updated to point to the next instruction to be
executed.
• In the case of a branch operation, the PC is updated
to point to the branch target instruction after the
branch is resolved, that is, the target address is
known.
 5.2.3. Condition Registers
• Condition registers, or flags, are used to maintain
status information.
• Some architectures contain a special program status
word (PSW) register.
• The PSW contains bits that are set by the CPU to
indicate the current status of an executing program.
• These indicators are typically for
– arithmetic operations,
– interrupts,
– memory protection information,
– or processor status.
 5.2.4. Special-Purpose Address Registers

Index Register
• Index Register, the address of the operand is
obtained by adding a constant to the content of a
register, called the index register.
• The index register holds an address displacement.
• Index addressing is indicated in the instruction by
including the name of the index register in
parentheses and using the symbol X to indicate
the constant to be added.
Segment Pointer

• Segment Pointers As we will discuss later, in

order to support segmentation, the address
issued by the processor should consist of a
segment number (base) and a displacement
(or an offset) within the segment.
• A segment register holds the address of the
base of the segment.
Stack Pointer Register
• A specific register, called the stack pointer
(SP), is used to indicate the stack location that
can be addressed.
• In the stack push operation, the SP value is
used to indicate the location (called the top of
the stack).
• After storing (pushing) this value, the SP is
incremented (in some architectures, e.g. X86,
the SP is decremented as the stack grows low
in memory).
 5.2.5. 80386 Registers
• the Intel basic programming model of the 386,
486, and the Pentium consists of three register
groups.
1. These are the general-purpose registers,
2. the segment registers,
3. and the instruction pointer (program counter) and
the flag register. Figure 5.2 (which repeats Fig. 3.6)
shows the three sets of registers.
• The first set consists of general purpose
registers A, B, C, D, SI (source index), DI
(destination index), SP (stack pointer), and BP
(base pointer).
• The second set of registers consists of CS
(code segment), SS (stack segment), and four
data segment registers DS, ES, FS, and GS.
•
• The third set of registers consists of the instruction pointer
(program counter) and the flags (status) register.
• Among the status bits, the first five are identical to those
bits introduced as early as in the 8085 8-bit microprocessor.
• The next 6–11 bits are identical to those introduced in the
8086.
• The flags in the bits 12–14 were introduced in the 80286
while the 16–17 bits were introduced in the 80386.
• The flag in bit 18 was introduced in the 80486.
 5.2.6. MIPS Registers

• MIPS is a load-store architecture, which

means that only load and store instructions
can access memory.
• Table 5.1 lists the registers and describes their
intended use. Refer page 88
• The MIPS CPU contains 32 general-purpose
registers that are numbered 0–31.
• Register x is designated by $x.
• Register $zero always contains the hardwired
value 0.
• Registers $at (1), $k0 (26), and $k1 (27) are
reserved for use by the assembler and
operating system.
• Registers $a0–$a3 (4–7) are used to pass the
first four arguments to routines
• (remaining arguments are passed on the stack). Registers $v0 and
$v1 (2, 3) are used to return values from functions.
• Registers $t0–$t9 (8–15, 24, 25) are caller-saved registers used for
temporary quantities that do not need to be preserved across calls.
• Registers $s0–$s7 (16–23) are caller-saved registers that hold long-
lived values that should be preserved across calls.
• Register $sp(29) is the stack pointer, which points to the last
location in use on the stack.
• Register $fp(30) is the frame pointer. Register $ra(31) is written
with the return address for a function call.
• Register $gp(28) is a global pointer that points into the middle of a
64 K block of memory in the heap that holds constants and global
variables. The objects in this heap can be quickly accessed with a
single load or store instruction.
The END